diff --git a/patch/kernel/rockchip-dev/9005_DTS_IOMMU_IEP_ISP.patch b/patch/kernel/rockchip-dev/9005_DTS_IOMMU_IEP_ISP.patch
new file mode 100644
index 000000000..50e61198e
--- /dev/null
+++ b/patch/kernel/rockchip-dev/9005_DTS_IOMMU_IEP_ISP.patch
@@ -0,0 +1,199 @@
+diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
+index 3896506..a6c0ec1 100644
+--- a/arch/arm/boot/dts/rk3288-miniarm.dts
++++ b/arch/arm/boot/dts/rk3288-miniarm.dts
+@@ -642,7 +642,6 @@
+ };
+ 
+ &usb_host0_ehci {
+-	no-relinquish-port;
+ 	status = "okay";
+ };
+ 
+@@ -684,7 +683,22 @@
+ 	status = "okay";
+ };
+ 
++&hevc_mmu {
++	status = "okay";
++};
++
+ &vpu_service {
+ 	status = "okay";
+ };
+ 
++&vpu_mmu {
++	status = "okay";
++};
++
++&iep_mmu {
++	status = "okay";
++};
++
++&isp_mmu {
++	status = "okay";
++};
+\ No newline at end of file
+diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
+index 83bb2a2..52ec00c 100644
+--- a/arch/arm/boot/dts/rk3288-miqi.dts
++++ b/arch/arm/boot/dts/rk3288-miqi.dts
+@@ -588,3 +588,20 @@
+ &vpu_service {
+ 	status = "okay";
+ };
++
++&hevc_mmu {
++	status = "okay";
++};
++
++&vpu_mmu {
++	status = "okay";
++};
++
++&iep_mmu {
++	status = "okay";
++};
++
++&isp_mmu {
++	status = "okay";
++};
++
+diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
+index 624416f..cfa5178 100644
+--- a/arch/arm/boot/dts/rk3288.dtsi
++++ b/arch/arm/boot/dts/rk3288.dtsi
+@@ -958,16 +958,31 @@
+ 		compatible = "rockchip,rk3288-rga";
+ 		reg = <0xff920000 0x180>;
+ 		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "rga";
+ 		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+ 		clock-names = "aclk", "hclk", "sclk";
+ 		power-domains = <&power RK3288_PD_VIO>;
+ 		resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
+-
+ 		reset-names = "core", "axi", "ahb";
++	};
++
++	iep_mmu: iommu@ff900800 {
++		compatible = "rockchip,iommu";
++		reg = <0xff900800 0x40>;
++		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "iep_mmu";
++		#iommu-cells = <0>;
+ 		status = "disabled";
+ 	};
+ 
++	isp_mmu: iommu@ff914000 {
++		compatible = "rockchip,iommu";
++		reg = <0xff914000 0x100>, <0xff915000 0x100>;
++		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "isp_mmu";
++		#iommu-cells = <0>;
++		rockchip,disable-mmu-reset;
++		status = "disabled";
++	};
+ 
+ 	vopb: vop@ff930000 {
+ 		compatible = "rockchip,rk3288-vop";
+@@ -999,6 +1014,11 @@
+ 				reg = <2>;
+ 				remote-endpoint = <&mipi_in_vopb>;
+ 			};
++
++			vopb_out_lvds: endpoint@3 {
++				reg = <3>;
++				remote-endpoint = <&lvds_in_vopb>;
++			};			
+ 		};
+ 	};
+ 
+@@ -1042,6 +1062,11 @@
+ 				reg = <2>;
+ 				remote-endpoint = <&mipi_in_vopl>;
+ 			};
++
++			vopl_out_lvds: endpoint@3 {
++				reg = <3>;
++				remote-endpoint = <&lvds_in_vopl>;
++			};
+ 		};
+ 	};
+ 
+@@ -1083,6 +1108,39 @@
+ 		};
+ 	};
+ 
++	lvds: lvds@ff96c000 {
++		compatible = "rockchip,rk3288-lvds";
++		reg = <0xff96c000 0x4000>;
++		clocks = <&cru PCLK_LVDS_PHY>;
++		clock-names = "pclk_lvds";
++		pinctrl-names = "lcdc";
++		pinctrl-0 = <&lcdc_ctl>;
++		power-domains = <&power RK3288_PD_VIO>;
++		rockchip,grf = <&grf>;
++		status = "disabled";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			lvds_in: port@0 {
++				reg = <0>;
++
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				lvds_in_vopb: endpoint@0 {
++					reg = <0>;
++					remote-endpoint = <&vopb_out_lvds>;
++				};
++				lvds_in_vopl: endpoint@1 {
++					reg = <1>;
++					remote-endpoint = <&vopl_out_lvds>;
++				};
++			};
++		};
++	};
++
+ 	edp: dp@ff970000 {
+ 		compatible = "rockchip,rk3288-dp";
+ 		reg = <0xff970000 0x4000>;
+@@ -1183,8 +1241,8 @@
+ 		reg = <0xff9a0800 0x100>;
+ 		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "vpu_mmu";
+-		power-domains = <&power RK3288_PD_VIDEO>;
+ 		#iommu-cells = <0>;
++		status = "disabled";
+ 	};
+ 
+ 	hevc_service: hevc-service@ff9c0000 {
+@@ -1224,8 +1282,8 @@
+ 		reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
+ 		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "hevc_mmu";
+-		power-domains = <&power RK3288_PD_HEVC>;
+ 		#iommu-cells = <0>;
++		status = "disabled";
+ 	};
+ 
+ 
+@@ -1926,5 +1984,15 @@
+ 				rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
+ 			};
+ 		};
++
++		lcdc {
++			lcdc_ctl: lcdc-ctl {
++				rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
++						<1 25 RK_FUNC_1 &pcfg_pull_none>,
++						<1 26 RK_FUNC_1 &pcfg_pull_none>,
++						<1 27 RK_FUNC_1 &pcfg_pull_none>;
++			};
++		};
++
+ 	};
+ };