mirror of
https://github.com/Fishwaldo/build.git
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Many changes for rk322x target:
- Chanaged default x.org configuration to disable glamor - Reintroduce patch to use DRM cursor plane as overlay in rk322x-current and -dev - Updated wifi patches for kernel 5.8.10 - Bumped rk322x to u-boot v2020.07, removed reserved zones from device trees - Updated OPTEE to v3.10, using ddrbin v1.10 - Bumped rk322x-current to kernel 5.8.y - Imported new patches from knaerzche's LibreELEC fork for rk322x-dev (kernel 5.8.y) - Adjusted existing patches to match changes, updated rk322x-dev kernel config file - Add default modprobe conf file for esp8089 to force the crystal frequency to 40Mhz for rk322x targets - Removed ssv6051 firmware packages to move to armbian-firmware repository - Switching ssv6051-wifi.cfg to /lib/firmware for rk322x-legacy - Removed P2P interface for esp8089 driver for rk322x-legacy - Optimized ssv6051 performance: kernel module gains -Os flag, disabled p2p interface, enabled HW crypto for CCMP cipher - Enabled remote control interface, IR GPIO kernel module and HDMI CEC modules
This commit is contained in:
paolo
parent
7b6920a25f
commit
bd17d4dbd0
70 changed files with 66037 additions and 21218 deletions
3987
patch/kernel/rk322x-current/01-linux-0001-rockchip-from-5.9.patch
Normal file
3987
patch/kernel/rk322x-current/01-linux-0001-rockchip-from-5.9.patch
Normal file
File diff suppressed because it is too large
Load diff
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@ -0,0 +1,434 @@
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From 9d29c5e2f20a44575a5a0e483319682d62daa4b3 Mon Sep 17 00:00:00 2001
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From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
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Date: Wed, 29 Jan 2020 17:38:19 +0100
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Subject: [PATCH] clk: rockchip: convert rk3399 pll type to use
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readl_relaxed_poll_timeout
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Instead of open coding the polling of the lock status, use the handy
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readl_relaxed_poll_timeout for this. As the pll locking is normally
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blazingly fast and we don't want to incur additional delays, we're
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not doing any sleeps similar to for example the imx clk-pllv4
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and define a very safe but still short timeout of 1ms.
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Suggested-by: Stephen Boyd <sboyd@kernel.org>
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Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
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Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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Link: https://lore.kernel.org/r/20200129163821.1547295-1-heiko@sntech.de
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(cherry picked from commit bf4237a188f872e535de8cbfc7903c1387b83b01)
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---
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drivers/clk/rockchip/clk-pll.c | 23 ++++++++++++-----------
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1 file changed, 12 insertions(+), 11 deletions(-)
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diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
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index 10560d963baf..28b04aad31ad 100644
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--- a/drivers/clk/rockchip/clk-pll.c
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+++ b/drivers/clk/rockchip/clk-pll.c
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@@ -589,19 +589,20 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
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static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
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{
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u32 pllcon;
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- int delay = 24000000;
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+ int ret;
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- /* poll check the lock status in rk3399 xPLLCON2 */
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- while (delay > 0) {
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- pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
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- if (pllcon & RK3399_PLLCON2_LOCK_STATUS)
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- return 0;
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+ /*
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+ * Lock time typical 250, max 500 input clock cycles @24MHz
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+ * So define a very safe maximum of 1000us, meaning 24000 cycles.
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+ */
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+ ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
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+ pllcon,
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+ pllcon & RK3399_PLLCON2_LOCK_STATUS,
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+ 0, 1000);
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+ if (ret)
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+ pr_err("%s: timeout waiting for pll to lock\n", __func__);
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- delay--;
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- }
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-
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- pr_err("%s: timeout waiting for pll to lock\n", __func__);
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- return -ETIMEDOUT;
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+ return ret;
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}
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static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
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From afe54d66a661ce9d99250431f1371e46f9b6d8a5 Mon Sep 17 00:00:00 2001
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From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
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Date: Wed, 29 Jan 2020 17:38:20 +0100
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Subject: [PATCH] clk: rockchip: convert basic pll lock_wait to use
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regmap_read_poll_timeout
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Instead of open coding the polling of the lock status, use the
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handy regmap_read_poll_timeout for this. As the pll locking is
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normally blazingly fast and we don't want to incur additional
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delays, we're not doing any sleeps similar to for example the imx
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clk-pllv4 and define a very safe but still short timeout of 1ms.
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Suggested-by: Stephen Boyd <sboyd@kernel.org>
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Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
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Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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Link: https://lore.kernel.org/r/20200129163821.1547295-2-heiko@sntech.de
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(cherry picked from commit 3507df1a4615113ae6509e0f14f6546f0d1c84b4)
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---
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drivers/clk/rockchip/clk-pll.c | 21 ++++++---------------
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1 file changed, 6 insertions(+), 15 deletions(-)
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diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
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index 28b04aad31ad..945f8b2cacc1 100644
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--- a/drivers/clk/rockchip/clk-pll.c
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+++ b/drivers/clk/rockchip/clk-pll.c
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@@ -86,23 +86,14 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
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{
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struct regmap *grf = pll->ctx->grf;
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unsigned int val;
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- int delay = 24000000, ret;
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-
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- while (delay > 0) {
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- ret = regmap_read(grf, pll->lock_offset, &val);
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- if (ret) {
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- pr_err("%s: failed to read pll lock status: %d\n",
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- __func__, ret);
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- return ret;
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- }
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+ int ret;
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- if (val & BIT(pll->lock_shift))
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- return 0;
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- delay--;
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- }
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+ ret = regmap_read_poll_timeout(grf, pll->lock_offset, val,
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+ val & BIT(pll->lock_shift), 0, 1000);
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+ if (ret)
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+ pr_err("%s: timeout waiting for pll to lock\n", __func__);
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- pr_err("%s: timeout waiting for pll to lock\n", __func__);
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- return -ETIMEDOUT;
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+ return ret;
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}
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/**
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From 9a37c781854b2cc475aced9045ba8c35b6838f3a Mon Sep 17 00:00:00 2001
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From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
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Date: Wed, 29 Jan 2020 17:38:21 +0100
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Subject: [PATCH] clk: rockchip: convert rk3036 pll type to use internal lock
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status
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The rk3036 pll type exposes its lock status in both its pllcon registers
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as well as the General Register Files. To remove one dependency convert
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it to the "internal" lock status, similar to how rk3399 handles it.
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Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
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Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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Link: https://lore.kernel.org/r/20200129163821.1547295-3-heiko@sntech.de
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(cherry picked from commit 7f6ffbb885d147557bdca471c37b7b1204005798)
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---
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drivers/clk/rockchip/clk-pll.c | 26 +++++++++++++++++++++++---
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1 file changed, 23 insertions(+), 3 deletions(-)
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diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
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index 945f8b2cacc1..4c6c9167ef50 100644
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--- a/drivers/clk/rockchip/clk-pll.c
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+++ b/drivers/clk/rockchip/clk-pll.c
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@@ -12,6 +12,7 @@
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/clk-provider.h>
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+#include <linux/iopoll.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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#include "clk.h"
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@@ -109,12 +110,31 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
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#define RK3036_PLLCON1_REFDIV_SHIFT 0
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#define RK3036_PLLCON1_POSTDIV2_MASK 0x7
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#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
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+#define RK3036_PLLCON1_LOCK_STATUS BIT(10)
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#define RK3036_PLLCON1_DSMPD_MASK 0x1
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#define RK3036_PLLCON1_DSMPD_SHIFT 12
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+#define RK3036_PLLCON1_PWRDOWN BIT(13)
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#define RK3036_PLLCON2_FRAC_MASK 0xffffff
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#define RK3036_PLLCON2_FRAC_SHIFT 0
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-#define RK3036_PLLCON1_PWRDOWN (1 << 13)
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+static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
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+{
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+ u32 pllcon;
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+ int ret;
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+
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+ /*
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+ * Lock time typical 250, max 500 input clock cycles @24MHz
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+ * So define a very safe maximum of 1000us, meaning 24000 cycles.
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+ */
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+ ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
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+ pllcon,
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+ pllcon & RK3036_PLLCON1_LOCK_STATUS,
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+ 0, 1000);
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+ if (ret)
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+ pr_err("%s: timeout waiting for pll to lock\n", __func__);
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+
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+ return ret;
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+}
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static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
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struct rockchip_pll_rate_table *rate)
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@@ -212,7 +232,7 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
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writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
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/* wait for the pll to lock */
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- ret = rockchip_pll_wait_lock(pll);
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+ ret = rockchip_rk3036_pll_wait_lock(pll);
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if (ret) {
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pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
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__func__);
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@@ -251,7 +271,7 @@ static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
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writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
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pll->reg_base + RK3036_PLLCON(1));
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- rockchip_pll_wait_lock(pll);
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+ rockchip_rk3036_pll_wait_lock(pll);
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return 0;
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}
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From 4e8605e139b42a4b239339fc54016ef2d0704908 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@collabora.com>
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Date: Tue, 2 Jun 2020 10:06:43 +0200
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Subject: [PATCH] clk: rockchip: Handle clock tree for rk3288w variant
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The revision rk3288w has a different clock tree about "hclk_vio"
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clock, according to the BSP kernel code.
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This patch handles this difference by detecting which device-tree
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we are using. If it is a "rockchip,rk3288-cru", let's register
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the clock tree as it was before. If the device-tree node is
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"rockchip,rk3288w-cru", we will apply the difference with this
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version of this SoC.
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Noticed that this new device-tree compatible must be handled in
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bootloader such as u-boot.
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|
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Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
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Link: https://lore.kernel.org/r/20200602080644.11333-2-mylene.josserand@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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(cherry picked from commit 1627f683636df70fb25358b0a7b39a24e8fce5bf)
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---
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drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++--
|
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1 file changed, 18 insertions(+), 2 deletions(-)
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|
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diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
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index cc2a177bbdbf..204976e2d0cb 100644
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--- a/drivers/clk/rockchip/clk-rk3288.c
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+++ b/drivers/clk/rockchip/clk-rk3288.c
|
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@@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
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COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
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RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
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RK3288_CLKGATE_CON(3), 0, GFLAGS),
|
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- DIV(0, "hclk_vio", "aclk_vio0", 0,
|
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- RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
|
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COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3288_CLKGATE_CON(3), 2, GFLAGS),
|
||||
@@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
||||
INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
|
||||
};
|
||||
|
||||
+static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
|
||||
+ DIV(0, "hclk_vio", "aclk_vio1", 0,
|
||||
+ RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
|
||||
+};
|
||||
+
|
||||
+static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
|
||||
+ DIV(0, "hclk_vio", "aclk_vio0", 0,
|
||||
+ RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
|
||||
+};
|
||||
+
|
||||
static const char *const rk3288_critical_clocks[] __initconst = {
|
||||
"aclk_cpu",
|
||||
"aclk_peri",
|
||||
@@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
|
||||
RK3288_GRF_SOC_STATUS1);
|
||||
rockchip_clk_register_branches(ctx, rk3288_clk_branches,
|
||||
ARRAY_SIZE(rk3288_clk_branches));
|
||||
+
|
||||
+ if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
|
||||
+ rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
|
||||
+ ARRAY_SIZE(rk3288w_hclkvio_branch));
|
||||
+ else
|
||||
+ rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
|
||||
+ ARRAY_SIZE(rk3288_hclkvio_branch));
|
||||
+
|
||||
rockchip_clk_protect_critical(rk3288_critical_clocks,
|
||||
ARRAY_SIZE(rk3288_critical_clocks));
|
||||
|
||||
|
||||
From cac2ef41ac59ff839b73fea934e8ffd161d406f2 Mon Sep 17 00:00:00 2001
|
||||
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
|
||||
Date: Fri, 3 Jul 2020 17:49:48 +0200
|
||||
Subject: [PATCH] clk: rockchip: use separate compatibles for rk3288w-cru
|
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|
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Commit 1627f683636d ("clk: rockchip: Handle clock tree for rk3288w variant")
|
||||
added the check for rk3288w-specific clock-tree changes but in turn would
|
||||
require a double-compatible due to re-using the main rockchip,rk3288-cru
|
||||
compatible as entry point.
|
||||
|
||||
The binding change actually describes the compatibles as one or the other
|
||||
so adapt the code accordingly and add a real second entry-point for the
|
||||
clock controller.
|
||||
|
||||
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
|
||||
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # rock-pi-n8
|
||||
Link: https://lore.kernel.org/r/20200703154948.260369-1-heiko@sntech.de
|
||||
(cherry picked from commit 0a7f99aad259d223ce69c03e792c7e2bfcf8c2c6)
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3288.c | 21 +++++++++++++++++++--
|
||||
1 file changed, 19 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
|
||||
index 204976e2d0cb..93c794695c46 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3288.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3288.c
|
||||
@@ -15,6 +15,11 @@
|
||||
#define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
|
||||
#define RK3288_GRF_SOC_STATUS1 0x284
|
||||
|
||||
+enum rk3288_variant {
|
||||
+ RK3288_CRU,
|
||||
+ RK3288W_CRU,
|
||||
+};
|
||||
+
|
||||
enum rk3288_plls {
|
||||
apll, dpll, cpll, gpll, npll,
|
||||
};
|
||||
@@ -922,7 +927,8 @@ static struct syscore_ops rk3288_clk_syscore_ops = {
|
||||
.resume = rk3288_clk_resume,
|
||||
};
|
||||
|
||||
-static void __init rk3288_clk_init(struct device_node *np)
|
||||
+static void __init rk3288_common_init(struct device_node *np,
|
||||
+ enum rk3288_variant soc)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
|
||||
@@ -945,7 +951,7 @@ static void __init rk3288_clk_init(struct device_node *np)
|
||||
rockchip_clk_register_branches(ctx, rk3288_clk_branches,
|
||||
ARRAY_SIZE(rk3288_clk_branches));
|
||||
|
||||
- if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
|
||||
+ if (soc == RK3288W_CRU)
|
||||
rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
|
||||
ARRAY_SIZE(rk3288w_hclkvio_branch));
|
||||
else
|
||||
@@ -970,4 +976,15 @@ static void __init rk3288_clk_init(struct device_node *np)
|
||||
|
||||
rockchip_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
+
|
||||
+static void __init rk3288_clk_init(struct device_node *np)
|
||||
+{
|
||||
+ rk3288_common_init(np, RK3288_CRU);
|
||||
+}
|
||||
CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
|
||||
+
|
||||
+static void __init rk3288w_clk_init(struct device_node *np)
|
||||
+{
|
||||
+ rk3288_common_init(np, RK3288W_CRU);
|
||||
+}
|
||||
+CLK_OF_DECLARE(rk3288w_cru, "rockchip,rk3288w-cru", rk3288w_clk_init);
|
||||
|
||||
From b80ef30ce22bba6a4bdf9f0aaa9376b6fea24249 Mon Sep 17 00:00:00 2001
|
||||
From: Robin Murphy <robin.murphy@arm.com>
|
||||
Date: Thu, 18 Jun 2020 18:56:29 +0100
|
||||
Subject: [PATCH] clk: rockchip: Revert "fix wrong mmc sample phase shift for
|
||||
rk3328"
|
||||
|
||||
This reverts commit 82f4b67f018c88a7cc9337f0067ed3d6ec352648.
|
||||
|
||||
According to a subsequent revert in the vendor kernel, the original
|
||||
change was based on unclear documentation and was in fact incorrect.
|
||||
|
||||
Emprically, my board's HS200 eMMC at 200MHZ apparently gets lucky with a
|
||||
phase where this had no impact, but limiting max-frequency to 150MHz to
|
||||
match the nominal capability of the I/O pins made it virtually unusable,
|
||||
constantly throwing errors and retuning. With this revert, it starts
|
||||
behaving perfectly at 150MHz too.
|
||||
|
||||
Fixes: 82f4b67f018c ("clk: rockchip: fix wrong mmc sample phase shift for rk3328")
|
||||
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
|
||||
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/c80eb52e34c03f817586b6b7912fbd4e31be9079.1589475794.git.robin.murphy@arm.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
(cherry picked from commit 465931e70881476a210d44705102ef8b6ee6cdb0)
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3328.c | 8 ++++----
|
||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
|
||||
index c186a1985bf4..2429b7c2a8b3 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3328.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3328.c
|
||||
@@ -808,22 +808,22 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
|
||||
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
|
||||
RK3328_SDMMC_CON0, 1),
|
||||
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
|
||||
- RK3328_SDMMC_CON1, 0),
|
||||
+ RK3328_SDMMC_CON1, 1),
|
||||
|
||||
MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
|
||||
RK3328_SDIO_CON0, 1),
|
||||
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
|
||||
- RK3328_SDIO_CON1, 0),
|
||||
+ RK3328_SDIO_CON1, 1),
|
||||
|
||||
MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
|
||||
RK3328_EMMC_CON0, 1),
|
||||
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
|
||||
- RK3328_EMMC_CON1, 0),
|
||||
+ RK3328_EMMC_CON1, 1),
|
||||
|
||||
MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",
|
||||
RK3328_SDMMC_EXT_CON0, 1),
|
||||
MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",
|
||||
- RK3328_SDMMC_EXT_CON1, 0),
|
||||
+ RK3328_SDMMC_EXT_CON1, 1),
|
||||
};
|
||||
|
||||
static const char *const rk3328_critical_clocks[] __initconst = {
|
||||
|
||||
From 21710a18bfba0cf0993a1ef700f03f540d2648ed Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 22 Jul 2020 18:18:20 +0200
|
||||
Subject: [PATCH] clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks
|
||||
|
||||
Since the loopbacktest clock is not exported and is not touched in the
|
||||
driver, it has to be added to rk3188_critical_clocks to be protected from
|
||||
being disabled and in order to get the emac working.
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20200722161820.5316-1-knaerzche@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
(cherry picked from commit ef990bcad58cf1d13c5a49191a2c2342eb8d6709)
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3188.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
|
||||
index 77aebfb1d6d5..730020fcc7fe 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3188.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3188.c
|
||||
@@ -751,6 +751,7 @@ static const char *const rk3188_critical_clocks[] __initconst = {
|
||||
"pclk_peri",
|
||||
"hclk_cpubus",
|
||||
"hclk_vio_bus",
|
||||
+ "sclk_mac_lbtest",
|
||||
};
|
||||
|
||||
static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
1190
patch/kernel/rk322x-current/01-linux-0011-v4l2-from-5.9.patch
Normal file
1190
patch/kernel/rk322x-current/01-linux-0011-v4l2-from-5.9.patch
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,319 +0,0 @@
|
|||
diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
|
||||
index 28313c0f4e7c..d472a54d1c4d 100644
|
||||
--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
|
||||
+++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
|
||||
@@ -2028,6 +2028,18 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type -
|
||||
* - ``V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM``
|
||||
- 0x00000004
|
||||
- The DPB entry is a long term reference frame
|
||||
+ * - ``V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE``
|
||||
+ - 0x00000008
|
||||
+ - The DPB entry is a field picture
|
||||
+ * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_TOP``
|
||||
+ - 0x00000010
|
||||
+ - The DPB entry is a top field reference
|
||||
+ * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM``
|
||||
+ - 0x00000020
|
||||
+ - The DPB entry is a bottom field reference
|
||||
+ * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME``
|
||||
+ - 0x00000030
|
||||
+ - The DPB entry is a reference frame
|
||||
|
||||
``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (enum)``
|
||||
Specifies the decoding mode to use. Currently exposes slice-based and
|
||||
diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h
|
||||
index e877bf1d537c..76020ebd1e6c 100644
|
||||
--- a/include/media/h264-ctrls.h
|
||||
+++ b/include/media/h264-ctrls.h
|
||||
@@ -185,6 +185,10 @@ struct v4l2_ctrl_h264_slice_params {
|
||||
#define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01
|
||||
#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02
|
||||
#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04
|
||||
+#define V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE 0x08
|
||||
+#define V4L2_H264_DPB_ENTRY_FLAG_REF_TOP 0x10
|
||||
+#define V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM 0x20
|
||||
+#define V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME 0x30
|
||||
|
||||
struct v4l2_h264_dpb_entry {
|
||||
__u64 reference_ts;
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From ef240de60cedea0264ca954a8e8e2fa25db097ae Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Tue, 29 Oct 2019 01:26:02 +0000
|
||||
Subject: [PATCH] RFC: media: hantro: Fix H264 decoding of field encoded
|
||||
content
|
||||
|
||||
This still need code cleanup and formatting
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
.../staging/media/hantro/hantro_g1_h264_dec.c | 17 +--
|
||||
drivers/staging/media/hantro/hantro_h264.c | 122 ++++++++++++------
|
||||
drivers/staging/media/hantro/hantro_hw.h | 2 +
|
||||
3 files changed, 85 insertions(+), 56 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
|
||||
index 424c648ce9fc..89cf5741280e 100644
|
||||
--- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c
|
||||
+++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
|
||||
@@ -132,25 +132,12 @@ static void set_ref(struct hantro_ctx *ctx)
|
||||
struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
|
||||
const u8 *b0_reflist, *b1_reflist, *p_reflist;
|
||||
struct hantro_dev *vpu = ctx->dev;
|
||||
- u32 dpb_longterm = 0;
|
||||
- u32 dpb_valid = 0;
|
||||
int reg_num;
|
||||
u32 reg;
|
||||
int i;
|
||||
|
||||
- /*
|
||||
- * Set up bit maps of valid and long term DPBs.
|
||||
- * NOTE: The bits are reversed, i.e. MSb is DPB 0.
|
||||
- */
|
||||
- for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
|
||||
- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
|
||||
- dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
|
||||
-
|
||||
- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
|
||||
- dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
|
||||
- }
|
||||
- vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF);
|
||||
- vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF);
|
||||
+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF);
|
||||
+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF);
|
||||
|
||||
/*
|
||||
* Set up reference frame picture numbers.
|
||||
diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c
|
||||
index f2d3e81fb6ce..4db779354e89 100644
|
||||
--- a/drivers/staging/media/hantro/hantro_h264.c
|
||||
+++ b/drivers/staging/media/hantro/hantro_h264.c
|
||||
@@ -225,17 +225,65 @@ static void prepare_table(struct hantro_ctx *ctx)
|
||||
{
|
||||
const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
|
||||
const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;
|
||||
+ const struct v4l2_ctrl_h264_slice_params *slices = ctrls->slices;
|
||||
struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu;
|
||||
const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
|
||||
+ u32 dpb_longterm = 0;
|
||||
+ u32 dpb_valid = 0;
|
||||
int i;
|
||||
|
||||
+ /*
|
||||
+ * Set up bit maps of valid and long term DPBs.
|
||||
+ * NOTE: The bits are reversed, i.e. MSb is DPB 0.
|
||||
+ */
|
||||
+ if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || (slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
|
||||
+ for (i = 0; i < HANTRO_H264_DPB_SIZE * 2; ++i) {
|
||||
+ // check for correct reference use
|
||||
+ u32 flag = (i & 0x1) ? V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM : V4L2_H264_DPB_ENTRY_FLAG_REF_TOP;
|
||||
+ if (dpb[i / 2].flags & flag)
|
||||
+ dpb_valid |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
|
||||
+
|
||||
+ if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
|
||||
+ dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
|
||||
+ }
|
||||
+
|
||||
+ ctx->h264_dec.dpb_valid = dpb_valid;
|
||||
+ ctx->h264_dec.dpb_longterm = dpb_longterm;
|
||||
+ } else {
|
||||
+ for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
|
||||
+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
|
||||
+ dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
|
||||
+
|
||||
+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
|
||||
+ dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
|
||||
+ }
|
||||
+
|
||||
+ ctx->h264_dec.dpb_valid = dpb_valid << 16;
|
||||
+ ctx->h264_dec.dpb_longterm = dpb_longterm << 16;
|
||||
+ }
|
||||
+
|
||||
for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
|
||||
- tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
|
||||
- tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
|
||||
+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) {
|
||||
+ tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
|
||||
+ tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
|
||||
+ } else {
|
||||
+ tbl->poc[i * 2] = 0;
|
||||
+ tbl->poc[i * 2 + 1] = 0;
|
||||
+ }
|
||||
}
|
||||
|
||||
- tbl->poc[32] = dec_param->top_field_order_cnt;
|
||||
- tbl->poc[33] = dec_param->bottom_field_order_cnt;
|
||||
+ if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || !(slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
|
||||
+ if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC))
|
||||
+ tbl->poc[32] = (slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ?
|
||||
+ dec_param->bottom_field_order_cnt :
|
||||
+ dec_param->top_field_order_cnt;
|
||||
+ else
|
||||
+ tbl->poc[32] = min(dec_param->top_field_order_cnt, dec_param->bottom_field_order_cnt);
|
||||
+ tbl->poc[33] = 0;
|
||||
+ } else {
|
||||
+ tbl->poc[32] = dec_param->top_field_order_cnt;
|
||||
+ tbl->poc[33] = dec_param->bottom_field_order_cnt;
|
||||
+ }
|
||||
|
||||
reorder_scaling_list(ctx);
|
||||
}
|
||||
@@ -249,21 +297,6 @@ struct hantro_h264_reflist_builder {
|
||||
u8 num_valid;
|
||||
};
|
||||
|
||||
-static s32 get_poc(enum v4l2_field field, s32 top_field_order_cnt,
|
||||
- s32 bottom_field_order_cnt)
|
||||
-{
|
||||
- switch (field) {
|
||||
- case V4L2_FIELD_TOP:
|
||||
- return top_field_order_cnt;
|
||||
- case V4L2_FIELD_BOTTOM:
|
||||
- return bottom_field_order_cnt;
|
||||
- default:
|
||||
- break;
|
||||
- }
|
||||
-
|
||||
- return min(top_field_order_cnt, bottom_field_order_cnt);
|
||||
-}
|
||||
-
|
||||
static void
|
||||
init_reflist_builder(struct hantro_ctx *ctx,
|
||||
struct hantro_h264_reflist_builder *b)
|
||||
@@ -271,9 +304,7 @@ init_reflist_builder(struct hantro_ctx *ctx,
|
||||
const struct v4l2_ctrl_h264_slice_params *slice_params;
|
||||
const struct v4l2_ctrl_h264_decode_params *dec_param;
|
||||
const struct v4l2_ctrl_h264_sps *sps;
|
||||
- struct vb2_v4l2_buffer *buf = hantro_get_dst_buf(ctx);
|
||||
const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
|
||||
- struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q;
|
||||
int cur_frame_num, max_frame_num;
|
||||
unsigned int i;
|
||||
|
||||
@@ -285,21 +316,15 @@ init_reflist_builder(struct hantro_ctx *ctx,
|
||||
|
||||
memset(b, 0, sizeof(*b));
|
||||
b->dpb = dpb;
|
||||
- b->curpoc = get_poc(buf->field, dec_param->top_field_order_cnt,
|
||||
- dec_param->bottom_field_order_cnt);
|
||||
+ b->curpoc = (slice_params->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ?
|
||||
+ dec_param->bottom_field_order_cnt :
|
||||
+ dec_param->top_field_order_cnt;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) {
|
||||
- int buf_idx;
|
||||
-
|
||||
- if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
|
||||
+ u32 ref_flag = dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME;
|
||||
+ if (!ref_flag)
|
||||
continue;
|
||||
|
||||
- buf_idx = vb2_find_timestamp(cap_q, dpb[i].reference_ts, 0);
|
||||
- if (buf_idx < 0)
|
||||
- continue;
|
||||
-
|
||||
- buf = to_vb2_v4l2_buffer(vb2_get_buffer(cap_q, buf_idx));
|
||||
-
|
||||
/*
|
||||
* Handle frame_num wraparound as described in section
|
||||
* '8.2.4.1 Decoding process for picture numbers' of the spec.
|
||||
@@ -311,8 +336,13 @@ init_reflist_builder(struct hantro_ctx *ctx,
|
||||
else
|
||||
b->frame_nums[i] = dpb[i].frame_num;
|
||||
|
||||
- b->pocs[i] = get_poc(buf->field, dpb[i].top_field_order_cnt,
|
||||
- dpb[i].bottom_field_order_cnt);
|
||||
+ if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME)
|
||||
+ b->pocs[i] = min(dpb[i].bottom_field_order_cnt, dpb[i].top_field_order_cnt);
|
||||
+ else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM)
|
||||
+ b->pocs[i] = dpb[i].bottom_field_order_cnt;
|
||||
+ else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_TOP)
|
||||
+ b->pocs[i] = dpb[i].top_field_order_cnt;
|
||||
+
|
||||
b->unordered_reflist[b->num_valid] = i;
|
||||
b->num_valid++;
|
||||
}
|
||||
@@ -466,8 +496,7 @@ build_b_ref_lists(const struct hantro_h264_reflist_builder *builder,
|
||||
static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a,
|
||||
const struct v4l2_h264_dpb_entry *b)
|
||||
{
|
||||
- return a->top_field_order_cnt == b->top_field_order_cnt &&
|
||||
- a->bottom_field_order_cnt == b->bottom_field_order_cnt;
|
||||
+ return a->reference_ts == b->reference_ts;
|
||||
}
|
||||
|
||||
static void update_dpb(struct hantro_ctx *ctx)
|
||||
@@ -481,13 +510,13 @@ static void update_dpb(struct hantro_ctx *ctx)
|
||||
|
||||
/* Disable all entries by default. */
|
||||
for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++)
|
||||
- ctx->h264_dec.dpb[i].flags &= ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE;
|
||||
+ ctx->h264_dec.dpb[i].flags = 0;
|
||||
|
||||
/* Try to match new DPB entries with existing ones by their POCs. */
|
||||
for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) {
|
||||
const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i];
|
||||
|
||||
- if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
|
||||
+ if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID))
|
||||
continue;
|
||||
|
||||
/*
|
||||
@@ -498,8 +527,7 @@ static void update_dpb(struct hantro_ctx *ctx)
|
||||
struct v4l2_h264_dpb_entry *cdpb;
|
||||
|
||||
cdpb = &ctx->h264_dec.dpb[j];
|
||||
- if (cdpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE ||
|
||||
- !dpb_entry_match(cdpb, ndpb))
|
||||
+ if (!dpb_entry_match(cdpb, ndpb))
|
||||
continue;
|
||||
|
||||
*cdpb = *ndpb;
|
||||
@@ -535,7 +563,11 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
|
||||
unsigned int dpb_idx)
|
||||
{
|
||||
struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
|
||||
+ const struct v4l2_ctrl_h264_decode_params *dec_param = ctx->h264_dec.ctrls.decode;
|
||||
+ const struct v4l2_ctrl_h264_slice_params *slices = ctx->h264_dec.ctrls.slices;
|
||||
dma_addr_t dma_addr = 0;
|
||||
+ s32 cur_poc;
|
||||
+ u32 flags;
|
||||
|
||||
if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
|
||||
dma_addr = hantro_get_ref(ctx, dpb[dpb_idx].reference_ts);
|
||||
@@ -553,7 +585,15 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
|
||||
dma_addr = vb2_dma_contig_plane_dma_addr(buf, 0);
|
||||
}
|
||||
|
||||
- return dma_addr;
|
||||
+ cur_poc = slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD ?
|
||||
+ dec_param->bottom_field_order_cnt :
|
||||
+ dec_param->top_field_order_cnt;
|
||||
+ flags = dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE ? 0x2 : 0;
|
||||
+ flags |= abs(dpb[dpb_idx].top_field_order_cnt - cur_poc) <
|
||||
+ abs(dpb[dpb_idx].bottom_field_order_cnt - cur_poc) ?
|
||||
+ 0x1 : 0;
|
||||
+
|
||||
+ return dma_addr | flags;
|
||||
}
|
||||
|
||||
int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx)
|
||||
diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
|
||||
index 2398d4c1f207..3dc7b8f27c32 100644
|
||||
--- a/drivers/staging/media/hantro/hantro_hw.h
|
||||
+++ b/drivers/staging/media/hantro/hantro_hw.h
|
||||
@@ -88,6 +88,8 @@ struct hantro_h264_dec_hw_ctx {
|
||||
struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE];
|
||||
struct hantro_h264_dec_reflists reflists;
|
||||
struct hantro_h264_dec_ctrls ctrls;
|
||||
+ u32 dpb_longterm;
|
||||
+ u32 dpb_valid;
|
||||
};
|
||||
|
||||
/**
|
||||
--
|
||||
2.17.1
|
||||
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,53 +0,0 @@
|
|||
Add a node to define the presence of RGA, a 2D raster
|
||||
graphic acceleration unit.
|
||||
|
||||
Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
|
||||
---
|
||||
arch/arm/boot/dts/rk322x.dtsi | 11 +++++++++++
|
||||
1 file changed, 11 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
|
||||
index 340ed6ccb..29d50bebc 100644
|
||||
--- a/arch/arm/boot/dts/rk322x.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk322x.dtsi
|
||||
@@ -621,6 +621,17 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ rga: rga@20060000 {
|
||||
+ compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
|
||||
+ reg = <0x20060000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
|
||||
+ clock-names = "aclk", "hclk", "sclk";
|
||||
+ resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
|
||||
+ reset-names = "core", "axi", "ahb";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
iep_mmu: iommu@20070800 {
|
||||
compatible = "rockchip,iommu";
|
||||
reg = <0x20070800 0x100>;
|
||||
|
||||
Enable RGA for Mecer Xtreme Mini S6.
|
||||
|
||||
Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
|
||||
---
|
||||
arch/arm/boot/dts/rk3229-xms6.dts | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rk3229-xms6.dts
|
||||
index 679fc2b00..894f64a4a 100644
|
||||
--- a/arch/arm/boot/dts/rk3229-xms6.dts
|
||||
+++ b/arch/arm/boot/dts/rk3229-xms6.dts
|
||||
@@ -202,6 +202,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&rga {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&sdmmc {
|
||||
cap-mmc-highspeed;
|
||||
disable-wp;
|
||||
|
|
@ -1,718 +0,0 @@
|
|||
diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c
|
||||
index cc34c5ab7009..3070672e6b4f 100644
|
||||
--- a/drivers/media/v4l2-core/v4l2-mem2mem.c
|
||||
+++ b/drivers/media/v4l2-core/v4l2-mem2mem.c
|
||||
@@ -499,12 +499,21 @@ void v4l2_m2m_buf_done_and_job_finish(struct v4l2_m2m_dev *m2m_dev,
|
||||
|
||||
if (WARN_ON(!src_buf || !dst_buf))
|
||||
goto unlock;
|
||||
- v4l2_m2m_buf_done(src_buf, state);
|
||||
dst_buf->is_held = src_buf->flags & V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF;
|
||||
if (!dst_buf->is_held) {
|
||||
v4l2_m2m_dst_buf_remove(m2m_ctx);
|
||||
v4l2_m2m_buf_done(dst_buf, state);
|
||||
}
|
||||
+ /*
|
||||
+ * If the request API is being used, returning the OUTPUT
|
||||
+ * (src) buffer will wake-up any process waiting on the
|
||||
+ * request file descriptor.
|
||||
+ *
|
||||
+ * Therefore, return the CAPTURE (dst) buffer first,
|
||||
+ * to avoid signalling the request file descriptor
|
||||
+ * before the CAPTURE buffer is done.
|
||||
+ */
|
||||
+ v4l2_m2m_buf_done(src_buf, state);
|
||||
schedule_next = _v4l2_m2m_job_finish(m2m_dev, m2m_ctx);
|
||||
unlock:
|
||||
spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags);
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From 46fef6ecbc765dedaeef46339474529645f09404 Mon Sep 17 00:00:00 2001
|
||||
From: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
Date: Wed, 18 Mar 2020 10:21:02 -0300
|
||||
Subject: [PATCH] hantro: Set buffers' zeroth plane payload in .buf_prepare
|
||||
|
||||
Buffers' zeroth plane payload size is calculated at format
|
||||
negotiation time, and so it can be set in .buf_prepare.
|
||||
|
||||
Keep in mind that, to make this change easier, hantro_buf_prepare
|
||||
is refactored, using the cedrus driver as reference. This results
|
||||
in cleaner code as byproduct.
|
||||
|
||||
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
---
|
||||
drivers/staging/media/hantro/hantro_v4l2.c | 16 +++++++++++-----
|
||||
1 file changed, 11 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c
|
||||
index f4ae2cee0f18..3142ab6697d5 100644
|
||||
--- a/drivers/staging/media/hantro/hantro_v4l2.c
|
||||
+++ b/drivers/staging/media/hantro/hantro_v4l2.c
|
||||
@@ -608,7 +608,7 @@ hantro_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
|
||||
}
|
||||
|
||||
static int
|
||||
-hantro_buf_plane_check(struct vb2_buffer *vb, const struct hantro_fmt *vpu_fmt,
|
||||
+hantro_buf_plane_check(struct vb2_buffer *vb,
|
||||
struct v4l2_pix_format_mplane *pixfmt)
|
||||
{
|
||||
unsigned int sz;
|
||||
@@ -630,12 +630,18 @@ static int hantro_buf_prepare(struct vb2_buffer *vb)
|
||||
{
|
||||
struct vb2_queue *vq = vb->vb2_queue;
|
||||
struct hantro_ctx *ctx = vb2_get_drv_priv(vq);
|
||||
+ struct v4l2_pix_format_mplane *pix_fmt;
|
||||
+ int ret;
|
||||
|
||||
if (V4L2_TYPE_IS_OUTPUT(vq->type))
|
||||
- return hantro_buf_plane_check(vb, ctx->vpu_src_fmt,
|
||||
- &ctx->src_fmt);
|
||||
-
|
||||
- return hantro_buf_plane_check(vb, ctx->vpu_dst_fmt, &ctx->dst_fmt);
|
||||
+ pix_fmt = &ctx->src_fmt;
|
||||
+ else
|
||||
+ pix_fmt = &ctx->dst_fmt;
|
||||
+ ret = hantro_buf_plane_check(vb, pix_fmt);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ vb2_set_plane_payload(vb, 0, pix_fmt->plane_fmt[0].sizeimage);
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static void hantro_buf_queue(struct vb2_buffer *vb)
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From 49b98070ac9cbd4e731a84f0a3c10e6dd803d37c Mon Sep 17 00:00:00 2001
|
||||
From: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
Date: Wed, 18 Mar 2020 10:21:03 -0300
|
||||
Subject: [PATCH] hantro: Use v4l2_m2m_buf_done_and_job_finish
|
||||
|
||||
Let the core sort out the nuances of returning buffers
|
||||
to userspace, by using the v4l2_m2m_buf_done_and_job_finish
|
||||
helper.
|
||||
|
||||
This change also removes usage of buffer sequence fields,
|
||||
which shouldn't have any meaning for stateless decoders.
|
||||
|
||||
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
Nacked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
|
||||
---
|
||||
drivers/staging/media/hantro/hantro_drv.c | 27 ++++++++---------------
|
||||
1 file changed, 9 insertions(+), 18 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
|
||||
index c98835326135..dd503918a017 100644
|
||||
--- a/drivers/staging/media/hantro/hantro_drv.c
|
||||
+++ b/drivers/staging/media/hantro/hantro_drv.c
|
||||
@@ -94,32 +94,23 @@ static void hantro_job_finish(struct hantro_dev *vpu,
|
||||
unsigned int bytesused,
|
||||
enum vb2_buffer_state result)
|
||||
{
|
||||
- struct vb2_v4l2_buffer *src, *dst;
|
||||
int ret;
|
||||
|
||||
pm_runtime_mark_last_busy(vpu->dev);
|
||||
pm_runtime_put_autosuspend(vpu->dev);
|
||||
clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks);
|
||||
|
||||
- src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
|
||||
- dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
|
||||
-
|
||||
- if (WARN_ON(!src))
|
||||
- return;
|
||||
- if (WARN_ON(!dst))
|
||||
- return;
|
||||
-
|
||||
- src->sequence = ctx->sequence_out++;
|
||||
- dst->sequence = ctx->sequence_cap++;
|
||||
-
|
||||
- ret = ctx->buf_finish(ctx, &dst->vb2_buf, bytesused);
|
||||
- if (ret)
|
||||
- result = VB2_BUF_STATE_ERROR;
|
||||
+ if (ctx->buf_finish) {
|
||||
+ struct vb2_v4l2_buffer *dst;
|
||||
|
||||
- v4l2_m2m_buf_done(src, result);
|
||||
- v4l2_m2m_buf_done(dst, result);
|
||||
+ dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
|
||||
+ ret = ctx->buf_finish(ctx, &dst->vb2_buf, bytesused);
|
||||
+ if (ret)
|
||||
+ result = VB2_BUF_STATE_ERROR;
|
||||
+ }
|
||||
|
||||
- v4l2_m2m_job_finish(vpu->m2m_dev, ctx->fh.m2m_ctx);
|
||||
+ v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
|
||||
+ result);
|
||||
}
|
||||
|
||||
void hantro_irq_done(struct hantro_dev *vpu, unsigned int bytesused,
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From ee3c913094e5776a0b1270b78ecce8a5e9803a42 Mon Sep 17 00:00:00 2001
|
||||
From: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
Date: Wed, 18 Mar 2020 10:21:04 -0300
|
||||
Subject: [PATCH] hantro: Remove unneeded hantro_dec_buf_finish
|
||||
|
||||
Since now .buf_prepare takes care of setting the
|
||||
buffer payload size, we can get rid of this,
|
||||
at least for decoders.
|
||||
|
||||
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
---
|
||||
drivers/staging/media/hantro/hantro_drv.c | 10 ----------
|
||||
1 file changed, 10 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
|
||||
index dd503918a017..a732beeb3bb6 100644
|
||||
--- a/drivers/staging/media/hantro/hantro_drv.c
|
||||
+++ b/drivers/staging/media/hantro/hantro_drv.c
|
||||
@@ -80,15 +80,6 @@ hantro_enc_buf_finish(struct hantro_ctx *ctx, struct vb2_buffer *buf,
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int
|
||||
-hantro_dec_buf_finish(struct hantro_ctx *ctx, struct vb2_buffer *buf,
|
||||
- unsigned int bytesused)
|
||||
-{
|
||||
- /* For decoders set bytesused as per the output picture. */
|
||||
- buf->planes[0].bytesused = ctx->dst_fmt.plane_fmt[0].sizeimage;
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
static void hantro_job_finish(struct hantro_dev *vpu,
|
||||
struct hantro_ctx *ctx,
|
||||
unsigned int bytesused,
|
||||
@@ -412,7 +403,6 @@ static int hantro_open(struct file *filp)
|
||||
ctx->buf_finish = hantro_enc_buf_finish;
|
||||
} else if (func->id == MEDIA_ENT_F_PROC_VIDEO_DECODER) {
|
||||
allowed_codecs = vpu->variant->codec & HANTRO_DECODERS;
|
||||
- ctx->buf_finish = hantro_dec_buf_finish;
|
||||
} else {
|
||||
ret = -ENODEV;
|
||||
goto err_ctx_free;
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From 403b36c2db7e39b46f8e0f6a363af6763373933d Mon Sep 17 00:00:00 2001
|
||||
From: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
Date: Wed, 18 Mar 2020 10:21:05 -0300
|
||||
Subject: [PATCH] hantro: Move H264 motion vector calculation to a helper
|
||||
|
||||
Move the extra bytes calculation that are needed for H264
|
||||
motion vector to a helper. This is just a cosmetic cleanup.
|
||||
|
||||
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
---
|
||||
drivers/staging/media/hantro/hantro.h | 4 ---
|
||||
drivers/staging/media/hantro/hantro_hw.h | 31 ++++++++++++++++++++++
|
||||
drivers/staging/media/hantro/hantro_v4l2.c | 25 ++---------------
|
||||
3 files changed, 33 insertions(+), 27 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
|
||||
index b0faa43b3f79..1a010d438ac2 100644
|
||||
--- a/drivers/staging/media/hantro/hantro.h
|
||||
+++ b/drivers/staging/media/hantro/hantro.h
|
||||
@@ -26,10 +26,6 @@
|
||||
|
||||
#include "hantro_hw.h"
|
||||
|
||||
-#define MB_DIM 16
|
||||
-#define MB_WIDTH(w) DIV_ROUND_UP(w, MB_DIM)
|
||||
-#define MB_HEIGHT(h) DIV_ROUND_UP(h, MB_DIM)
|
||||
-
|
||||
struct hantro_ctx;
|
||||
struct hantro_codec_ops;
|
||||
|
||||
diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
|
||||
index 4a64873bf332..33c1ce169203 100644
|
||||
--- a/drivers/staging/media/hantro/hantro_hw.h
|
||||
+++ b/drivers/staging/media/hantro/hantro_hw.h
|
||||
@@ -18,6 +18,10 @@
|
||||
|
||||
#define DEC_8190_ALIGN_MASK 0x07U
|
||||
|
||||
+#define MB_DIM 16
|
||||
+#define MB_WIDTH(w) DIV_ROUND_UP(w, MB_DIM)
|
||||
+#define MB_HEIGHT(h) DIV_ROUND_UP(h, MB_DIM)
|
||||
+
|
||||
struct hantro_dev;
|
||||
struct hantro_ctx;
|
||||
struct hantro_buf;
|
||||
@@ -180,6 +184,33 @@ void rk3399_vpu_h264_dec_run(struct hantro_ctx *ctx);
|
||||
int hantro_h264_dec_init(struct hantro_ctx *ctx);
|
||||
void hantro_h264_dec_exit(struct hantro_ctx *ctx);
|
||||
|
||||
+static inline size_t
|
||||
+hantro_h264_mv_size(unsigned int width, unsigned int height)
|
||||
+{
|
||||
+ /*
|
||||
+ * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to
|
||||
+ * 448 bytes per macroblock with additional 32 bytes on
|
||||
+ * multi-core variants.
|
||||
+ *
|
||||
+ * The H264 decoder needs extra space on the output buffers
|
||||
+ * to store motion vectors. This is needed for reference
|
||||
+ * frames and only if the format is non-post-processed NV12.
|
||||
+ *
|
||||
+ * Memory layout is as follow:
|
||||
+ *
|
||||
+ * +---------------------------+
|
||||
+ * | Y-plane 256 bytes x MBs |
|
||||
+ * +---------------------------+
|
||||
+ * | UV-plane 128 bytes x MBs |
|
||||
+ * +---------------------------+
|
||||
+ * | MV buffer 64 bytes x MBs |
|
||||
+ * +---------------------------+
|
||||
+ * | MC sync 32 bytes |
|
||||
+ * +---------------------------+
|
||||
+ */
|
||||
+ return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32;
|
||||
+}
|
||||
+
|
||||
void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);
|
||||
void rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx);
|
||||
void hantro_mpeg2_dec_copy_qtable(u8 *qtable,
|
||||
diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c
|
||||
index 3142ab6697d5..458b502ff01b 100644
|
||||
--- a/drivers/staging/media/hantro/hantro_v4l2.c
|
||||
+++ b/drivers/staging/media/hantro/hantro_v4l2.c
|
||||
@@ -273,32 +273,11 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f,
|
||||
/* Fill remaining fields */
|
||||
v4l2_fill_pixfmt_mp(pix_mp, fmt->fourcc, pix_mp->width,
|
||||
pix_mp->height);
|
||||
- /*
|
||||
- * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to
|
||||
- * 448 bytes per macroblock with additional 32 bytes on
|
||||
- * multi-core variants.
|
||||
- *
|
||||
- * The H264 decoder needs extra space on the output buffers
|
||||
- * to store motion vectors. This is needed for reference
|
||||
- * frames and only if the format is non-post-processed NV12.
|
||||
- *
|
||||
- * Memory layout is as follow:
|
||||
- *
|
||||
- * +---------------------------+
|
||||
- * | Y-plane 256 bytes x MBs |
|
||||
- * +---------------------------+
|
||||
- * | UV-plane 128 bytes x MBs |
|
||||
- * +---------------------------+
|
||||
- * | MV buffer 64 bytes x MBs |
|
||||
- * +---------------------------+
|
||||
- * | MC sync 32 bytes |
|
||||
- * +---------------------------+
|
||||
- */
|
||||
if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE &&
|
||||
!hantro_needs_postproc(ctx, fmt))
|
||||
pix_mp->plane_fmt[0].sizeimage +=
|
||||
- 64 * MB_WIDTH(pix_mp->width) *
|
||||
- MB_WIDTH(pix_mp->height) + 32;
|
||||
+ hantro_h264_mv_size(pix_mp->width,
|
||||
+ pix_mp->height);
|
||||
} else if (!pix_mp->plane_fmt[0].sizeimage) {
|
||||
/*
|
||||
* For coded formats the application can specify
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From 220559bea572812494ac528eb4bb3af770748641 Mon Sep 17 00:00:00 2001
|
||||
From: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
Date: Wed, 18 Mar 2020 10:21:06 -0300
|
||||
Subject: [PATCH] hantro: Refactor for V4L2 API spec compliancy
|
||||
|
||||
Refactor how S_FMT and TRY_FMT are handled, and also make sure
|
||||
internal initial format and format reset are done properly.
|
||||
|
||||
The latter is achieved by making sure the same hantro_{set,try}_fmt
|
||||
helpers are called on all paths that set the format (which is
|
||||
part of the driver state).
|
||||
|
||||
This commit removes the following v4l2-compliance warnings:
|
||||
|
||||
test VIDIOC_G_FMT: OK
|
||||
fail: v4l2-test-formats.cpp(711): Video Capture Multiplanar: TRY_FMT(G_FMT) != G_FMT
|
||||
test VIDIOC_TRY_FMT: FAIL
|
||||
fail: v4l2-test-formats.cpp(1116): Video Capture Multiplanar: S_FMT(G_FMT) != G_FMT
|
||||
test VIDIOC_S_FMT: FAIL
|
||||
|
||||
Reported-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
|
||||
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
---
|
||||
drivers/staging/media/hantro/hantro.h | 3 +-
|
||||
drivers/staging/media/hantro/hantro_v4l2.c | 70 ++++++++++++++--------
|
||||
2 files changed, 47 insertions(+), 26 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
|
||||
index 1a010d438ac2..f0aca46969f9 100644
|
||||
--- a/drivers/staging/media/hantro/hantro.h
|
||||
+++ b/drivers/staging/media/hantro/hantro.h
|
||||
@@ -417,7 +417,8 @@ hantro_get_dst_buf(struct hantro_ctx *ctx)
|
||||
}
|
||||
|
||||
static inline bool
|
||||
-hantro_needs_postproc(struct hantro_ctx *ctx, const struct hantro_fmt *fmt)
|
||||
+hantro_needs_postproc(const struct hantro_ctx *ctx,
|
||||
+ const struct hantro_fmt *fmt)
|
||||
{
|
||||
return fmt->fourcc != V4L2_PIX_FMT_NV12;
|
||||
}
|
||||
diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c
|
||||
index 458b502ff01b..f28a94e2fa93 100644
|
||||
--- a/drivers/staging/media/hantro/hantro_v4l2.c
|
||||
+++ b/drivers/staging/media/hantro/hantro_v4l2.c
|
||||
@@ -30,6 +30,11 @@
|
||||
#include "hantro_hw.h"
|
||||
#include "hantro_v4l2.h"
|
||||
|
||||
+static int hantro_set_fmt_out(struct hantro_ctx *ctx,
|
||||
+ struct v4l2_pix_format_mplane *pix_mp);
|
||||
+static int hantro_set_fmt_cap(struct hantro_ctx *ctx,
|
||||
+ struct v4l2_pix_format_mplane *pix_mp);
|
||||
+
|
||||
static const struct hantro_fmt *
|
||||
hantro_get_formats(const struct hantro_ctx *ctx, unsigned int *num_fmts)
|
||||
{
|
||||
@@ -227,12 +232,12 @@ static int vidioc_g_fmt_cap_mplane(struct file *file, void *priv,
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f,
|
||||
- bool capture)
|
||||
+static int hantro_try_fmt(const struct hantro_ctx *ctx,
|
||||
+ struct v4l2_pix_format_mplane *pix_mp,
|
||||
+ enum v4l2_buf_type type)
|
||||
{
|
||||
- struct hantro_ctx *ctx = fh_to_ctx(priv);
|
||||
- struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
|
||||
const struct hantro_fmt *fmt, *vpu_fmt;
|
||||
+ bool capture = !V4L2_TYPE_IS_OUTPUT(type);
|
||||
bool coded;
|
||||
|
||||
coded = capture == hantro_is_encoder_ctx(ctx);
|
||||
@@ -246,7 +251,7 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f,
|
||||
fmt = hantro_find_format(ctx, pix_mp->pixelformat);
|
||||
if (!fmt) {
|
||||
fmt = hantro_get_default_fmt(ctx, coded);
|
||||
- f->fmt.pix_mp.pixelformat = fmt->fourcc;
|
||||
+ pix_mp->pixelformat = fmt->fourcc;
|
||||
}
|
||||
|
||||
if (coded) {
|
||||
@@ -294,13 +299,13 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f,
|
||||
static int vidioc_try_fmt_cap_mplane(struct file *file, void *priv,
|
||||
struct v4l2_format *f)
|
||||
{
|
||||
- return vidioc_try_fmt(file, priv, f, true);
|
||||
+ return hantro_try_fmt(fh_to_ctx(priv), &f->fmt.pix_mp, f->type);
|
||||
}
|
||||
|
||||
static int vidioc_try_fmt_out_mplane(struct file *file, void *priv,
|
||||
struct v4l2_format *f)
|
||||
{
|
||||
- return vidioc_try_fmt(file, priv, f, false);
|
||||
+ return hantro_try_fmt(fh_to_ctx(priv), &f->fmt.pix_mp, f->type);
|
||||
}
|
||||
|
||||
static void
|
||||
@@ -334,11 +339,12 @@ hantro_reset_encoded_fmt(struct hantro_ctx *ctx)
|
||||
}
|
||||
|
||||
hantro_reset_fmt(fmt, vpu_fmt);
|
||||
- fmt->num_planes = 1;
|
||||
fmt->width = vpu_fmt->frmsize.min_width;
|
||||
fmt->height = vpu_fmt->frmsize.min_height;
|
||||
- fmt->plane_fmt[0].sizeimage = vpu_fmt->header_size +
|
||||
- fmt->width * fmt->height * vpu_fmt->max_depth;
|
||||
+ if (hantro_is_encoder_ctx(ctx))
|
||||
+ hantro_set_fmt_cap(ctx, fmt);
|
||||
+ else
|
||||
+ hantro_set_fmt_out(ctx, fmt);
|
||||
}
|
||||
|
||||
static void
|
||||
@@ -360,9 +366,12 @@ hantro_reset_raw_fmt(struct hantro_ctx *ctx)
|
||||
}
|
||||
|
||||
hantro_reset_fmt(raw_fmt, raw_vpu_fmt);
|
||||
- v4l2_fill_pixfmt_mp(raw_fmt, raw_vpu_fmt->fourcc,
|
||||
- encoded_fmt->width,
|
||||
- encoded_fmt->height);
|
||||
+ raw_fmt->width = encoded_fmt->width;
|
||||
+ raw_fmt->width = encoded_fmt->width;
|
||||
+ if (hantro_is_encoder_ctx(ctx))
|
||||
+ hantro_set_fmt_out(ctx, raw_fmt);
|
||||
+ else
|
||||
+ hantro_set_fmt_cap(ctx, raw_fmt);
|
||||
}
|
||||
|
||||
void hantro_reset_fmts(struct hantro_ctx *ctx)
|
||||
@@ -388,15 +397,15 @@ hantro_update_requires_request(struct hantro_ctx *ctx, u32 fourcc)
|
||||
}
|
||||
}
|
||||
|
||||
-static int
|
||||
-vidioc_s_fmt_out_mplane(struct file *file, void *priv, struct v4l2_format *f)
|
||||
+static int hantro_set_fmt_out(struct hantro_ctx *ctx,
|
||||
+ struct v4l2_pix_format_mplane *pix_mp)
|
||||
{
|
||||
- struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
|
||||
- struct hantro_ctx *ctx = fh_to_ctx(priv);
|
||||
- struct vb2_queue *vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
|
||||
+ struct vb2_queue *vq;
|
||||
int ret;
|
||||
|
||||
- ret = vidioc_try_fmt_out_mplane(file, priv, f);
|
||||
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
|
||||
+ V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
|
||||
+ ret = hantro_try_fmt(ctx, pix_mp, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@@ -458,16 +467,15 @@ vidioc_s_fmt_out_mplane(struct file *file, void *priv, struct v4l2_format *f)
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int vidioc_s_fmt_cap_mplane(struct file *file, void *priv,
|
||||
- struct v4l2_format *f)
|
||||
+static int hantro_set_fmt_cap(struct hantro_ctx *ctx,
|
||||
+ struct v4l2_pix_format_mplane *pix_mp)
|
||||
{
|
||||
- struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
|
||||
- struct hantro_ctx *ctx = fh_to_ctx(priv);
|
||||
struct vb2_queue *vq;
|
||||
int ret;
|
||||
|
||||
/* Change not allowed if queue is busy. */
|
||||
- vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
|
||||
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
|
||||
+ V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
|
||||
if (vb2_is_busy(vq))
|
||||
return -EBUSY;
|
||||
|
||||
@@ -488,7 +496,7 @@ static int vidioc_s_fmt_cap_mplane(struct file *file, void *priv,
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
- ret = vidioc_try_fmt_cap_mplane(file, priv, f);
|
||||
+ ret = hantro_try_fmt(ctx, pix_mp, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@@ -522,6 +530,18 @@ static int vidioc_s_fmt_cap_mplane(struct file *file, void *priv,
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int
|
||||
+vidioc_s_fmt_out_mplane(struct file *file, void *priv, struct v4l2_format *f)
|
||||
+{
|
||||
+ return hantro_set_fmt_out(fh_to_ctx(priv), &f->fmt.pix_mp);
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+vidioc_s_fmt_cap_mplane(struct file *file, void *priv, struct v4l2_format *f)
|
||||
+{
|
||||
+ return hantro_set_fmt_cap(fh_to_ctx(priv), &f->fmt.pix_mp);
|
||||
+}
|
||||
+
|
||||
const struct v4l2_ioctl_ops hantro_ioctl_ops = {
|
||||
.vidioc_querycap = vidioc_querycap,
|
||||
.vidioc_enum_framesizes = vidioc_enum_framesizes,
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From 03a4222379d16c8a5f4a9c74f78c977b6a0e16a0 Mon Sep 17 00:00:00 2001
|
||||
From: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
Date: Wed, 18 Mar 2020 10:21:07 -0300
|
||||
Subject: [PATCH] dt-bindings: rockchip-vpu: Convert bindings to json-schema
|
||||
|
||||
Convert Rockchip VPU (Hantro IP block) codec driver documentation to
|
||||
json-schema.
|
||||
|
||||
Cc: Rob Herring <robh@kernel.org>
|
||||
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
---
|
||||
.../bindings/media/rockchip-vpu.txt | 43 ----------
|
||||
.../bindings/media/rockchip-vpu.yaml | 82 +++++++++++++++++++
|
||||
MAINTAINERS | 2 +-
|
||||
3 files changed, 83 insertions(+), 44 deletions(-)
|
||||
delete mode 100644 Documentation/devicetree/bindings/media/rockchip-vpu.txt
|
||||
create mode 100644 Documentation/devicetree/bindings/media/rockchip-vpu.yaml
|
||||
|
||||
diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.txt b/Documentation/devicetree/bindings/media/rockchip-vpu.txt
|
||||
deleted file mode 100644
|
||||
index 339252d9c515..000000000000
|
||||
--- a/Documentation/devicetree/bindings/media/rockchip-vpu.txt
|
||||
+++ /dev/null
|
||||
@@ -1,43 +0,0 @@
|
||||
-device-tree bindings for rockchip VPU codec
|
||||
-
|
||||
-Rockchip (Video Processing Unit) present in various Rockchip platforms,
|
||||
-such as RK3288, RK3328 and RK3399.
|
||||
-
|
||||
-Required properties:
|
||||
-- compatible: value should be one of the following
|
||||
- "rockchip,rk3288-vpu";
|
||||
- "rockchip,rk3328-vpu";
|
||||
- "rockchip,rk3399-vpu";
|
||||
-- interrupts: encoding and decoding interrupt specifiers
|
||||
-- interrupt-names: should be
|
||||
- "vepu", "vdpu" on RK3288 and RK3399,
|
||||
- "vdpu" on RK3328.
|
||||
-- clocks: phandle to VPU aclk, hclk clocks
|
||||
-- clock-names: should be "aclk" and "hclk"
|
||||
-- power-domains: phandle to power domain node
|
||||
-- iommus: phandle to a iommu node
|
||||
-
|
||||
-Example:
|
||||
-SoC-specific DT entry:
|
||||
- vpu: video-codec@ff9a0000 {
|
||||
- compatible = "rockchip,rk3288-vpu";
|
||||
- reg = <0x0 0xff9a0000 0x0 0x800>;
|
||||
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- interrupt-names = "vepu", "vdpu";
|
||||
- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
|
||||
- clock-names = "aclk", "hclk";
|
||||
- power-domains = <&power RK3288_PD_VIDEO>;
|
||||
- iommus = <&vpu_mmu>;
|
||||
- };
|
||||
-
|
||||
- vpu: video-codec@ff350000 {
|
||||
- compatible = "rockchip,rk3328-vpu";
|
||||
- reg = <0x0 0xff350000 0x0 0x800>;
|
||||
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- interrupt-names = "vdpu";
|
||||
- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
||||
- clock-names = "aclk", "hclk";
|
||||
- power-domains = <&power RK3328_PD_VPU>;
|
||||
- iommus = <&vpu_mmu>;
|
||||
- };
|
||||
diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
|
||||
new file mode 100644
|
||||
index 000000000000..a0c45e05cf03
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
|
||||
@@ -0,0 +1,82 @@
|
||||
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
+
|
||||
+%YAML 1.2
|
||||
+---
|
||||
+$id: "http://devicetree.org/schemas/media/rockchip-vpu.yaml#"
|
||||
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
+
|
||||
+title: Hantro G1 VPU codecs implemented on Rockchip SoCs
|
||||
+
|
||||
+maintainers:
|
||||
+ - Ezequiel Garcia <ezequiel@collabora.com>
|
||||
+
|
||||
+description:
|
||||
+ Hantro G1 video encode and decode accelerators present on Rockchip SoCs.
|
||||
+
|
||||
+properties:
|
||||
+ compatible:
|
||||
+ enum:
|
||||
+ - rockchip,rk3288-vpu
|
||||
+ - rockchip,rk3328-vpu
|
||||
+ - rockchip,rk3399-vpu
|
||||
+
|
||||
+ reg:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ interrupts:
|
||||
+ maxItems: 2
|
||||
+
|
||||
+ interrupt-names:
|
||||
+ items:
|
||||
+ - const: vepu
|
||||
+ - const: vdpu
|
||||
+
|
||||
+ clocks:
|
||||
+ maxItems: 2
|
||||
+
|
||||
+ clock-names:
|
||||
+ items:
|
||||
+ - const: aclk
|
||||
+ - const: hclk
|
||||
+
|
||||
+ power-domains:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ iommus:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+required:
|
||||
+ - compatible
|
||||
+ - reg
|
||||
+ - interrupts
|
||||
+ - interrupt-names
|
||||
+ - clocks
|
||||
+ - clock-names
|
||||
+
|
||||
+examples:
|
||||
+ - |
|
||||
+ #include <dt-bindings/clock/rk3288-cru.h>
|
||||
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+
|
||||
+ vpu: video-codec@ff9a0000 {
|
||||
+ compatible = "rockchip,rk3288-vpu";
|
||||
+ reg = <0x0 0xff9a0000 0x0 0x800>;
|
||||
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "vepu", "vdpu";
|
||||
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
|
||||
+ clock-names = "aclk", "hclk";
|
||||
+ power-domains = <&power RK3288_PD_VIDEO>;
|
||||
+ iommus = <&vpu_mmu>;
|
||||
+ };
|
||||
+
|
||||
+ vpu: video-codec@ff350000 {
|
||||
+ compatible = "rockchip,rk3328-vpu";
|
||||
+ reg = <0x0 0xff350000 0x0 0x800>;
|
||||
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "vdpu";
|
||||
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
||||
+ clock-names = "aclk", "hclk";
|
||||
+ power-domains = <&power RK3328_PD_VPU>;
|
||||
+ iommus = <&vpu_mmu>;
|
||||
+ };
|
||||
|
||||
|
||||
|
||||
From 1eba04297572f566a06ab9fe50f901640c77b091 Mon Sep 17 00:00:00 2001
|
||||
From: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
Date: Wed, 18 Mar 2020 10:21:08 -0300
|
||||
Subject: [PATCH] hantro: Add linux-rockchip mailing list to MAINTAINERS
|
||||
|
||||
The linux-rockchip mailing list is relevant for the
|
||||
Hantro driver, given this support the VPU present
|
||||
in Rockchip SoCs.
|
||||
|
||||
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
MAINTAINERS | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/MAINTAINERS b/MAINTAINERS
|
||||
index ca95e804aae0..47876afb9e26 100644
|
||||
--- a/MAINTAINERS
|
||||
+++ b/MAINTAINERS
|
||||
@@ -14317,6 +14317,7 @@ F: Documentation/devicetree/bindings/media/rockchip-rga.txt
|
||||
HANTRO VPU CODEC DRIVER
|
||||
M: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
L: linux-media@vger.kernel.org
|
||||
+L: linux-rockchip@lists.infradead.org
|
||||
S: Maintained
|
||||
F: drivers/staging/media/hantro/
|
||||
F: Documentation/devicetree/bindings/media/rockchip-vpu.yaml
|
||||
--
|
||||
2.17.1
|
||||
|
||||
3500
patch/kernel/rk322x-current/01-linux-0021-drm-from-5.9.patch
Normal file
3500
patch/kernel/rk322x-current/01-linux-0021-drm-from-5.9.patch
Normal file
File diff suppressed because it is too large
Load diff
1276
patch/kernel/rk322x-current/01-linux-0022-drm-from-next.patch
Normal file
1276
patch/kernel/rk322x-current/01-linux-0022-drm-from-next.patch
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -1,98 +0,0 @@
|
|||
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
|
||||
index 0127d702720c..6ef71ec239ae 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3228.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3228.c
|
||||
@@ -353,7 +353,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
RK2928_CLKGATE_CON(10), 12, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
|
||||
- RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
|
||||
+ RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 15, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From 3acbbe5eb438e8b1061a803881579030d3c2b424 Mon Sep 17 00:00:00 2001
|
||||
From: Chen Lei <lei.chen@rock-chips.com>
|
||||
Date: Tue, 25 Dec 2018 18:29:04 +0800
|
||||
Subject: [PATCH] clk: rockchip: rk322x: fix wrong mmc phase shift for rk3228
|
||||
|
||||
mmc sample shift should be 1 for rk3228, or it will fail
|
||||
if we enable mmc tuning for rk3228.
|
||||
|
||||
Change-Id: I301c2a7d33de8d519d7c288aef03a82531016373
|
||||
Signed-off-by: Chen Lei <lei.chen@rock-chips.com>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3228.c | 6 +++---
|
||||
1 file changed, 3 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
|
||||
index 6ef71ec239ae..27adfca1a095 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3228.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3228.c
|
||||
@@ -610,13 +610,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
|
||||
/* PD_MMC */
|
||||
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
|
||||
- MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
|
||||
+ MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
|
||||
|
||||
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
|
||||
- MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0),
|
||||
+ MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1),
|
||||
|
||||
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
|
||||
- MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
|
||||
+ MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1),
|
||||
};
|
||||
|
||||
static const char *const rk3228_critical_clocks[] __initconst = {
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From a692001c1249473bdfe975ef53d2bdb8a4df736d Mon Sep 17 00:00:00 2001
|
||||
From: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Date: Mon, 5 Feb 2018 10:04:15 +0800
|
||||
Subject: [PATCH] clk: rockchip: rk3228: Fix armclk parent
|
||||
|
||||
Change-Id: I09830d96b37cca600f1782b9013b25e043467f97
|
||||
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3228.c | 8 +++++++-
|
||||
1 file changed, 7 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
|
||||
index 58292f80ad66..fba513de94eb 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3228.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3228.c
|
||||
@@ -170,7 +170,7 @@ static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
|
||||
[cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
|
||||
RK2928_MODE_CON, 8, 8, 0, NULL),
|
||||
[gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
|
||||
- RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
|
||||
+ RK2928_MODE_CON, 12, 9, 0, rk3228_pll_rates),
|
||||
};
|
||||
|
||||
#define MFLAGS CLK_MUX_HIWORD_MASK
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From f57d5061e7357a8f7a181517530658a223ba415b Mon Sep 17 00:00:00 2001
|
||||
From: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Date: Thu, 22 Jun 2017 19:53:46 +0800
|
||||
Subject: [PATCH] clk: rockchip: rk3228: fix gpu gate-register
|
||||
|
||||
Fix a typo making the aclk_gpu and aclk_gpu_noc access a wrong register to
|
||||
handle its gate.
|
||||
|
||||
Change-Id: Ie0bac8014363af7c0409b8a56eacf2e858818843
|
||||
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3228.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
diff --git a/mm/memory.c b/mm/memory.c
|
||||
index 606da18..8429abc 100644
|
||||
--- a/mm/memory.c
|
||||
+++ b/mm/memory.c
|
||||
@@ -158,6 +158,7 @@
|
||||
{
|
||||
trace_rss_stat(mm, member, count);
|
||||
}
|
||||
+EXPORT_SYMBOL(mm_trace_rss_stat);
|
||||
|
||||
#if defined(SPLIT_RSS_COUNTING)
|
||||
|
||||
|
|
@ -1,219 +0,0 @@
|
|||
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
|
||||
index 448b202bf4f3..828d0003a18e 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3228.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3228.c
|
||||
@@ -510,12 +510,12 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
|
||||
/* PD_VOP */
|
||||
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
|
||||
- GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
|
||||
+ GATE(0, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 11, GFLAGS),
|
||||
GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
|
||||
- GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
|
||||
+ GATE(0, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 9, GFLAGS),
|
||||
|
||||
GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
|
||||
- GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
|
||||
+ GATE(0, "aclk_vop_noc", "aclk_vop_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 12, GFLAGS),
|
||||
|
||||
GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
|
||||
GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
|
||||
@@ -523,13 +523,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
|
||||
GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
|
||||
GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
|
||||
- GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
|
||||
- GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
|
||||
- GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
|
||||
- GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
|
||||
+ GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 7, GFLAGS),
|
||||
+ GATE(0, "hclk_vio_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 8, GFLAGS),
|
||||
+ GATE(0, "hclk_vop_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 13, GFLAGS),
|
||||
+ GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(14), 7, GFLAGS),
|
||||
GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
|
||||
GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
|
||||
- GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
|
||||
+ GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(14), 8, GFLAGS),
|
||||
GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
|
||||
|
||||
/* PD_PERI */
|
||||
@@ -541,13 +541,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
|
||||
GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
|
||||
GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
|
||||
- GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
|
||||
+ GATE(0, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 7, GFLAGS),
|
||||
GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
|
||||
- GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
|
||||
+ GATE(0, "hclk_host1_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 9, GFLAGS),
|
||||
GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
|
||||
GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
|
||||
- GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
|
||||
- GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
|
||||
+ GATE(0, "hclk_otg_pmu", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 13, GFLAGS),
|
||||
+ GATE(0, "hclk_host2_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 14, GFLAGS),
|
||||
GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
|
||||
|
||||
GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
|
||||
@@ -555,15 +555,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
|
||||
/* PD_GPU */
|
||||
GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
|
||||
- GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
|
||||
+ GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 15, GFLAGS),
|
||||
|
||||
/* PD_BUS */
|
||||
- GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
|
||||
- GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
|
||||
+ GATE(0, "sclk_initmem_mbist", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 1, GFLAGS),
|
||||
+ GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 0, GFLAGS),
|
||||
GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
|
||||
GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
|
||||
|
||||
- GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
|
||||
+ GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 3, GFLAGS),
|
||||
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
|
||||
GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
|
||||
GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
|
||||
@@ -572,9 +572,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
|
||||
GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
|
||||
|
||||
- GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
|
||||
- GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
|
||||
- GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
|
||||
+ GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 4, GFLAGS),
|
||||
+ GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 6, GFLAGS),
|
||||
+ GATE(0, "pclk_msch_noc", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
|
||||
|
||||
GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
|
||||
GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
|
||||
@@ -583,7 +583,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
|
||||
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
|
||||
GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
|
||||
- GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
|
||||
+ GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 5, GFLAGS),
|
||||
GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
|
||||
GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
|
||||
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
|
||||
@@ -597,22 +597,22 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),
|
||||
GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
|
||||
GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
|
||||
- GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
|
||||
+ GATE(0, "pclk_sim", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 3, GFLAGS),
|
||||
|
||||
- GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
|
||||
- GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
|
||||
+ GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 3, GFLAGS),
|
||||
+ GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 5, GFLAGS),
|
||||
GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
|
||||
- GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
|
||||
- GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
|
||||
+ GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 8, GFLAGS),
|
||||
+ GATE(0, "pclk_phy_noc", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 9, GFLAGS),
|
||||
|
||||
GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
|
||||
- GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
|
||||
+ GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 4, GFLAGS),
|
||||
GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
|
||||
- GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
|
||||
+ GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 6, GFLAGS),
|
||||
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
|
||||
- GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
|
||||
+ GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 5, GFLAGS),
|
||||
GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
|
||||
- GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
|
||||
+ GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 7, GFLAGS),
|
||||
|
||||
/* PD_MMC */
|
||||
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
|
||||
@@ -656,25 +656,34 @@ static const char *const rk3228_critical_clocks[] __initconst = {
|
||||
"pclk_phy_noc",
|
||||
"aclk_vpu_noc",
|
||||
"aclk_rkvdec_noc",
|
||||
+ "aclk_rkvdec",
|
||||
"hclk_vpu_noc",
|
||||
"hclk_rkvdec_noc",
|
||||
+ "hclk_rkvdec",
|
||||
};
|
||||
|
||||
+static void __iomem *rk3228_cru_base;
|
||||
+
|
||||
+static void rk3228_clk_shutdown(void)
|
||||
+{
|
||||
+ writel_relaxed(0x11010000, rk3228_cru_base + RK3228_MODE_CON);
|
||||
+}
|
||||
+
|
||||
static void __init rk3228_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
- void __iomem *reg_base;
|
||||
|
||||
- reg_base = of_iomap(np, 0);
|
||||
- if (!reg_base) {
|
||||
+ rk3228_cru_base = of_iomap(np, 0);
|
||||
+
|
||||
+ if (!rk3228_cru_base) {
|
||||
pr_err("%s: could not map cru region\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
- ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
+ ctx = rockchip_clk_init(np, rk3228_cru_base, CLK_NR_CLKS);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
- iounmap(reg_base);
|
||||
+ iounmap(rk3228_cru_base);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -691,10 +700,10 @@ static void __init rk3228_clk_init(struct device_node *np)
|
||||
&rk3228_cpuclk_data, rk3228_cpuclk_rates,
|
||||
ARRAY_SIZE(rk3228_cpuclk_rates));
|
||||
|
||||
- rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
|
||||
+ rockchip_register_softrst(np, 9, rk3228_cru_base + RK2928_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
|
||||
- rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL);
|
||||
+ rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, rk3228_clk_shutdown);
|
||||
|
||||
rockchip_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
|
||||
index 2271a84124b0..f2f80f224f30 100644
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -134,6 +134,7 @@ struct clk;
|
||||
#define RK3308_EMMC_CON0 0x490
|
||||
#define RK3308_EMMC_CON1 0x494
|
||||
|
||||
+#define RK3228_MODE_CON 0x40
|
||||
#define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
||||
#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
|
||||
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
|
||||
index de550ea56eeb..16e1feae5ce4 100644
|
||||
--- a/include/dt-bindings/clock/rk3228-cru.h
|
||||
+++ b/include/dt-bindings/clock/rk3228-cru.h
|
||||
@@ -65,6 +65,7 @@
|
||||
#define SCLK_OTGPHY0 142
|
||||
#define SCLK_OTGPHY1 143
|
||||
#define SCLK_HDMI_PHY 144
|
||||
+#define SCLK_DDRC 145
|
||||
|
||||
/* dclk gates */
|
||||
#define DCLK_VOP 190
|
||||
@@ -115,6 +116,7 @@
|
||||
#define PCLK_HDMI_CTRL 364
|
||||
#define PCLK_HDMI_PHY 365
|
||||
#define PCLK_GMAC 367
|
||||
+#define PCLK_ACODECPHY 368
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_I2S0_8CH 442
|
||||
--
|
||||
2.17.1
|
||||
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,98 +0,0 @@
|
|||
diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
|
||||
index a0c45e05cf03..a20cfaa8973e 100644
|
||||
--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
|
||||
+++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
|
||||
@@ -16,6 +16,7 @@ description:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
+ - rockchip,rk322x-vpu
|
||||
- rockchip,rk3288-vpu
|
||||
- rockchip,rk3328-vpu
|
||||
- rockchip,rk3399-vpu
|
||||
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
|
||||
index f7a50b903a7d..2ed8aa7ae520 100644
|
||||
--- a/arch/arm/boot/dts/rk322x.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk322x.dtsi
|
||||
@@ -676,6 +676,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ vpu: video-codec@20020000 {
|
||||
+ compatible = "rockchip,rk322x-vpu";
|
||||
+ reg = <0x20020000 0x800>;
|
||||
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "vepu", "vdpu";
|
||||
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
||||
+ clock-names = "aclk", "hclk";
|
||||
+ iommus = <&vpu_mmu>;
|
||||
+ power-domains = <&power RK3228_PD_VPU>;
|
||||
+ };
|
||||
+
|
||||
vpu_mmu: iommu@20020800 {
|
||||
compatible = "rockchip,iommu";
|
||||
reg = <0x20020800 0x100>;
|
||||
diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig
|
||||
index de77fe6554e7..9f99d1c9f453 100644
|
||||
--- a/drivers/staging/media/hantro/Kconfig
|
||||
+++ b/drivers/staging/media/hantro/Kconfig
|
||||
@@ -20,4 +20,4 @@ config VIDEO_HANTRO_ROCKCHIP
|
||||
depends on ARCH_ROCKCHIP || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
- Enable support for RK3288, RK3328, and RK3399 SoCs.
|
||||
+ Enable support for RK322x, RK3288, RK3328, and RK3399 SoCs.
|
||||
diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
|
||||
index a732beeb3bb6..fae9555a349b 100644
|
||||
--- a/drivers/staging/media/hantro/hantro_drv.c
|
||||
+++ b/drivers/staging/media/hantro/hantro_drv.c
|
||||
@@ -469,6 +469,7 @@ static const struct of_device_id of_hantro_match[] = {
|
||||
{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
|
||||
{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
|
||||
{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
|
||||
+ { .compatible = "rockchip,rk322x-vpu", .data = &rk322x_vpu_variant, },
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
|
||||
index 33c1ce169203..e64369e01a21 100644
|
||||
--- a/drivers/staging/media/hantro/hantro_hw.h
|
||||
+++ b/drivers/staging/media/hantro/hantro_hw.h
|
||||
@@ -157,6 +157,7 @@ enum hantro_enc_fmt {
|
||||
extern const struct hantro_variant rk3399_vpu_variant;
|
||||
extern const struct hantro_variant rk3328_vpu_variant;
|
||||
extern const struct hantro_variant rk3288_vpu_variant;
|
||||
+extern const struct hantro_variant rk322x_vpu_variant;
|
||||
extern const struct hantro_variant imx8mq_vpu_variant;
|
||||
|
||||
extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
|
||||
|
||||
diff --git a/drivers/staging/media/hantro/rk3399_vpu_hw.c b/drivers/staging/media/hantro/rk3399_vpu_hw.c
|
||||
index 78f878ca01ff..0a6c021c2332 100644
|
||||
--- a/drivers/staging/media/hantro/rk3399_vpu_hw.c
|
||||
+++ b/drivers/staging/media/hantro/rk3399_vpu_hw.c
|
||||
@@ -241,3 +241,20 @@ const struct hantro_variant rk3328_vpu_variant = {
|
||||
.clk_names = rk3399_clk_names,
|
||||
.num_clocks = ARRAY_SIZE(rk3399_clk_names),
|
||||
};
|
||||
+
|
||||
+const struct hantro_variant rk322x_vpu_variant = {
|
||||
+ .enc_offset = 0x0,
|
||||
+ .enc_fmts = rk3399_vpu_enc_fmts,
|
||||
+ .num_enc_fmts = ARRAY_SIZE(rk3399_vpu_enc_fmts),
|
||||
+ .dec_offset = 0x400,
|
||||
+ .dec_fmts = rk3399_vpu_dec_fmts,
|
||||
+ .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
|
||||
+ .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
|
||||
+ HANTRO_H264_DECODER,
|
||||
+ .codec_ops = rk3399_vpu_codec_ops,
|
||||
+ .irqs = rk3399_irqs,
|
||||
+ .num_irqs = ARRAY_SIZE(rk3399_irqs),
|
||||
+ .init = rk3399_vpu_hw_init,
|
||||
+ .clk_names = rk3399_clk_names,
|
||||
+ .num_clocks = ARRAY_SIZE(rk3399_clk_names)
|
||||
+};
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
|
@ -1,383 +0,0 @@
|
|||
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
|
||||
index 54eb6cfc5d5b..c6b33f7c43df 100644
|
||||
--- a/drivers/soc/rockchip/pm_domains.c
|
||||
+++ b/drivers/soc/rockchip/pm_domains.c
|
||||
@@ -71,6 +71,7 @@ struct rockchip_pm_domain {
|
||||
struct regmap **qos_regmap;
|
||||
u32 *qos_save_regs[MAX_QOS_REGS_NUM];
|
||||
int num_clks;
|
||||
+ bool is_ignore_pwr;
|
||||
struct clk_bulk_data *clks;
|
||||
};
|
||||
|
||||
@@ -330,6 +331,9 @@ static int rockchip_pd_power_on(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
|
||||
|
||||
+ if (pd->is_ignore_pwr)
|
||||
+ return 0;
|
||||
+
|
||||
return rockchip_pd_power(pd, true);
|
||||
}
|
||||
|
||||
@@ -337,6 +341,9 @@ static int rockchip_pd_power_off(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
|
||||
|
||||
+ if (pd->is_ignore_pwr)
|
||||
+ return 0;
|
||||
+
|
||||
return rockchip_pd_power(pd, false);
|
||||
}
|
||||
|
||||
@@ -416,6 +423,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
|
||||
pd->info = pd_info;
|
||||
pd->pmu = pmu;
|
||||
|
||||
+ if (!pd_info->pwr_mask)
|
||||
+ pd->is_ignore_pwr = true;
|
||||
+
|
||||
pd->num_clks = of_clk_get_parent_count(node);
|
||||
if (pd->num_clks > 0) {
|
||||
pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
|
||||
@@ -566,6 +576,7 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
|
||||
{
|
||||
struct device_node *np;
|
||||
struct generic_pm_domain *child_domain, *parent_domain;
|
||||
+ struct rockchip_pm_domain *child_pd, *parent_pd;
|
||||
int error;
|
||||
|
||||
for_each_child_of_node(parent, np) {
|
||||
@@ -606,6 +617,18 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
|
||||
parent_domain->name, child_domain->name);
|
||||
}
|
||||
|
||||
+ /*
|
||||
+ * If child_pd doesn't do idle request or power on/off,
|
||||
+ * parent_pd may fail to do power on/off, so if parent_pd
|
||||
+ * need to power on/off, child_pd can't ignore to do idle
|
||||
+ * request and power on/off.
|
||||
+ */
|
||||
+ child_pd = to_rockchip_pd(child_domain);
|
||||
+ parent_pd = to_rockchip_pd(parent_domain);
|
||||
+ if (!parent_pd->is_ignore_pwr)
|
||||
+ child_pd->is_ignore_pwr = false;
|
||||
+
|
||||
+
|
||||
rockchip_pm_add_subdomain(pmu, np);
|
||||
}
|
||||
|
||||
--
|
||||
2.17.1
|
||||
|
||||
From c94b1272290bafced10d79b7da1525466e8c843b Mon Sep 17 00:00:00 2001
|
||||
From: "Huang, Tao" <huangtao@rock-chips.com>
|
||||
Date: Thu, 28 Jul 2016 10:59:22 +0800
|
||||
Subject: [PATCH] power: reset: reboot-mode: fix normal mode setup
|
||||
|
||||
If cmd is empty in get_reboot_mode_magic, we should return normal magic.
|
||||
|
||||
Change-Id: I10931adc49e33f72ae73d9471159f82cc02ff0c0
|
||||
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
|
||||
---
|
||||
drivers/power/reset/reboot-mode.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/power/reset/reboot-mode.c b/drivers/power/reset/reboot-mode.c
|
||||
index b4076b10b893..47f9a162807d 100644
|
||||
--- a/drivers/power/reset/reboot-mode.c
|
||||
+++ b/drivers/power/reset/reboot-mode.c
|
||||
@@ -26,7 +26,7 @@ static unsigned int get_reboot_mode_magic(struct reboot_mode_driver *reboot,
|
||||
int magic = 0;
|
||||
struct mode_info *info;
|
||||
|
||||
- if (!cmd)
|
||||
+ if (!cmd || !cmd[0])
|
||||
cmd = normal;
|
||||
|
||||
list_for_each_entry(info, &reboot->head, list) {
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From be9674f270c97399f9f6b1facb11e93eced6ec34 Mon Sep 17 00:00:00 2001
|
||||
From: Andy Yan <andy.yan@rock-chips.com>
|
||||
Date: Thu, 8 Dec 2016 16:58:07 +0800
|
||||
Subject: [PATCH] power: reset: reboot-mode: treat unrecognized reboot mode as
|
||||
normal mode
|
||||
|
||||
Some bootloader will check the reboot mode to take different action, so
|
||||
we treat unrecognized reboot mode as normal mode to prevent the system
|
||||
run into abnormal case.
|
||||
|
||||
Change-Id: I88063a5b41e4e645443229fa490b2b55db5ccf27
|
||||
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
|
||||
---
|
||||
drivers/power/reset/reboot-mode.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/drivers/power/reset/reboot-mode.c b/drivers/power/reset/reboot-mode.c
|
||||
index 47f9a162807d..99bf938404e3 100644
|
||||
--- a/drivers/power/reset/reboot-mode.c
|
||||
+++ b/drivers/power/reset/reboot-mode.c
|
||||
@@ -47,6 +47,8 @@ static int reboot_mode_notify(struct notifier_block *this,
|
||||
|
||||
reboot = container_of(this, struct reboot_mode_driver, reboot_notifier);
|
||||
magic = get_reboot_mode_magic(reboot, cmd);
|
||||
+ if (!magic)
|
||||
+ magic = get_reboot_mode_magic(reboot, NULL);
|
||||
if (magic)
|
||||
reboot->write(reboot, magic);
|
||||
|
||||
--
|
||||
2.17.1
|
||||
|
||||
From 7c097120eb21a9bd15ab63c0ac60ffd5cba902b2 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Fri, 24 Apr 2020 13:01:07 +0200
|
||||
Subject: [PATCH] sound: soc: rockchip: use rouned rate for i2s
|
||||
|
||||
---
|
||||
sound/soc/rockchip/rockchip_i2s.c | 9 +++++++--
|
||||
1 file changed, 7 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
|
||||
index 61c984f10d8e..efca853eba6b 100644
|
||||
--- a/sound/soc/rockchip/rockchip_i2s.c
|
||||
+++ b/sound/soc/rockchip/rockchip_i2s.c
|
||||
@@ -279,10 +279,13 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
|
||||
if (i2s->is_master_mode) {
|
||||
mclk_rate = clk_get_rate(i2s->mclk);
|
||||
bclk_rate = 2 * 32 * params_rate(params);
|
||||
- if (bclk_rate && mclk_rate % bclk_rate)
|
||||
+ if (!bclk_rate) {
|
||||
+ dev_err(i2s->dev, "invalid bclk_rate: %d\n",
|
||||
+ bclk_rate);
|
||||
return -EINVAL;
|
||||
+ }
|
||||
|
||||
- div_bclk = mclk_rate / bclk_rate;
|
||||
+ div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
|
||||
div_lrck = bclk_rate / params_rate(params);
|
||||
regmap_update_bits(i2s->regmap, I2S_CKR,
|
||||
I2S_CKR_MDIV_MASK,
|
||||
@@ -312,6 +315,8 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
|
||||
val |= I2S_TXCR_VDW(32);
|
||||
break;
|
||||
default:
|
||||
+ dev_err(i2s->dev, "invalid format: %d\n",
|
||||
+ params_format(params));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From 4102c5b07d8610c729d577612c1df52737fb9a0f Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Fri, 24 Apr 2020 09:08:44 +0200
|
||||
Subject: [PATCH] phy: rockchip: hdmi: readout hdmi phy flag for RK3228 HDMI
|
||||
phys
|
||||
|
||||
Some RK3228 HDMI phys only get a stable pll on frequencies higher 337,5 MHz.
|
||||
This is defined in a flag in efuse of those devices.
|
||||
---
|
||||
arch/arm/boot/dts/rk322x.dtsi | 7 ++++
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 38 ++++++++++++++++++-
|
||||
2 files changed, 43 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
|
||||
index 2ed8aa7ae520..8c50dcb0e9f1 100644
|
||||
--- a/arch/arm/boot/dts/rk322x.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk322x.dtsi
|
||||
@@ -402,6 +402,11 @@
|
||||
cpu_leakage: cpu_leakage@17 {
|
||||
reg = <0x17 0x1>;
|
||||
};
|
||||
+
|
||||
+ hdmi_phy_flag: hdmi-phy-flag@1d {
|
||||
+ reg = <0x1d 0x1>;
|
||||
+ bits = <1 1>;
|
||||
+ };
|
||||
};
|
||||
|
||||
i2c0: i2c@11050000 {
|
||||
@@ -628,6 +633,8 @@
|
||||
clock-names = "sysclk", "refoclk", "refpclk";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "hdmiphy_phy";
|
||||
+ nvmem-cells = <&hdmi_phy_flag>;
|
||||
+ nvmem-cell-names = "hdmi-phy-flag";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index bb8bdf5e3301..0c7a97352714 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -237,6 +237,9 @@ struct inno_hdmi_phy {
|
||||
struct clk *refoclk;
|
||||
struct clk *refpclk;
|
||||
|
||||
+ /* phy_flag flag */
|
||||
+ bool phy_flag;
|
||||
+
|
||||
/* platform data */
|
||||
const struct inno_hdmi_phy_drv_data *plat_data;
|
||||
int chip_version;
|
||||
@@ -347,6 +350,7 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
|
||||
static const struct post_pll_config post_pll_cfg_table[] = {
|
||||
{33750000, 1, 40, 8, 1},
|
||||
{33750000, 1, 80, 8, 2},
|
||||
+ {33750000, 1, 10, 2, 4},
|
||||
{74250000, 1, 40, 8, 1},
|
||||
{74250000, 18, 80, 8, 2},
|
||||
{148500000, 2, 40, 4, 3},
|
||||
@@ -497,8 +501,11 @@ static int inno_hdmi_phy_power_on(struct phy *phy)
|
||||
return -EINVAL;
|
||||
|
||||
for (; cfg->tmdsclock != 0; cfg++)
|
||||
- if (tmdsclock <= cfg->tmdsclock &&
|
||||
- cfg->version & inno->chip_version)
|
||||
+ if (((!inno->phy_flag || tmdsclock > 33750000)
|
||||
+ && tmdsclock <= cfg->tmdsclock
|
||||
+ && cfg->version & inno->chip_version) ||
|
||||
+ (inno->phy_flag && tmdsclock <= 33750000
|
||||
+ && cfg->version & 4))
|
||||
break;
|
||||
|
||||
for (; phy_cfg->tmdsclock != 0; phy_cfg++)
|
||||
@@ -909,6 +916,10 @@ static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
|
||||
|
||||
static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
|
||||
{
|
||||
+ struct nvmem_cell *cell;
|
||||
+ unsigned char *efuse_buf;
|
||||
+ size_t len;
|
||||
+
|
||||
/*
|
||||
* Use phy internal register control
|
||||
* rxsense/poweron/pllpd/pdataen signal.
|
||||
@@ -923,7 +934,28 @@ static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
|
||||
inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
|
||||
RK3228_POST_PLL_CTRL_MANUAL);
|
||||
|
||||
+
|
||||
inno->chip_version = 1;
|
||||
+ inno->phy_flag = false;
|
||||
+
|
||||
+ cell = nvmem_cell_get(inno->dev, "hdmi-phy-flag");
|
||||
+ if (IS_ERR(cell)) {
|
||||
+ if (PTR_ERR(cell) == -EPROBE_DEFER)
|
||||
+ return -EPROBE_DEFER;
|
||||
+
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ efuse_buf = nvmem_cell_read(cell, &len);
|
||||
+ nvmem_cell_put(cell);
|
||||
+
|
||||
+ if (IS_ERR(efuse_buf))
|
||||
+ return 0;
|
||||
+ if (len == 1)
|
||||
+ inno->phy_flag = (efuse_buf[0] & BIT(1)) ? true : false;
|
||||
+ kfree(efuse_buf);
|
||||
+
|
||||
+ dev_info(inno->dev, "phy_flag is: %d\n", inno->phy_flag);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1023,6 +1055,8 @@ static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
|
||||
|
||||
/* try to read the chip-version */
|
||||
inno->chip_version = 1;
|
||||
+ inno->phy_flag = false;
|
||||
+
|
||||
cell = nvmem_cell_get(inno->dev, "cpu-version");
|
||||
if (IS_ERR(cell)) {
|
||||
if (PTR_ERR(cell) == -EPROBE_DEFER)
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
From fe30b024a7a7d6261dff0b87c2aec270ad530c39 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Fri, 24 Apr 2020 14:23:38 +0200
|
||||
Subject: [PATCH] drm: rockchip: Use 2nd RK3228 plane as an overlay
|
||||
|
||||
As per datasheet the second plane of RK3228 vop is an overlay window. For
|
||||
the missing implementation of hardware cursor it is missued as such (as
|
||||
already pointed in comment for RK3288). Furthermore the overlay window
|
||||
does not support YUV modes with the current implementation - so it
|
||||
supports only RGB modes for now.
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 44 +++++++++++++++++++--
|
||||
1 file changed, 41 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
index 73d24c6bbf05..d4ac6e161ef2 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
@@ -614,6 +614,44 @@ static const struct vop_common rk3288_common = {
|
||||
.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
|
||||
};
|
||||
|
||||
+static const struct vop_win_phy rk3228_win0_data = {
|
||||
+ .scl = &rk3288_win_full_scl,
|
||||
+ .data_formats = formats_win_full,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_full),
|
||||
+ .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
+ .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
+ .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
+ .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
+ .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
|
||||
+ .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
|
||||
+ .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
|
||||
+ .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
|
||||
+ .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
|
||||
+ .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
|
||||
+ .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
|
||||
+ .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
|
||||
+};
|
||||
+
|
||||
+static const struct vop_win_phy rk3228_win1_data = {
|
||||
+ .scl = &rk3288_win_full_scl,
|
||||
+ .data_formats = formats_win_lite,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_lite),
|
||||
+ .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
+ .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
+ .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
+ .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
+ .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
|
||||
+ .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
|
||||
+ .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
|
||||
+ .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
|
||||
+ .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
|
||||
+ .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
|
||||
+ .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
|
||||
+ .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
|
||||
+};
|
||||
+
|
||||
/*
|
||||
* Note: rk3288 has a dedicated 'cursor' window, however, that window requires
|
||||
* special support to get alpha blending working. For now, just use overlay
|
||||
@@ -864,10 +902,10 @@ static const struct vop_data rk3399_vop_lit = {
|
||||
};
|
||||
|
||||
static const struct vop_win_data rk3228_vop_win_data[] = {
|
||||
- { .base = 0x00, .phy = &rk3288_win01_data,
|
||||
+ { .base = 0x00, .phy = &rk3228_win0_data,
|
||||
.type = DRM_PLANE_TYPE_PRIMARY },
|
||||
- { .base = 0x40, .phy = &rk3288_win01_data,
|
||||
- .type = DRM_PLANE_TYPE_CURSOR },
|
||||
+ { .base = 0x40, .phy = &rk3228_win1_data,
|
||||
+ .type = DRM_PLANE_TYPE_OVERLAY },
|
||||
};
|
||||
|
||||
static const struct vop_data rk3228_vop = {
|
||||
--
|
||||
2.17.1
|
||||
|
||||
5333
patch/kernel/rk322x-current/01-linux-2000-rockchip-drm-wip.patch
Normal file
5333
patch/kernel/rk322x-current/01-linux-2000-rockchip-drm-wip.patch
Normal file
File diff suppressed because it is too large
Load diff
4647
patch/kernel/rk322x-current/01-linux-3000-rockchip-v4l-wip.patch
Normal file
4647
patch/kernel/rk322x-current/01-linux-3000-rockchip-v4l-wip.patch
Normal file
File diff suppressed because it is too large
Load diff
1692
patch/kernel/rk322x-current/01-linux-4000-rockchip-linux-wip.patch
Normal file
1692
patch/kernel/rk322x-current/01-linux-4000-rockchip-linux-wip.patch
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,912 @@
|
|||
From 71fba6c19fa57e219657226d3d20528ebec86def Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sun, 16 Aug 2020 23:03:12 +0200
|
||||
Subject: [PATCH] WIP: ARM: dts: add RK322x box device trees
|
||||
|
||||
---
|
||||
arch/arm/boot/dts/Makefile | 4 +
|
||||
arch/arm/boot/dts/rk3228a-box-h96mini.dts | 115 +++++++++
|
||||
arch/arm/boot/dts/rk3228a-box.dts | 47 ++++
|
||||
arch/arm/boot/dts/rk3228a-box.dtsi | 12 +
|
||||
arch/arm/boot/dts/rk3229-box-a95xr1.dts | 57 ++++
|
||||
arch/arm/boot/dts/rk3229-box.dts | 50 ++++
|
||||
arch/arm/boot/dts/rk3229-box.dtsi | 21 ++
|
||||
arch/arm/boot/dts/rk3229-cpu-opp.dtsi | 50 ++++
|
||||
arch/arm/boot/dts/rk322x-box-dcdc.dtsi | 164 ++++++++++++
|
||||
arch/arm/boot/dts/rk322x-box.dtsi | 301 ++++++++++++++++++++++
|
||||
10 files changed, 821 insertions(+)
|
||||
create mode 100644 arch/arm/boot/dts/rk3228a-box-h96mini.dts
|
||||
create mode 100644 arch/arm/boot/dts/rk3228a-box.dts
|
||||
create mode 100644 arch/arm/boot/dts/rk3228a-box.dtsi
|
||||
create mode 100644 arch/arm/boot/dts/rk3229-box-a95xr1.dts
|
||||
create mode 100644 arch/arm/boot/dts/rk3229-box.dts
|
||||
create mode 100644 arch/arm/boot/dts/rk3229-box.dtsi
|
||||
create mode 100644 arch/arm/boot/dts/rk3229-cpu-opp.dtsi
|
||||
create mode 100644 arch/arm/boot/dts/rk322x-box-dcdc.dtsi
|
||||
create mode 100644 arch/arm/boot/dts/rk322x-box.dtsi
|
||||
|
||||
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
|
||||
index e6a1cac0bfc7..1e633e4aa5a2 100644
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -961,7 +961,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
||||
rk3188-bqedison2qc.dtb \
|
||||
rk3188-px3-evb.dtb \
|
||||
rk3188-radxarock.dtb \
|
||||
+ rk3228a-box.dtb \
|
||||
+ rk3228a-box-h96mini.dtb \
|
||||
rk3228-evb.dtb \
|
||||
+ rk3229-box.dtb \
|
||||
+ rk3229-box-a95xr1.dtb \
|
||||
rk3229-evb.dtb \
|
||||
rk3229-xms6.dtb \
|
||||
rk3288-evb-act8846.dtb \
|
||||
diff --git a/arch/arm/boot/dts/rk3228a-box-h96mini.dts b/arch/arm/boot/dts/rk3228a-box-h96mini.dts
|
||||
new file mode 100644
|
||||
index 000000000000..1041b6737d40
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk3228a-box-h96mini.dts
|
||||
@@ -0,0 +1,115 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include "rk3228a-box.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "eledvb,h96mini", "rockchip,rk3228a-box", "rockchip,rk3229";
|
||||
+ model = "Rockchip RK3228A Box H96 mini";
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led_green {
|
||||
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "on";
|
||||
+ };
|
||||
+
|
||||
+ led_red {
|
||||
+ gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ openvfd {
|
||||
+ compatible = "open,vfd";
|
||||
+ dev_name = "openvfd";
|
||||
+ openvfd_gpio_clk = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ openvfd_gpio_dat = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
|
||||
+ openvfd_display_type = <0x06000100>;
|
||||
+ openvfd_dot_bits = [00 01 03 02 04 05 06];
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&emmc {
|
||||
+ mmc-hs200-1_8v;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ tx_delay = <0x26>;
|
||||
+ rx_delay = <0x11>;
|
||||
+};
|
||||
+
|
||||
+&ir_receiver {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ wifi {
|
||||
+ wifi_host_wake_l: wifi-host-wake-l {
|
||||
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ bt {
|
||||
+ bt_host_wake_l: bt-host-wake-l {
|
||||
+ rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ bt_reg_on_h: bt-reg-on-h {
|
||||
+ rockchip,pins = <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ bt_wake_l: bt-wake-l {
|
||||
+ rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&power_key {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdio {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ brcmf: wifi@1 {
|
||||
+ compatible = "brcm,bcm4329-fmac";
|
||||
+ reg = <1>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ interrupt-names = "host-wake";
|
||||
+ brcm,drive-strength = <5>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_host_wake_l>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ disable-wp;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ bluetooth {
|
||||
+ compatible = "brcm,bcm4330-bt";
|
||||
+ host-wakeup-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
+ device-wakeup-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>;
|
||||
+ shutdown-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
+ max-speed = <4000000>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&usb_otg {
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/rk3228a-box.dts b/arch/arm/boot/dts/rk3228a-box.dts
|
||||
new file mode 100644
|
||||
index 000000000000..e68ef44b95c9
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk3228a-box.dts
|
||||
@@ -0,0 +1,47 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3228a-box.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Rockchip RK3228A Box";
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led_blue {
|
||||
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "on";
|
||||
+ };
|
||||
+
|
||||
+ led_red {
|
||||
+ gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&emmc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&ir_receiver {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdio {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_otg {
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/rk3228a-box.dtsi b/arch/arm/boot/dts/rk3228a-box.dtsi
|
||||
new file mode 100644
|
||||
index 000000000000..056945c6c9a7
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk3228a-box.dtsi
|
||||
@@ -0,0 +1,12 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "rk322x-box-dcdc.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+
|
||||
+ model = "Rockchip RK3228A Box";
|
||||
+ compatible = "rockchip,rk3228a-box", "rockchip,rk3229";
|
||||
+
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/rk3229-box-a95xr1.dts b/arch/arm/boot/dts/rk3229-box-a95xr1.dts
|
||||
new file mode 100644
|
||||
index 000000000000..b3695fb0b255
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk3229-box-a95xr1.dts
|
||||
@@ -0,0 +1,57 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include "rk3229-box.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Rockchip RK3229 Box A95X-R1";
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led_blue {
|
||||
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "on";
|
||||
+ };
|
||||
+
|
||||
+ led_red {
|
||||
+ gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ linux,default-trigger = "rc-feedback";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&emmc {
|
||||
+ mmc-hs200-1_8v;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ tx_delay = <0x26>;
|
||||
+ rx_delay = <0x11>;
|
||||
+};
|
||||
+
|
||||
+&ir_receiver {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&power_key {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdio {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ disable-wp;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_otg {
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/rk3229-box.dts b/arch/arm/boot/dts/rk3229-box.dts
|
||||
new file mode 100644
|
||||
index 000000000000..b63e61cda257
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk3229-box.dts
|
||||
@@ -0,0 +1,50 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3229-box.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Rockchip RK3229 Box";
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led_green {
|
||||
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "on";
|
||||
+ };
|
||||
+
|
||||
+ led_red {
|
||||
+ gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&emmc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&ir_receiver {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&power_key {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdio {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_otg {
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/rk3229-box.dtsi b/arch/arm/boot/dts/rk3229-box.dtsi
|
||||
new file mode 100644
|
||||
index 000000000000..84f98fc53ebf
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk3229-box.dtsi
|
||||
@@ -0,0 +1,21 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "rk322x-box-dcdc.dtsi"
|
||||
+#include "rk3229-cpu-opp.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+
|
||||
+ model = "Rockchip RK3229 Box";
|
||||
+ compatible = "rockchip,rk3229-box", "rockchip,rk3229";
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&cpu0_opp_table {
|
||||
+
|
||||
+ opp-1464000000 {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/rk3229-cpu-opp.dtsi b/arch/arm/boot/dts/rk3229-cpu-opp.dtsi
|
||||
new file mode 100644
|
||||
index 000000000000..c1c7613bab11
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk3229-cpu-opp.dtsi
|
||||
@@ -0,0 +1,50 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
+ */
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "rockchip,rk3229";
|
||||
+
|
||||
+ /delete-node/ opp-table0;
|
||||
+
|
||||
+ cpu0_opp_table: opp_table0 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-408000000 {
|
||||
+ opp-hz = /bits/ 64 <408000000>;
|
||||
+ opp-microvolt = <950000 950000 1400000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ opp-suspend;
|
||||
+ };
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <975000 975000 1400000>;
|
||||
+ };
|
||||
+ opp-816000000 {
|
||||
+ opp-hz = /bits/ 64 <816000000>;
|
||||
+ opp-microvolt = <1000000 1000000 1400000>;
|
||||
+ };
|
||||
+ opp-1008000000 {
|
||||
+ opp-hz = /bits/ 64 <1008000000>;
|
||||
+ opp-microvolt = <1175000 1175000 1400000>;
|
||||
+ };
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt = <1275000 1275000 1400000>;
|
||||
+ };
|
||||
+ opp-1296000000 {
|
||||
+ opp-hz = /bits/ 64 <1296000000>;
|
||||
+ opp-microvolt = <1325000 1325000 1400000>;
|
||||
+ };
|
||||
+ opp-1392000000 {
|
||||
+ opp-hz = /bits/ 64 <1392000000>;
|
||||
+ opp-microvolt = <1350000 1350000 1400000>;
|
||||
+ };
|
||||
+ opp-1464000000 {
|
||||
+ opp-hz = /bits/ 64 <1464000000>;
|
||||
+ opp-microvolt = <1400000 1400000 1400000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/rk322x-box-dcdc.dtsi b/arch/arm/boot/dts/rk322x-box-dcdc.dtsi
|
||||
new file mode 100644
|
||||
index 000000000000..b2e47c5b4693
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk322x-box-dcdc.dtsi
|
||||
@@ -0,0 +1,164 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include "rk322x-box.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+
|
||||
+ vcc_host: vcc-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&host_vbus_drv>;
|
||||
+ regulator-name = "vcc_host";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vccio_1v8: vccio-1v8-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vccio_1v8";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vccio_3v3: vccio-3v3-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vccio_3v3";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+
|
||||
+ vcc_otg: vcc-otg-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&otg_vbus_drv>;
|
||||
+ regulator-name = "vcc_otg_vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_phy: vcc-phy-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ regulator-name = "vcc_phy";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vccio_1v8>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sys: vcc-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_arm: vdd-arm-regulator {
|
||||
+ compatible = "pwm-regulator";
|
||||
+ pwms = <&pwm1 0 5000 1>;
|
||||
+ pwm-supply = <&vcc_sys>;
|
||||
+ regulator-name = "vdd_arm";
|
||||
+ regulator-min-microvolt = <950000>;
|
||||
+ regulator-max-microvolt = <1400000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-settling-time-up-us = <250>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+
|
||||
+ vdd_log: vdd-log-regulator {
|
||||
+ compatible = "pwm-regulator";
|
||||
+ pwms = <&pwm2 0 5000 1>;
|
||||
+ pwm-supply = <&vcc_sys>;
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-min-microvolt = <1000000>;
|
||||
+ regulator-max-microvolt = <1300000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-settling-time-up-us = <250>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
+
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ vccio1-supply = <&vccio_3v3>;
|
||||
+ vccio2-supply = <&vccio_1v8>;
|
||||
+ vccio4-supply = <&vccio_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ phy-supply = <&vcc_phy>;
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_log>;
|
||||
+};
|
||||
+
|
||||
+&pwm1 {
|
||||
+ pinctrl-0 = <&pwm1_pin_pull_down>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ pinctrl-0 = <&pwm2_pin_pull_up>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0 {
|
||||
+ u2phy0_host: host-port {
|
||||
+ phy-supply = <&vcc_host>;
|
||||
+ };
|
||||
+
|
||||
+ u2phy0_otg: otg-port {
|
||||
+ phy-supply = <&vcc_otg>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&u2phy1 {
|
||||
+ u2phy1_host: host-port {
|
||||
+ phy-supply = <&vcc_host>;
|
||||
+ };
|
||||
+
|
||||
+ u2phy1_otg: otg-port {
|
||||
+ phy-supply = <&vcc_otg>;
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/rk322x-box.dtsi b/arch/arm/boot/dts/rk322x-box.dtsi
|
||||
new file mode 100644
|
||||
index 000000000000..02c9b3540f38
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk322x-box.dtsi
|
||||
@@ -0,0 +1,299 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/clock/rk3228-cru.h>
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include "rk322x.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Rockchip RK322x Box";
|
||||
+ compatible = "rockchip,rk3229";
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "earlyprintk=uart8250,mmio32,0x11030000";
|
||||
+ };
|
||||
+
|
||||
+ gpio_keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ autorepeat;
|
||||
+
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwr_key>;
|
||||
+
|
||||
+ power_key: power-key {
|
||||
+ label = "GPIO Key Power";
|
||||
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
|
||||
+ linux,code = <KEY_POWER>;
|
||||
+ debounce-interval = <100>;
|
||||
+ wakeup-source;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ir_receiver: ir-receiver {
|
||||
+ compatible = "gpio-ir-receiver";
|
||||
+ gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-0 = <&ir_int>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ memory@60000000 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x60000000 0x40000000>;
|
||||
+ };
|
||||
+
|
||||
+ reserved-memory {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges;
|
||||
+
|
||||
+ /* Not needed since u-boot 2020.07
|
||||
+ trust_reserved: trust@68400000 {
|
||||
+ reg = <0x68400000 0xe00000>;
|
||||
+ no-map;
|
||||
+ };*/
|
||||
+ };
|
||||
+
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_enable_h>;
|
||||
+ reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&cpu_alert1 {
|
||||
+ temperature = <105000>;
|
||||
+};
|
||||
+
|
||||
+&cpu_crit {
|
||||
+ temperature = <115000>;
|
||||
+};
|
||||
+
|
||||
+&cpu_thermal {
|
||||
+ cooling-maps {
|
||||
+ /delete-node/ map0;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0_opp_table {
|
||||
+
|
||||
+ opp-408000000 {
|
||||
+ opp-microvolt = <950000 950000 1275000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-600000000 {
|
||||
+ opp-microvolt = <975000 975000 1275000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-816000000 {
|
||||
+ opp-microvolt = <1000000 1000000 1275000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-1008000000 {
|
||||
+ opp-microvolt = <1175000 1175000 1275000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-1200000000 {
|
||||
+ opp-microvolt = <1275000 1275000 1275000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cru {
|
||||
+ assigned-clocks =
|
||||
+ <&cru PLL_GPLL>, <&cru ARMCLK>,
|
||||
+ <&cru PLL_CPLL>, <&cru ACLK_PERI>,
|
||||
+ <&cru HCLK_PERI>, <&cru PCLK_PERI>,
|
||||
+ <&cru ACLK_CPU>, <&cru HCLK_CPU>,
|
||||
+ <&cru PCLK_CPU>, <&cru ACLK_VOP>;
|
||||
+ assigned-clock-rates =
|
||||
+ <1200000000>, <816000000>,
|
||||
+ <500000000>, <150000000>,
|
||||
+ <150000000>, <75000000>,
|
||||
+ <150000000>, <150000000>,
|
||||
+ <75000000>, <400000000>;
|
||||
+};
|
||||
+
|
||||
+&emmc {
|
||||
+ cap-mmc-highspeed;
|
||||
+ keep-power-in-suspend;
|
||||
+ non-removable;
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ assigned-clocks = <&cru SCLK_MAC_SRC>;
|
||||
+ assigned-clock-rates = <50000000>;
|
||||
+ clock_in_out = "output";
|
||||
+ phy-handle = <&phy>;
|
||||
+ phy-mode = "rmii";
|
||||
+ status = "okay";
|
||||
+
|
||||
+ mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ phy: phy@0 {
|
||||
+ compatible = "ethernet-phy-id1234.d400",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+ clocks = <&cru SCLK_MAC_PHY>;
|
||||
+ phy-is-integrated;
|
||||
+ resets = <&cru SRST_MACPHY>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ assigned-clocks = <&cru ACLK_GPU>;
|
||||
+ assigned-clock-rates = <300000000>;
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_sound {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+
|
||||
+ ir {
|
||||
+ ir_int: ir-int {
|
||||
+ rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ keys {
|
||||
+ pwr_key: pwr-key {
|
||||
+ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pwm1 {
|
||||
+ pwm1_pin_pull_down: pwm1-pin-pull-down {
|
||||
+ rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pwm2 {
|
||||
+ pwm2_pin_pull_up: pwm2-pin-pull-up {
|
||||
+ rockchip,pins = <1 RK_PB4 2 &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio-pwrseq {
|
||||
+ wifi_enable_h: wifi-enable-h {
|
||||
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ host_vbus_drv: host-vbus-drv {
|
||||
+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ otg_vbus_drv: otg-vbus-drv {
|
||||
+ rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&sdio {
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-sdio-irq;
|
||||
+ keep-power-in-suspend;
|
||||
+ non-removable;
|
||||
+ no-sd;
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ cap-sd-highspeed;
|
||||
+ keep-power-in-suspend;
|
||||
+ no-sdio;
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ rockchip,hw-tshut-mode = <0>;
|
||||
+ rockchip,hw-tshut-polarity = <1>;
|
||||
+ rockchip,hw-tshut-temp = <120000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart11_xfer &uart11_rts &uart11_cts>;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host2_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host2_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP>;
|
||||
+ assigned-clock-parents = <&cru SCLK_HDMI_PHY>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&wdt {
|
||||
+ status = "okay";
|
||||
+};
|
||||
|
|
@ -1,91 +1,92 @@
|
|||
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
|
||||
index b2fcf0e75..25051c03f 100644
|
||||
index be46697e1..b2a0246fb 100644
|
||||
--- a/arch/arm/boot/dts/rk322x.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk322x.dtsi
|
||||
@@ -1149,51 +1149,71 @@
|
||||
@@ -843,6 +843,22 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
flash_cs0: flash-cs0 {
|
||||
rockchip,pins =
|
||||
- <2 RK_PA6 1 &pcfg_pull_none>;
|
||||
+ <2 RK_PA6 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
flash_cs1: flash-cs1 {
|
||||
rockchip,pins =
|
||||
- <0 RK_PC7 1 &pcfg_pull_none>;
|
||||
+ <0 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+ nfc: nand-controller@ff4b0000 {
|
||||
+ compatible = "rockchip,rk3228_nfc";
|
||||
+ reg = <0x30030000 0x4000>;
|
||||
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
|
||||
+ clock-names = "nfc", "ahb";
|
||||
+ assigned-clocks = <&cru SCLK_NANDC>;
|
||||
+ assigned-clock-rates = <150000000>;
|
||||
+
|
||||
+ flash_cs2: flash-cs2 {
|
||||
+ rockchip,pins =
|
||||
+ <1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&flash_cs0 &flash_rdy &flash_ale &flash_cle
|
||||
+ &flash_wrn &flash_rdn &flash_bus8>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ flash_cs3: flash-cs3 {
|
||||
+ rockchip,pins =
|
||||
+ <1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
flash_rdy: flash-rdy {
|
||||
rockchip,pins =
|
||||
- <2 RK_PA4 1 &pcfg_pull_none>;
|
||||
+ <2 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
flash_ale: flash-ale {
|
||||
rockchip,pins =
|
||||
- <2 RK_PA0 1 &pcfg_pull_none>;
|
||||
+ <2 RK_PA0 RK_FUNC_1 &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
flash_cle: flash-cle {
|
||||
rockchip,pins =
|
||||
- <2 RK_PA1 1 &pcfg_pull_none>;
|
||||
+ <2 RK_PA1 RK_FUNC_1 &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
flash_wrn: flash-wrn {
|
||||
- rockchip,pins =
|
||||
- <2 RK_PA2 1 &pcfg_pull_none>;
|
||||
+ rockchip,pins =
|
||||
+ <2 RK_PA2 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
flash_rdn: flash-rdn {
|
||||
rockchip,pins =
|
||||
- <2 RK_PA3 1 &pcfg_pull_none>;
|
||||
+ <2 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
flash_bus8: flash-bus8 {
|
||||
- rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
|
||||
- <1 RK_PD1 1 &pcfg_pull_none>,
|
||||
- <1 RK_PD2 1 &pcfg_pull_none>,
|
||||
- <1 RK_PD3 1 &pcfg_pull_none>,
|
||||
- <1 RK_PD4 1 &pcfg_pull_none>,
|
||||
- <1 RK_PD5 1 &pcfg_pull_none>,
|
||||
- <1 RK_PD6 1 &pcfg_pull_none>,
|
||||
- <1 RK_PD7 1 &pcfg_pull_none>;
|
||||
+ rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD4 RK_FUNC_1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD5 RK_FUNC_1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD6 RK_FUNC_1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD7 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
+
|
||||
+ flash_dqs: flash-dqs {
|
||||
+ rockchip,pins = <2 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_wp: flash-wp {
|
||||
+ rockchip,pins = <2 RK_PA5 RK_FUNC_1 &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb_otg: usb@30040000 {
|
||||
compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
|
||||
"snps,dwc2";
|
||||
@@ -1105,6 +1121,65 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ flash {
|
||||
+
|
||||
+ flash_cs0: flash-cs0 {
|
||||
+ rockchip,pins = <2 RK_PA6 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_cs1: flash-cs1 {
|
||||
+ rockchip,pins = <0 RK_PC7 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_cs2: flash-cs2 {
|
||||
+ rockchip,pins = <1 RK_PC6 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_cs3: flash-cs3 {
|
||||
+ rockchip,pins = <1 RK_PC7 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_rdy: flash-rdy {
|
||||
+ rockchip,pins = <2 RK_PA4 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_ale: flash-ale {
|
||||
+ rockchip,pins = <2 RK_PA0 1 &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ flash_cle: flash-cle {
|
||||
+ rockchip,pins = <2 RK_PA1 1 &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ flash_wrn: flash-wrn {
|
||||
+ rockchip,pins = <2 RK_PA2 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_rdn: flash-rdn {
|
||||
+ rockchip,pins = <2 RK_PA3 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_bus8: flash-bus8 {
|
||||
+ rockchip,pins = <1 RK_PD0 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD1 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD2 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD3 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD4 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD5 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD6 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD7 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_dqs: flash-dqs {
|
||||
+ rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_wp: flash-wp {
|
||||
+ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+
|
||||
gmac {
|
||||
rgmii_pins: rgmii-pins {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,66 @@
|
|||
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
index 73d24c6bbf05..d4ac6e161ef2 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
@@ -614,6 +614,44 @@ static const struct vop_common rk3288_common = {
|
||||
.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
|
||||
};
|
||||
|
||||
+static const struct vop_win_phy rk3228_win0_data = {
|
||||
+ .scl = &rk3288_win_full_scl,
|
||||
+ .data_formats = formats_win_full,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_full),
|
||||
+ .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
+ .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
+ .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
+ .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
+ .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
|
||||
+ .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
|
||||
+ .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
|
||||
+ .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
|
||||
+ .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
|
||||
+ .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
|
||||
+ .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
|
||||
+ .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
|
||||
+};
|
||||
+
|
||||
+static const struct vop_win_phy rk3228_win1_data = {
|
||||
+ .scl = &rk3288_win_full_scl,
|
||||
+ .data_formats = formats_win_lite,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_lite),
|
||||
+ .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
+ .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
+ .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
+ .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
+ .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
|
||||
+ .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
|
||||
+ .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
|
||||
+ .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
|
||||
+ .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
|
||||
+ .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
|
||||
+ .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
|
||||
+ .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
|
||||
+};
|
||||
+
|
||||
/*
|
||||
* Note: rk3288 has a dedicated 'cursor' window, however, that window requires
|
||||
* special support to get alpha blending working. For now, just use overlay
|
||||
@@ -864,10 +902,10 @@ static const struct vop_data rk3399_vop_lit = {
|
||||
};
|
||||
|
||||
static const struct vop_win_data rk3228_vop_win_data[] = {
|
||||
- { .base = 0x00, .phy = &rk3288_win01_data,
|
||||
+ { .base = 0x00, .phy = &rk3228_win0_data,
|
||||
.type = DRM_PLANE_TYPE_PRIMARY },
|
||||
- { .base = 0x40, .phy = &rk3288_win01_data,
|
||||
- .type = DRM_PLANE_TYPE_CURSOR },
|
||||
+ { .base = 0x40, .phy = &rk3228_win1_data,
|
||||
+ .type = DRM_PLANE_TYPE_OVERLAY },
|
||||
};
|
||||
|
||||
static const struct vop_data rk3228_vop = {
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
|
@ -3,7 +3,7 @@ new file mode 100644
|
|||
index 000000000..24590f864
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk322x-box.dts
|
||||
@@ -0,0 +1,239 @@
|
||||
@@ -0,0 +1,235 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
|
|
@ -53,10 +53,6 @@ index 000000000..24590f864
|
|||
+ rockchip,default-sample-phase = <180>;
|
||||
+};
|
||||
+
|
||||
+&nfc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ tx_delay = <0x26>;
|
||||
+ rx_delay = <0x11>;
|
||||
|
|
@ -141,18 +137,18 @@ index 000000000..24590f864
|
|||
+ */
|
||||
+ sdmmc {
|
||||
+ sdmmc_clk: sdmmc-clk {
|
||||
+ rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_down>;
|
||||
+ rockchip,pins = <1 16 1 &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ sdmmc_cmd: sdmmc-cmd {
|
||||
+ rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_up>;
|
||||
+ rockchip,pins = <1 15 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ sdmmc_bus4: sdmmc-bus4 {
|
||||
+ rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_up>,
|
||||
+ <1 19 RK_FUNC_1 &pcfg_pull_up>,
|
||||
+ <1 20 RK_FUNC_1 &pcfg_pull_up>,
|
||||
+ <1 21 RK_FUNC_1 &pcfg_pull_up>;
|
||||
+ rockchip,pins = <1 18 1 &pcfg_pull_up>,
|
||||
+ <1 19 1 &pcfg_pull_up>,
|
||||
+ <1 20 1 &pcfg_pull_up>,
|
||||
+ <1 21 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
|
|
@ -162,18 +158,18 @@ index 000000000..24590f864
|
|||
+ */
|
||||
+ sdio {
|
||||
+ sdio_clk: sdio-clk {
|
||||
+ rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_down_2ma>;
|
||||
+ rockchip,pins = <3 0 1 &pcfg_pull_down_2ma>;
|
||||
+ };
|
||||
+
|
||||
+ sdio_cmd: sdio-cmd {
|
||||
+ rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_up_2ma>;
|
||||
+ rockchip,pins = <3 1 1 &pcfg_pull_up_2ma>;
|
||||
+ };
|
||||
+
|
||||
+ sdio_bus4: sdio-bus4 {
|
||||
+ rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up_2ma>,
|
||||
+ <3 3 RK_FUNC_1 &pcfg_pull_up_2ma>,
|
||||
+ <3 4 RK_FUNC_1 &pcfg_pull_up_2ma>,
|
||||
+ <3 5 RK_FUNC_1 &pcfg_pull_up_2ma>;
|
||||
+ rockchip,pins = <3 2 1 &pcfg_pull_up_2ma>,
|
||||
+ <3 3 1 &pcfg_pull_up_2ma>,
|
||||
+ <3 4 1 &pcfg_pull_up_2ma>,
|
||||
+ <3 5 1 &pcfg_pull_up_2ma>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
|
|
@ -183,30 +179,30 @@ index 000000000..24590f864
|
|||
+ */
|
||||
+ emmc {
|
||||
+ emmc_clk: emmc-clk {
|
||||
+ rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_up>;
|
||||
+ rockchip,pins = <2 7 2 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ emmc_cmd: emmc-cmd {
|
||||
+ rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_up>;
|
||||
+ rockchip,pins = <1 22 2 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ emmc_bus8: emmc-bus8 {
|
||||
+ rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_up>,
|
||||
+ <1 25 RK_FUNC_2 &pcfg_pull_up>,
|
||||
+ <1 26 RK_FUNC_2 &pcfg_pull_up>,
|
||||
+ <1 27 RK_FUNC_2 &pcfg_pull_up>,
|
||||
+ <1 28 RK_FUNC_2 &pcfg_pull_up>,
|
||||
+ <1 29 RK_FUNC_2 &pcfg_pull_up>,
|
||||
+ <1 30 RK_FUNC_2 &pcfg_pull_up>,
|
||||
+ <1 31 RK_FUNC_2 &pcfg_pull_up>;
|
||||
+ rockchip,pins = <1 24 2 &pcfg_pull_up>,
|
||||
+ <1 25 2 &pcfg_pull_up>,
|
||||
+ <1 26 2 &pcfg_pull_up>,
|
||||
+ <1 27 2 &pcfg_pull_up>,
|
||||
+ <1 28 2 &pcfg_pull_up>,
|
||||
+ <1 29 2 &pcfg_pull_up>,
|
||||
+ <1 30 2 &pcfg_pull_up>,
|
||||
+ <1 31 2 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ emmc_pwr: emmc-pwr {
|
||||
+ rockchip,pins = <2 RK_PA5 RK_FUNC_2 &pcfg_pull_down>;
|
||||
+ rockchip,pins = <2 RK_PA5 2 &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ emmc_rst: emmc-rst {
|
||||
+ rockchip,pins = <1 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
|
||||
+ rockchip,pins = <1 RK_PC7 2 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
|
|
|
|||
|
|
@ -0,0 +1,248 @@
|
|||
diff --git a/drivers/net/wireless/rtl8189es/include/rtw_security.h b/drivers/net/wireless/rtl8189es/include/rtw_security.h
|
||||
index 5820a55..3e8e428 100644
|
||||
--- a/drivers/net/wireless/rtl8189es/include/rtw_security.h
|
||||
+++ b/drivers/net/wireless/rtl8189es/include/rtw_security.h
|
||||
@@ -238,7 +238,7 @@ struct security_priv
|
||||
#endif /* DBG_SW_SEC_CNT */
|
||||
};
|
||||
|
||||
-struct sha256_state {
|
||||
+struct rtl_sha256_state {
|
||||
u64 length;
|
||||
u32 state[8], curlen;
|
||||
u8 buf[64];
|
||||
diff --git a/drivers/net/wireless/rtl8189es/core/rtw_security.c b/drivers/net/wireless/rtl8189es/core/rtw_security.c
|
||||
index 8dac771..9b3a1f9 100644
|
||||
--- a/drivers/net/wireless/rtl8189es/core/rtw_security.c
|
||||
+++ b/drivers/net/wireless/rtl8189es/core/rtw_security.c
|
||||
@@ -2281,7 +2281,7 @@ BIP_exit:
|
||||
|
||||
#ifndef PLATFORM_FREEBSD
|
||||
/* compress 512-bits */
|
||||
-static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
+static int sha256_compress(struct rtl_sha256_state *md, unsigned char *buf)
|
||||
{
|
||||
u32 S[8], W[64], t0, t1;
|
||||
u32 t;
|
||||
@@ -2323,7 +2323,7 @@ static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
}
|
||||
|
||||
/* Initialize the hash state */
|
||||
-static void sha256_init(struct sha256_state *md)
|
||||
+static void sha256_init(struct rtl_sha256_state *md)
|
||||
{
|
||||
md->curlen = 0;
|
||||
md->length = 0;
|
||||
@@ -2344,7 +2344,7 @@ static void sha256_init(struct sha256_state *md)
|
||||
@param inlen The length of the data (octets)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
+static int sha256_process(struct rtl_sha256_state *md, unsigned char *in,
|
||||
unsigned long inlen)
|
||||
{
|
||||
unsigned long n;
|
||||
@@ -2385,7 +2385,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
@param out [out] The destination of the hash (32 bytes)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
+static int sha256_done(struct rtl_sha256_state *md, unsigned char *out)
|
||||
{
|
||||
int i;
|
||||
|
||||
@@ -2437,7 +2437,7 @@ static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,
|
||||
u8 *mac)
|
||||
{
|
||||
- struct sha256_state ctx;
|
||||
+ struct rtl_sha256_state ctx;
|
||||
size_t i;
|
||||
|
||||
sha256_init(&ctx);
|
||||
diff --git a/drivers/net/wireless/rtl8811cu/include/rtw_security.h b/drivers/net/wireless/rtl8811cu/include/rtw_security.h
|
||||
index ac8432e..5f74fb7 100755
|
||||
--- a/drivers/net/wireless/rtl8811cu/include/rtw_security.h
|
||||
+++ b/drivers/net/wireless/rtl8811cu/include/rtw_security.h
|
||||
@@ -249,7 +249,7 @@ struct security_priv {
|
||||
#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE
|
||||
#endif
|
||||
|
||||
-struct sha256_state {
|
||||
+struct rtl_sha256_state {
|
||||
u64 length;
|
||||
u32 state[8], curlen;
|
||||
u8 buf[64];
|
||||
diff --git a/drivers/net/wireless/rtl8811cu/core/rtw_security.c b/drivers/net/wireless/rtl8811cu/core/rtw_security.c
|
||||
index b537a26..f8c42f4 100755
|
||||
--- a/drivers/net/wireless/rtl8811cu/core/rtw_security.c
|
||||
+++ b/drivers/net/wireless/rtl8811cu/core/rtw_security.c
|
||||
@@ -2133,7 +2133,7 @@ BIP_exit:
|
||||
#ifndef PLATFORM_FREEBSD
|
||||
#if defined(CONFIG_TDLS)
|
||||
/* compress 512-bits */
|
||||
-static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
+static int sha256_compress(struct rtl_sha256_state *md, unsigned char *buf)
|
||||
{
|
||||
u32 S[8], W[64], t0, t1;
|
||||
u32 t;
|
||||
@@ -2181,7 +2181,7 @@ static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
}
|
||||
|
||||
/* Initialize the hash state */
|
||||
-static void sha256_init(struct sha256_state *md)
|
||||
+static void sha256_init(struct rtl_sha256_state *md)
|
||||
{
|
||||
md->curlen = 0;
|
||||
md->length = 0;
|
||||
@@ -2202,7 +2202,7 @@ static void sha256_init(struct sha256_state *md)
|
||||
@param inlen The length of the data (octets)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
+static int sha256_process(struct rtl_sha256_state *md, unsigned char *in,
|
||||
unsigned long inlen)
|
||||
{
|
||||
unsigned long n;
|
||||
@@ -2243,7 +2243,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
@param out [out] The destination of the hash (32 bytes)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
+static int sha256_done(struct rtl_sha256_state *md, unsigned char *out)
|
||||
{
|
||||
int i;
|
||||
|
||||
@@ -2293,7 +2293,7 @@ static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,
|
||||
u8 *mac)
|
||||
{
|
||||
- struct sha256_state ctx;
|
||||
+ struct rtl_sha256_state ctx;
|
||||
size_t i;
|
||||
|
||||
sha256_init(&ctx);
|
||||
diff --git a/drivers/net/wireless/rtl8188eu/include/rtw_security.h b/drivers/net/wireless/rtl8188eu/include/rtw_security.h
|
||||
index 0adc700..2a9cf9d 100644
|
||||
--- a/drivers/net/wireless/rtl8188eu/include/rtw_security.h
|
||||
+++ b/drivers/net/wireless/rtl8188eu/include/rtw_security.h
|
||||
@@ -249,7 +249,7 @@ struct security_priv {
|
||||
#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE
|
||||
#endif
|
||||
|
||||
-struct sha256_state {
|
||||
+struct rtl_sha256_state {
|
||||
u64 length;
|
||||
u32 state[8], curlen;
|
||||
u8 buf[64];
|
||||
diff --git a/drivers/net/wireless/rtl8188eu/core/rtw_security.c b/drivers/net/wireless/rtl8188eu/core/rtw_security.c
|
||||
index 5807521..0b3eed2 100644
|
||||
--- a/drivers/net/wireless/rtl8188eu/core/rtw_security.c
|
||||
+++ b/drivers/net/wireless/rtl8188eu/core/rtw_security.c
|
||||
@@ -2133,7 +2133,7 @@ BIP_exit:
|
||||
#ifndef PLATFORM_FREEBSD
|
||||
#if defined(CONFIG_TDLS)
|
||||
/* compress 512-bits */
|
||||
-static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
+static int sha256_compress(struct rtl_sha256_state *md, unsigned char *buf)
|
||||
{
|
||||
u32 S[8], W[64], t0, t1;
|
||||
u32 t;
|
||||
@@ -2181,7 +2181,7 @@ static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
}
|
||||
|
||||
/* Initialize the hash state */
|
||||
-static void sha256_init(struct sha256_state *md)
|
||||
+static void sha256_init(struct rtl_sha256_state *md)
|
||||
{
|
||||
md->curlen = 0;
|
||||
md->length = 0;
|
||||
@@ -2202,7 +2202,7 @@ static void sha256_init(struct sha256_state *md)
|
||||
@param inlen The length of the data (octets)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
+static int sha256_process(struct rtl_sha256_state *md, unsigned char *in,
|
||||
unsigned long inlen)
|
||||
{
|
||||
unsigned long n;
|
||||
@@ -2243,7 +2243,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
@param out [out] The destination of the hash (32 bytes)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
+static int sha256_done(struct rtl_sha256_state *md, unsigned char *out)
|
||||
{
|
||||
int i;
|
||||
|
||||
@@ -2293,7 +2293,7 @@ static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,
|
||||
u8 *mac)
|
||||
{
|
||||
- struct sha256_state ctx;
|
||||
+ struct rtl_sha256_state ctx;
|
||||
size_t i;
|
||||
|
||||
sha256_init(&ctx);
|
||||
diff --git a/drivers/net/wireless/rtl88x2bu/include/rtw_security.h b/drivers/net/wireless/rtl88x2bu/include/rtw_security.h
|
||||
index ac8432e..5f74fb7 100644
|
||||
--- a/drivers/net/wireless/rtl88x2bu/include/rtw_security.h
|
||||
+++ b/drivers/net/wireless/rtl88x2bu/include/rtw_security.h
|
||||
@@ -249,7 +249,7 @@ struct security_priv {
|
||||
#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE
|
||||
#endif
|
||||
|
||||
-struct sha256_state {
|
||||
+struct rtl_sha256_state {
|
||||
u64 length;
|
||||
u32 state[8], curlen;
|
||||
u8 buf[64];
|
||||
diff --git a/drivers/net/wireless/rtl88x2bu/core/rtw_security.c b/drivers/net/wireless/rtl88x2bu/core/rtw_security.c
|
||||
index b537a26..f8c42f4 100644
|
||||
--- a/drivers/net/wireless/rtl88x2bu/core/rtw_security.c
|
||||
+++ b/drivers/net/wireless/rtl88x2bu/core/rtw_security.c
|
||||
@@ -2133,7 +2133,7 @@ BIP_exit:
|
||||
#ifndef PLATFORM_FREEBSD
|
||||
#if defined(CONFIG_TDLS)
|
||||
/* compress 512-bits */
|
||||
-static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
+static int sha256_compress(struct rtl_sha256_state *md, unsigned char *buf)
|
||||
{
|
||||
u32 S[8], W[64], t0, t1;
|
||||
u32 t;
|
||||
@@ -2181,7 +2181,7 @@ static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
}
|
||||
|
||||
/* Initialize the hash state */
|
||||
-static void sha256_init(struct sha256_state *md)
|
||||
+static void sha256_init(struct rtl_sha256_state *md)
|
||||
{
|
||||
md->curlen = 0;
|
||||
md->length = 0;
|
||||
@@ -2202,7 +2202,7 @@ static void sha256_init(struct sha256_state *md)
|
||||
@param inlen The length of the data (octets)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
+static int sha256_process(struct rtl_sha256_state *md, unsigned char *in,
|
||||
unsigned long inlen)
|
||||
{
|
||||
unsigned long n;
|
||||
@@ -2243,7 +2243,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
@param out [out] The destination of the hash (32 bytes)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
+static int sha256_done(struct rtl_sha256_state *md, unsigned char *out)
|
||||
{
|
||||
int i;
|
||||
|
||||
@@ -2293,7 +2293,7 @@ static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,
|
||||
u8 *mac)
|
||||
{
|
||||
- struct sha256_state ctx;
|
||||
+ struct rtl_sha256_state ctx;
|
||||
size_t i;
|
||||
|
||||
sha256_init(&ctx);
|
||||
236
patch/kernel/rk322x-current/wifi-4004-fix-cfg80211-for-5.8.patch
Normal file
236
patch/kernel/rk322x-current/wifi-4004-fix-cfg80211-for-5.8.patch
Normal file
|
|
@ -0,0 +1,236 @@
|
|||
diff --git a/drivers/net/wireless/rtl8189es/os_dep/linux/ioctl_cfg80211.c b/drivers/net/wireless/rtl8189es/os_dep/linux/ioctl_cfg80211.c
|
||||
index d77cc17..32cc240 100644
|
||||
--- a/drivers/net/wireless/rtl8189es/os_dep/linux/ioctl_cfg80211.c
|
||||
+++ b/drivers/net/wireless/rtl8189es/os_dep/linux/ioctl_cfg80211.c
|
||||
@@ -5567,6 +5567,33 @@ exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))
|
||||
+
|
||||
+static void
|
||||
+cfg80211_rtw_update_mgmt_frame_registrations(struct wiphy *wiphy,
|
||||
+ struct wireless_dev *wdev,
|
||||
+ struct mgmt_frame_regs *upd)
|
||||
+{
|
||||
+ struct net_device *ndev = wdev_to_ndev(wdev);
|
||||
+ struct rtw_wdev_priv *pwdev_priv;
|
||||
+ _adapter *adapter;
|
||||
+
|
||||
+ if (ndev == NULL)
|
||||
+ return;
|
||||
+
|
||||
+ adapter = (_adapter *)rtw_netdev_priv(ndev);
|
||||
+ pwdev_priv = adapter_wdev_data(adapter);
|
||||
+
|
||||
+#ifdef CONFIG_DEBUG_CFG80211
|
||||
+ RTW_INFO(FUNC_ADPT_FMT" stypes:%x\n", FUNC_ADPT_ARG(adapter),
|
||||
+ upd->interface_stypes);
|
||||
+#endif
|
||||
+
|
||||
+ /* not implemented, see bellow */
|
||||
+}
|
||||
+
|
||||
+#else
|
||||
+
|
||||
static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy,
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
|
||||
struct wireless_dev *wdev,
|
||||
@@ -5611,6 +5638,8 @@ exit:
|
||||
return;
|
||||
}
|
||||
|
||||
+#endif
|
||||
+
|
||||
#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
|
||||
static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy,
|
||||
struct net_device *ndev,
|
||||
@@ -6505,7 +6534,11 @@ static struct cfg80211_ops rtw_cfg80211_ops = {
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
|
||||
.mgmt_tx = cfg80211_rtw_mgmt_tx,
|
||||
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))
|
||||
+ .update_mgmt_frame_registrations = cfg80211_rtw_update_mgmt_frame_registrations,
|
||||
+#else
|
||||
.mgmt_frame_register = cfg80211_rtw_mgmt_frame_register,
|
||||
+#endif
|
||||
#elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,34) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,35))
|
||||
.action = cfg80211_rtw_mgmt_tx,
|
||||
#endif
|
||||
diff --git a/drivers/net/wireless/rtl8811cu/os_dep/linux/ioctl_cfg80211.c b/drivers/net/wireless/rtl8811cu/os_dep/linux/ioctl_cfg80211.c
|
||||
index c0df148..9bff924 100755
|
||||
--- a/drivers/net/wireless/rtl8811cu/os_dep/linux/ioctl_cfg80211.c
|
||||
+++ b/drivers/net/wireless/rtl8811cu/os_dep/linux/ioctl_cfg80211.c
|
||||
@@ -7143,6 +7143,33 @@ exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))
|
||||
+
|
||||
+static void
|
||||
+cfg80211_rtw_update_mgmt_frame_registrations(struct wiphy *wiphy,
|
||||
+ struct wireless_dev *wdev,
|
||||
+ struct mgmt_frame_regs *upd)
|
||||
+{
|
||||
+ struct net_device *ndev = wdev_to_ndev(wdev);
|
||||
+ struct rtw_wdev_priv *pwdev_priv;
|
||||
+ _adapter *adapter;
|
||||
+
|
||||
+ if (ndev == NULL)
|
||||
+ return;
|
||||
+
|
||||
+ adapter = (_adapter *)rtw_netdev_priv(ndev);
|
||||
+ pwdev_priv = adapter_wdev_data(adapter);
|
||||
+
|
||||
+#ifdef CONFIG_DEBUG_CFG80211
|
||||
+ RTW_INFO(FUNC_ADPT_FMT" stypes:%x\n", FUNC_ADPT_ARG(adapter),
|
||||
+ upd->interface_stypes);
|
||||
+#endif
|
||||
+
|
||||
+ /* not implemented, see bellow */
|
||||
+}
|
||||
+
|
||||
+#else
|
||||
+
|
||||
static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy,
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
|
||||
struct wireless_dev *wdev,
|
||||
@@ -7187,6 +7214,8 @@ exit:
|
||||
return;
|
||||
}
|
||||
|
||||
+#endif
|
||||
+
|
||||
#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
|
||||
static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy,
|
||||
struct net_device *ndev,
|
||||
@@ -9457,7 +9486,11 @@ static struct cfg80211_ops rtw_cfg80211_ops = {
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
|
||||
.mgmt_tx = cfg80211_rtw_mgmt_tx,
|
||||
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))
|
||||
+ .update_mgmt_frame_registrations = cfg80211_rtw_update_mgmt_frame_registrations,
|
||||
+#else
|
||||
.mgmt_frame_register = cfg80211_rtw_mgmt_frame_register,
|
||||
+#endif
|
||||
#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
|
||||
.action = cfg80211_rtw_mgmt_tx,
|
||||
#endif
|
||||
diff --git a/drivers/net/wireless/rtl8188eu/os_dep/linux/ioctl_cfg80211.c b/drivers/net/wireless/rtl8188eu/os_dep/linux/ioctl_cfg80211.c
|
||||
index 721723e..62fd530 100644
|
||||
--- a/drivers/net/wireless/rtl8188eu/os_dep/linux/ioctl_cfg80211.c
|
||||
+++ b/drivers/net/wireless/rtl8188eu/os_dep/linux/ioctl_cfg80211.c
|
||||
@@ -7470,6 +7470,33 @@ exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))
|
||||
+
|
||||
+static void
|
||||
+cfg80211_rtw_update_mgmt_frame_registrations(struct wiphy *wiphy,
|
||||
+ struct wireless_dev *wdev,
|
||||
+ struct mgmt_frame_regs *upd)
|
||||
+{
|
||||
+ struct net_device *ndev = wdev_to_ndev(wdev);
|
||||
+ struct rtw_wdev_priv *pwdev_priv;
|
||||
+ _adapter *adapter;
|
||||
+
|
||||
+ if (ndev == NULL)
|
||||
+ return;
|
||||
+
|
||||
+ adapter = (_adapter *)rtw_netdev_priv(ndev);
|
||||
+ pwdev_priv = adapter_wdev_data(adapter);
|
||||
+
|
||||
+#ifdef CONFIG_DEBUG_CFG80211
|
||||
+ RTW_INFO(FUNC_ADPT_FMT" stypes:%x\n", FUNC_ADPT_ARG(adapter),
|
||||
+ upd->interface_stypes);
|
||||
+#endif
|
||||
+
|
||||
+ /* not implemented, see bellow */
|
||||
+}
|
||||
+
|
||||
+#else
|
||||
+
|
||||
static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy,
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
|
||||
struct wireless_dev *wdev,
|
||||
@@ -7525,6 +7552,8 @@ exit:
|
||||
return;
|
||||
}
|
||||
|
||||
+#endif
|
||||
+
|
||||
#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
|
||||
static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy,
|
||||
struct net_device *ndev,
|
||||
@@ -9903,7 +9932,11 @@ static struct cfg80211_ops rtw_cfg80211_ops = {
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
|
||||
.mgmt_tx = cfg80211_rtw_mgmt_tx,
|
||||
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))
|
||||
+ .update_mgmt_frame_registrations = cfg80211_rtw_update_mgmt_frame_registrations,
|
||||
+#else
|
||||
.mgmt_frame_register = cfg80211_rtw_mgmt_frame_register,
|
||||
+#endif
|
||||
#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
|
||||
.action = cfg80211_rtw_mgmt_tx,
|
||||
#endif
|
||||
diff --git a/drivers/net/wireless/rtl88x2bu/os_dep/linux/ioctl_cfg80211.c b/drivers/net/wireless/rtl88x2bu/os_dep/linux/ioctl_cfg80211.c
|
||||
index 2fd4e28..b463e55 100755
|
||||
--- a/drivers/net/wireless/rtl88x2bu/os_dep/linux/ioctl_cfg80211.c
|
||||
+++ b/drivers/net/wireless/rtl88x2bu/os_dep/linux/ioctl_cfg80211.c
|
||||
@@ -7325,6 +7325,33 @@ exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))
|
||||
+
|
||||
+static void
|
||||
+cfg80211_rtw_update_mgmt_frame_registrations(struct wiphy *wiphy,
|
||||
+ struct wireless_dev *wdev,
|
||||
+ struct mgmt_frame_regs *upd)
|
||||
+{
|
||||
+ struct net_device *ndev = wdev_to_ndev(wdev);
|
||||
+ struct rtw_wdev_priv *pwdev_priv;
|
||||
+ _adapter *adapter;
|
||||
+
|
||||
+ if (ndev == NULL)
|
||||
+ return;
|
||||
+
|
||||
+ adapter = (_adapter *)rtw_netdev_priv(ndev);
|
||||
+ pwdev_priv = adapter_wdev_data(adapter);
|
||||
+
|
||||
+#ifdef CONFIG_DEBUG_CFG80211
|
||||
+ RTW_INFO(FUNC_ADPT_FMT" stypes:%x\n", FUNC_ADPT_ARG(adapter),
|
||||
+ upd->interface_stypes);
|
||||
+#endif
|
||||
+
|
||||
+ /* not implemented, see bellow */
|
||||
+}
|
||||
+
|
||||
+#else
|
||||
+
|
||||
static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy,
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
|
||||
struct wireless_dev *wdev,
|
||||
@@ -7369,6 +7396,8 @@ exit:
|
||||
return;
|
||||
}
|
||||
|
||||
+#endif
|
||||
+
|
||||
#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
|
||||
static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy,
|
||||
struct net_device *ndev,
|
||||
@@ -9652,7 +9681,11 @@ static struct cfg80211_ops rtw_cfg80211_ops = {
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
|
||||
.mgmt_tx = cfg80211_rtw_mgmt_tx,
|
||||
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))
|
||||
+ .update_mgmt_frame_registrations = cfg80211_rtw_update_mgmt_frame_registrations,
|
||||
+#else
|
||||
.mgmt_frame_register = cfg80211_rtw_mgmt_frame_register,
|
||||
+#endif
|
||||
#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
|
||||
.action = cfg80211_rtw_mgmt_tx,
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue