Add Helios64 support (#2126)

* Add initial Helios64 configuration

Add ethernet udev rules
Added disable auto power on script during shutdown
Configure ALSA to output audio to (DisplayPort) USB type-C

armbian-firstrun: exclude helios64 from generating fixed_mac

Each network interface on Helios64 already assigned to unique MAC
address in factory. Assigning Network Manager with cloned MAC is not
needed.

Signed-off-by: Aditya Prayoga <aditya@kobol.io>

* u-boot: rk3399: Add Helios64

Use rockchip propriettary loader

* kernel: rk3399-legacy: Update r8152 to support 2.5GbE USB RTL8156

Required for Helios64

* kernel: rk3399-legacy: update Rockchip PCIe driver

Port changes by ayufan on rockchip64.

* kernel: rk3399-legacy: Add support for Helios64

Add Helios64 device tree.
Enable missing driver/kernel module.
Auto load lm75 modules

Signed-off-by: Aditya Prayoga <aditya@kobol.io>

* kernel: rk3399-legacy: rework roc-rk3399-pc patch

the patch broken due to additional line added by helios64 on
arch/arm64/boot/dts/rockchip/Makefile

Signed-off-by: Aditya Prayoga <aditya@kobol.io>

* kernel: rk3399-legacy: update Rockchip PCIe driver

Backport bugfix from mainline
refer to
https://patchwork.kernel.org/patch/11561979/
and
https://patchwork.kernel.org/patch/11561977/

Signed-off-by: Aditya Prayoga <aditya@kobol.io>

* kernel: rockchip64-current: Add support for Helios64

Add Helios64 device tree.
Enable missing driver/kernel module.

* config: helios64: use mainline ATF on current branch

and u-boot TPL/SPL instead of Rockchip proprietary loader

* helios64: u-boot v2020.07 update

* Add Helios64 target

* kernel: rk3399-legacy: update Rockchip PCIe driver

Removed unrelated changes from porting ayufan fixes

Signed-off-by: Piotr Szczepanik <piter75@gmail.com>

* helios64: make use of PACKAGE_LIST* variables

Co-authored-by: Piotr Szczepanik <piter75@gmail.com>

config/boards/helios64.wip

@@ -0,0 +1,9 @@
+# RK3399 hexa core 4GB SoC 2.5GbE eMMC USB3 SATA M.2 UPS
+BOARD_NAME="Helios64"
+BOARDFAMILY="rk3399"
+BOOTCONFIG="helios64_defconfig"
+KERNEL_TARGET="legacy,current"
+MODULES="lm75"
+FULL_DESKTOP="yes"
+PACKAGE_LIST_BOARD="mdadm i2c-tools"
+PACKAGE_LIST_BOARD_REMOVE="fake-hwclock"

config/kernel/linux-rk3399-legacy.config

@@ -526,7 +526,9 @@ CONFIG_SUSPEND_FREEZER=y
 # CONFIG_SUSPEND_SKIP_SYNC is not set
 CONFIG_HAS_WAKELOCK=y
 CONFIG_WAKELOCK=y
-# CONFIG_HIBERNATION is not set
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_PM_STD_PARTITION=""
 CONFIG_PM_SLEEP=y
 CONFIG_PM_SLEEP_SMP=y
 # CONFIG_PM_AUTOSLEEP is not set
@@ -545,6 +547,7 @@ CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
 CONFIG_PM_GENERIC_DOMAINS_OF=y
 CONFIG_CPU_PM=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_HIBERNATION_HEADER=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
@@ -1904,7 +1907,7 @@ CONFIG_DM_MULTIPATH=m
 CONFIG_DM_MULTIPATH_QL=m
 CONFIG_DM_MULTIPATH_ST=m
 CONFIG_DM_DELAY=m
-# CONFIG_DM_UEVENT is not set
+CONFIG_DM_UEVENT=y
 CONFIG_DM_FLAKEY=m
 CONFIG_DM_VERITY=m
 # CONFIG_DM_VERITY_FEC is not set
@@ -2662,7 +2665,7 @@ CONFIG_INPUT_AD714X_SPI=m
 # CONFIG_INPUT_MMA8450 is not set
 # CONFIG_INPUT_MPU3050 is not set
 # CONFIG_INPUT_GP2A is not set
-# CONFIG_INPUT_GPIO_BEEPER is not set
+CONFIG_INPUT_GPIO_BEEPER=m
 # CONFIG_INPUT_GPIO_TILT_POLLED is not set
 CONFIG_INPUT_ATI_REMOTE2=m
 CONFIG_INPUT_KEYCHORD=m
@@ -2940,6 +2943,7 @@ CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_DEVRES=y
 CONFIG_OF_GPIO=y
+CONFIG_GPIOLIB_IRQCHIP=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_GENERIC=y
@@ -2966,7 +2970,8 @@ CONFIG_GPIO_GENERIC_PLATFORM=y
 # CONFIG_GPIO_ADNP is not set
 # CONFIG_GPIO_MAX7300 is not set
 # CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
 # CONFIG_GPIO_PCF857X is not set
 # CONFIG_GPIO_SX150X is not set
 
@@ -3032,7 +3037,7 @@ CONFIG_W1_SLAVE_BQ27000=m
 CONFIG_POWER_SUPPLY=y
 # CONFIG_POWER_SUPPLY_DEBUG is not set
 # CONFIG_PDA_POWER is not set
-# CONFIG_GENERIC_ADC_BATTERY is not set
+CONFIG_GENERIC_ADC_BATTERY=m
 # CONFIG_TEST_POWER is not set
 CONFIG_BATTERY_DS2760=m
 # CONFIG_BATTERY_DS2780 is not set
@@ -4449,12 +4454,12 @@ CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
 # CONFIG_SND_SOC_ROCKCHIP_VAD is not set
 # CONFIG_SND_SOC_ROCKCHIP_DA7219 is not set
 # CONFIG_SND_SOC_ROCKCHIP_HDMI_ANALOG is not set
-# CONFIG_SND_SOC_ROCKCHIP_HDMI_DP is not set
+CONFIG_SND_SOC_ROCKCHIP_HDMI_DP=m
 CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
 # CONFIG_SND_SOC_ROCKCHIP_MULTICODECS is not set
 CONFIG_SND_SOC_ROCKCHIP_RT5645=y
 # CONFIG_SND_SOC_ROCKCHIP_RT5651_TC358749 is not set
-# CONFIG_SND_SOC_ROCKCHIP_CDNDP is not set
+CONFIG_SND_SOC_ROCKCHIP_CDNDP=m
 
 #
 # Allwinner SoC Audio support
@@ -5007,7 +5012,7 @@ CONFIG_USB_G_WEBCAM=m
 #
 # CONFIG_USB20_HOST is not set
 # CONFIG_USB20_OTG is not set
-# CONFIG_USB_LED_TRIG is not set
+CONFIG_USB_LED_TRIG=y
 # CONFIG_UWB is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
@@ -5534,7 +5539,8 @@ CONFIG_ROCKCHIP_OPP=y
 # CONFIG_ROCKCHIP_PM_TEST is not set
 CONFIG_ROCKCHIP_GRF=y
 CONFIG_ROCKCHIP_PM_DOMAINS=y
-# CONFIG_ROCKCHIP_PVTM is not set
+CONFIG_ROCKCHIP_PVTM=y
+CONFIG_ROCKCHIP_SUSPEND_MODE=y
 CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
 # CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER is not set
 # CONFIG_SUNXI_SRAM is not set
@@ -5887,7 +5893,7 @@ CONFIG_RK_FLASH=m
 CONFIG_ARM_PSCI_FW=y
 # CONFIG_FIRMWARE_MEMMAP is not set
 CONFIG_HAVE_ARM_SMCCC=y
-# CONFIG_ROCKCHIP_SIP is not set
+CONFIG_ROCKCHIP_SIP=y
 # CONFIG_ACPI is not set
 
 #

config/kernel/linux-rockchip64-current.config

@@ -3397,7 +3397,7 @@ CONFIG_INPUT_MSM_VIBRATOR=m
 CONFIG_INPUT_MAX77650_ONKEY=m
 # CONFIG_INPUT_MMA8450 is not set
 # CONFIG_INPUT_GP2A is not set
-# CONFIG_INPUT_GPIO_BEEPER is not set
+CONFIG_INPUT_GPIO_BEEPER=m
 CONFIG_INPUT_GPIO_DECODER=m
 CONFIG_INPUT_GPIO_VIBRA=m
 # CONFIG_INPUT_ATI_REMOTE2 is not set
@@ -3836,7 +3836,8 @@ CONFIG_GPIO_ADNP=m
 CONFIG_GPIO_GW_PLD=m
 CONFIG_GPIO_MAX7300=m
 CONFIG_GPIO_MAX732X=m
-CONFIG_GPIO_PCA953X=m
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_PCF857X=m
 CONFIG_GPIO_TPIC2810=m
 # end of I2C GPIO expanders
@@ -3938,7 +3939,7 @@ CONFIG_POWER_SUPPLY=y
 # CONFIG_POWER_SUPPLY_DEBUG is not set
 CONFIG_POWER_SUPPLY_HWMON=y
 # CONFIG_PDA_POWER is not set
-# CONFIG_GENERIC_ADC_BATTERY is not set
+CONFIG_GENERIC_ADC_BATTERY=m
 # CONFIG_TEST_POWER is not set
 CONFIG_CHARGER_ADP5061=m
 CONFIG_BATTERY_CW2015=m

config/sources/families/include/rockchip64_common.inc

@@ -298,6 +298,16 @@ family_tweaks_bsp()
 		cp $SRC/packages/bsp/pinebook-pro/xorg.conf $destination/etc/X11/
 	fi
 
+	if [[ $BOARD == helios64 ]]; then
+
+		mkdir -p $destination/etc/udev/rules.d/
+		mkdir -p $destination/lib/systemd/system-shutdown/
+		cp $SRC/packages/bsp/helios64/50-usb-realtek-net.rules $destination/etc/udev/rules.d/
+		cp $SRC/packages/bsp/helios64/70-keep-usb-lan-as-eth1.rules $destination/etc/udev/rules.d/
+		cp $SRC/packages/bsp/helios64/asound.conf $destination/etc/
+		install -m 755 $SRC/packages/bsp/helios64/disable_auto_poweron $destination/lib/systemd/system-shutdown/
+	fi
+
 	# Graphics and media
 	mkdir -p $destination/etc/udev/rules.d
 	cp $SRC/packages/bsp/rk3399/50-mali.rules $destination/etc/udev/rules.d/

config/sources/families/rk3399.conf

@@ -20,6 +20,17 @@ if [[ $BOARD == roc-rk3399-pc ]]; then
 
 	BOOT_USE_MAINLINE_ATF=yes
 
+elif [[ $BOARD == helios64 ]]; then
+
+	if [[ $BRANCH == legacy ]]; then
+		BOOT_USE_BLOBS=yes
+		DDR_BLOB='rk33/rk3399_ddr_933MHz_v1.24.bin'
+		MINILOADER_BLOB='rk33/rk3399_miniloader_v1.19.bin'
+		BL31_BLOB='rk33/rk3399_bl31_v1.30.elf'
+	else
+		BOOT_USE_MAINLINE_ATF=yes
+	fi
+
 elif [[ $BOARD == nanopim4v2 || $BOARD == orangepi4 ]]; then
 
 	BOOT_USE_BLOBS=yes

config/targets.conf

@@ -83,6 +83,13 @@ helios4				current			focal		cli			stable	yes
 helios4				current			bullseye	cli			stable	yes
 helios4				current			focal		cli			beta	yes
 
+# Helios64
+helios64			legacy			buster		cli			stable	yes
+helios64			current			buster		cli			stable	yes
+helios64			current			bionic		cli			stable	yes
+helios64			current			focal		cli			stable	yes
+helios64			current			bullseye	cli			stable	yes
+
 # Clearfog Base
 clearfogbase			legacy			buster		cli			stable	no
 clearfogbase			current			buster		cli			stable	yes

packages/bsp/common/usr/lib/armbian/armbian-firstrun

@@ -131,7 +131,7 @@ case "$1" in
 	esac
 
 	# varios temporary hardware workarounds
-	[[ $LINUXFAMILY == rk3399 || $LINUXFAMILY == rockchip64 ]] && set_fixed_mac
+	[[ $LINUXFAMILY == rk3399 || $LINUXFAMILY == rockchip64 ]] && [[ $BOARD != helios64 ]] && set_fixed_mac
 	[[ $BRANCH == dev && $LINUXFAMILY == rockchip ]] && set_fixed_mac
 	[[ $BRANCH == current && $LINUXFAMILY == odroidc1 ]] && set_fixed_mac
 	[[ $LINUXFAMILY == meson64 ]] && set_fixed_mac

packages/bsp/helios64/50-usb-realtek-net.rules

@@ -0,0 +1,38 @@
+# This is used to change the default configuration of Realtek USB ethernet adapters
+
+ACTION!="add", GOTO="usb_realtek_net_end"
+SUBSYSTEM!="usb", GOTO="usb_realtek_net_end"
+ENV{DEVTYPE}!="usb_device", GOTO="usb_realtek_net_end"
+
+# Modify this to change the default value
+ENV{REALTEK_NIC_MODE}="1"
+
+# Realtek
+ATTR{idVendor}=="0bda", ATTR{idProduct}=="8156", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="0bda", ATTR{idProduct}=="8153", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="0bda", ATTR{idProduct}=="8152", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+
+# Samsung
+ATTR{idVendor}=="04e8", ATTR{idProduct}=="a101", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+
+# Lenovo
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="304f", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="3052", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="3054", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="3057", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="3082", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="7205", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="720a", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="720b", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="720c", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="721e", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="a359", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+ATTR{idVendor}=="17ef", ATTR{idProduct}=="a387", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+
+# TP-LINK
+ATTR{idVendor}=="2357", ATTR{idProduct}=="0601", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+
+# Nvidia
+ATTR{idVendor}=="0955", ATTR{idProduct}=="09ff", ATTR{bConfigurationValue}!="$env{REALTEK_NIC_MODE}", ATTR{bConfigurationValue}="$env{REALTEK_NIC_MODE}"
+
+LABEL="usb_realtek_net_end"

packages/bsp/helios64/70-keep-usb-lan-as-eth1.rules

@@ -0,0 +1 @@
+SUBSYSTEM=="net", ACTION=="add", DRIVERS=="r8152", KERNEL=="eth1", NAME="eth1"

packages/bsp/helios64/asound.conf

@@ -0,0 +1,2 @@
+defaults.pcm.!card rkhdmidpsound
+defaults.ctl.!card rkhdmidpsound

packages/bsp/helios64/disable_auto_poweron

@@ -0,0 +1,18 @@
+#!/bin/bash
+
+# Export GPIO
+# AUTO_ON_D
+echo 153 > /sys/class/gpio/export
+# AUTO_EN_CLK
+echo 154 > /sys/class/gpio/export
+
+echo out > /sys/class/gpio/gpio153/direction
+echo out > /sys/class/gpio/gpio154/direction
+
+# Toggling the D Flip-Flop
+echo 0 > /sys/class/gpio/gpio153/value
+echo 0 > /sys/class/gpio/gpio154/value
+sleep 0.1
+echo 1 > /sys/class/gpio/gpio154/value
+sleep 0.1
+echo 0 > /sys/class/gpio/gpio154/value

patch/kernel/rk3399-legacy/pci-host-rockchip-0000-scan-bus-fix-from-rockchip64.patch

@@ -0,0 +1,241 @@
+From e5467fb60570c9c300e9d412b9d5386cbb9951ba Mon Sep 17 00:00:00 2001
+From: Aditya Prayoga <aditya@kobol.io>
+Date: Mon, 18 May 2020 09:42:14 +0700
+Subject: [PATCH] port pcie changes from ayufan rockchip64
+
+Signed-off-by: Aditya Prayoga <aditya@kobol.io>
+---
+ drivers/pci/host/pcie-rockchip.c | 119 +++++++++++++++++++++++++------
+ 1 file changed, 96 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
+index 87291016d..1823323f8 100644
+--- a/drivers/pci/host/pcie-rockchip.c
++++ b/drivers/pci/host/pcie-rockchip.c
+@@ -26,6 +26,7 @@
+ #include <linux/irqdomain.h>
+ #include <linux/kernel.h>
+ #include <linux/mfd/syscon.h>
++#include <linux/moduleparam.h>
+ #include <linux/of_address.h>
+ #include <linux/of_device.h>
+ #include <linux/of_pci.h>
+@@ -153,6 +154,7 @@
+ 		 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
+ 		 PCIE_CORE_INT_MMVC)
+ 
++#define PCIE_RC_CONFIG_NORMAL_BASE	0x800000
+ #define PCIE_RC_CONFIG_BASE		0xa00000
+ #define PCIE_RC_CONFIG_RID_CCR		(PCIE_RC_CONFIG_BASE + 0x08)
+ #define   PCIE_RC_CONFIG_SCC_SHIFT		16
+@@ -189,6 +191,8 @@
+ #define IB_ROOT_PORT_REG_SIZE_SHIFT		3
+ #define AXI_WRAPPER_IO_WRITE			0x6
+ #define AXI_WRAPPER_MEM_WRITE			0x2
++#define AXI_WRAPPER_TYPE0_CFG			0xa
++#define AXI_WRAPPER_TYPE1_CFG			0xb
+ #define AXI_WRAPPER_CFG0			0xa
+ #define AXI_WRAPPER_NOR_MSG			0xc
+ 
+@@ -213,6 +217,7 @@
+ #define RC_REGION_0_ADDR_TRANS_H		0x00000000
+ #define RC_REGION_0_ADDR_TRANS_L		0x00000000
+ #define RC_REGION_0_PASS_BITS			(25 - 1)
++#define RC_REGION_0_TYPE_MASK			GENMASK(3, 0)
+ #define MAX_AXI_WRAPPER_REGION_NUM		33
+ 
+ struct rockchip_pcie {
+@@ -253,8 +258,12 @@ struct rockchip_pcie {
+ 	int wait_ep;
+ 	struct dma_trx_obj *dma_obj;
+ 	struct list_head resources;
++	u32	bus_scan_delay;
+ };
+ 
++static int bus_scan_delay = -1;
++core_param(pcie_rk_bus_scan_delay, bus_scan_delay, int, S_IRUGO);
++
+ static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
+ {
+ 	return readl(rockchip->apb_base + reg);
+@@ -330,7 +339,9 @@ static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
+ static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
+ 				     int where, int size, u32 *val)
+ {
+-	void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
++	void __iomem *addr;
++
++	addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where;
+ 
+ 	if (!IS_ALIGNED((uintptr_t)addr, size)) {
+ 		*val = 0;
+@@ -354,11 +365,13 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
+ 				     int where, int size, u32 val)
+ {
+ 	u32 mask, tmp, offset;
++	void __iomem *addr;
+ 
+ 	offset = where & ~0x3;
++	addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset;
+ 
+ 	if (size == 4) {
+-		writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
++		writel(val, addr);
+ 		return PCIBIOS_SUCCESSFUL;
+ 	}
+ 
+@@ -369,13 +382,33 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
+ 	 * corrupt RW1C bits in adjacent registers.  But the hardware
+ 	 * doesn't support smaller writes.
+ 	 */
+-	tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
++	tmp = readl(addr) & mask;
+ 	tmp |= val << ((where & 0x3) * 8);
+-	writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
++	writel(tmp, addr);
+ 
+ 	return PCIBIOS_SUCCESSFUL;
+ }
+ 
++static void rockchip_pcie_cfg_configuration_accesses(
++		struct rockchip_pcie *rockchip, u32 type)
++{
++	u32 ob_desc_0;
++
++	/* Configuration Accesses for region 0 */
++	rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
++
++	rockchip_pcie_write(rockchip,
++			    (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
++			    PCIE_CORE_OB_REGION_ADDR0);
++	rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
++			    PCIE_CORE_OB_REGION_ADDR1);
++	ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0);
++	ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK);
++	ob_desc_0 |= (type | (0x1 << 23));
++	rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0);
++	rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
++}
++
+ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
+ 				       struct pci_bus *bus, u32 devfn,
+ 				       int where, int size, u32 *val)
+@@ -385,11 +418,23 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
+ 	busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
+ 				PCI_FUNC(devfn), where);
+ 
++	if (bus->number > 0x1f) {
++		*val = 0;
++		return PCIBIOS_DEVICE_NOT_FOUND;
++	}
++
+ 	if (!IS_ALIGNED(busdev, size)) {
+ 		*val = 0;
+ 		return PCIBIOS_BAD_REGISTER_NUMBER;
+ 	}
+ 
++	if (bus->parent->number == rockchip->root_bus_nr)
++		rockchip_pcie_cfg_configuration_accesses(rockchip,
++						AXI_WRAPPER_TYPE0_CFG);
++	else
++		rockchip_pcie_cfg_configuration_accesses(rockchip,
++						AXI_WRAPPER_TYPE1_CFG);
++
+ 	if (size == 4) {
+ 		*val = readl(rockchip->reg_base + busdev);
+ 	} else if (size == 2) {
+@@ -411,9 +456,19 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
+ 
+ 	busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
+ 				PCI_FUNC(devfn), where);
++
++	if (bus->number > 0x1f)
++		return PCIBIOS_DEVICE_NOT_FOUND;
+ 	if (!IS_ALIGNED(busdev, size))
+ 		return PCIBIOS_BAD_REGISTER_NUMBER;
+ 
++	if (bus->parent->number == rockchip->root_bus_nr)
++		rockchip_pcie_cfg_configuration_accesses(rockchip,
++						AXI_WRAPPER_TYPE0_CFG);
++	else
++		rockchip_pcie_cfg_configuration_accesses(rockchip,
++						AXI_WRAPPER_TYPE1_CFG);
++
+ 	if (size == 4)
+ 		writel(val, rockchip->reg_base + busdev);
+ 	else if (size == 2)
+@@ -638,6 +693,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
+ 	status |= PCI_EXP_LNKCTL_CCC;
+ 	rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
+ 
++	/* Set RC's RCB to 128 */
++	status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
++	status |= PCI_EXP_LNKCTL_RCB;
++	rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
++
+ 	/* Enable Gen1 training */
+ 	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
+ 			    PCIE_CLIENT_CONFIG);
+@@ -696,15 +756,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
+ 		rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
+ 	}
+ 
+-	rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
+-
+-	rockchip_pcie_write(rockchip,
+-			    (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
+-			    PCIE_CORE_OB_REGION_ADDR0);
+-	rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
+-			    PCIE_CORE_OB_REGION_ADDR1);
+-	rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
+-	rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
++	rockchip_pcie_cfg_configuration_accesses(rockchip,
++					AXI_WRAPPER_TYPE0_CFG);
+ 
+ 	return 0;
+ }
+@@ -1067,6 +1120,14 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
+ 		dev_info(dev, "no vpcie0v9 regulator found\n");
+ 	}
+ 
++	err = of_property_read_u32(node, "bus-scan-delay-ms", &rockchip->bus_scan_delay);
++	if (err) {
++		dev_info(dev, "no bus-scan-delay-ms in device tree, default 0 ms\n");
++		rockchip->bus_scan_delay = 0;
++	} else {
++		dev_info(dev, "bus-scan-delay-ms in device tree is %u ms\n", rockchip->bus_scan_delay);
++	}
++
+ 	mem = of_parse_phandle(node, "memory-region", 0);
+ 	if (!mem) {
+ 		dev_warn(dev, "missing \"memory-region\" property\n");
+@@ -1396,6 +1457,7 @@ static int rockchip_pcie_really_probe(struct rockchip_pcie *rockchip)
+ 	int err;
+ 	struct pci_bus *bus, *child;
+ 	struct	device *dev = rockchip->dev;
++	u32 delay = 0;
+ 
+ 	err = rockchip_pcie_init_port(rockchip);
+ 	if (err)
+@@ -1407,6 +1469,18 @@ static int rockchip_pcie_really_probe(struct rockchip_pcie *rockchip)
+ 	if (err)
+ 		return err;
+ 
++	/* Prefer command-line param over device tree */
++	if (bus_scan_delay > 0) {
++		delay = bus_scan_delay;
++		dev_info(dev, "wait %u ms (from command-line) before bus scan\n", delay);
++	} else if (rockchip->bus_scan_delay > 0 && bus_scan_delay < 0) {
++		delay = rockchip->bus_scan_delay;
++		dev_info(dev, "wait %u ms (from device tree) before bus scan\n", delay);
++	}
++	if (delay > 0) {
++		msleep(delay);
++	}
++
+ 	bus = pci_scan_root_bus(dev, 0, &rockchip_pcie_ops,
+ 				rockchip, &rockchip->resources);
+ 	if (!bus)
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+

patch/kernel/rk3399-legacy/pci-host-rockchip-0001-backport-fix-power-stable-and-config-access.patch

@@ -0,0 +1,45 @@
+From 6606ce73fb42a987b1cc45edbeb7c5e78246fb51 Mon Sep 17 00:00:00 2001
+From: Aditya Prayoga <aditya@kobol.io>
+Date: Wed, 10 Jun 2020 17:21:06 +0700
+Subject: [PATCH] backport pcie fix power stable and config access
+
+Signed-off-by: Aditya Prayoga <aditya@kobol.io>
+---
+ drivers/pci/host/pcie-rockchip.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
+index 1823323f8..f57571863 100644
+--- a/drivers/pci/host/pcie-rockchip.c
++++ b/drivers/pci/host/pcie-rockchip.c
+@@ -394,8 +394,11 @@ static void rockchip_pcie_cfg_configuration_accesses(
+ {
+ 	u32 ob_desc_0;
+ 
+-	/* Configuration Accesses for region 0 */
+-	rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
++	/*
++	 * Configuration Accesses for region 0.
++	 * Bit 19 is for enabling IO base and limit registers.
++	 */
++	rockchip_pcie_write(rockchip, BIT(19), PCIE_RC_BAR_CONF);
+ 
+ 	rockchip_pcie_write(rockchip,
+ 			    (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
+@@ -701,6 +704,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
+ 	/* Enable Gen1 training */
+ 	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
+ 			    PCIE_CLIENT_CONFIG);
++	/*
++	 * According to PCI Express Card Electromechanical Specification
++	 * Revision 3.0, Table 2-4, power stable and reference clk stable
++	 * before PERST# inactive should be at least 100ms and 100us
++	 * respectively. Otherwise we do see some failures for link training.
++	 */
++	msleep(100);
+ 
+ 	gpiod_set_value(rockchip->ep_gpio, 1);
+ 
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+

patch/kernel/rk3399-legacy/roc-rk3399-pc-add-board.patch

@@ -1,16 +1,18 @@
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index adfa8211..2c3a023a 100644
 --- a/arch/arm64/boot/dts/rockchip/Makefile
 +++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -8,7 +8,8 @@
- 	rk3399-nanopi4-rev07.dtb \
- 	rk3399-nanopi4-rev21.dtb \
+@@ -15,7 +15,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ 	rk3399-nanopi-m4v2.dtb \
  	rk3399-nanopi4-rev22.dtb \
+ 	rk3399-helios64.dtb \
 -	rk3399-firefly.dtb
 +	rk3399-firefly.dtb \
 +	rk3399-roc-pc.dtb
  
- else
- 
-@@ -109,6 +110,7 @@
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ 	rk3328-nanopi-r2-rev00.dtb
+@@ -119,6 +120,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin-r0.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin-r1.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-mid-818-android-6.0.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-mid-818-android.dtb
@@ -18,6 +20,9 @@
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960-ab.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rv1-android.dtb
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-exp.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-exp.dts
+new file mode 100644
+index 00000000..cc922411
 --- /dev/null
 +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-exp.dts
 @@ -0,0 +1,20 @@
@@ -41,6 +46,9 @@
 +	status = "okay";
 +};
 +
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mipi.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mipi.dts
+new file mode 100644
+index 00000000..b3145e99
 --- /dev/null
 +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mipi.dts
 @@ -0,0 +1,78 @@
@@ -122,6 +130,9 @@
 +&route_dsi {
 +	status = "disabled";
 +};
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
+new file mode 100644
+index 00000000..0b1c902b
 --- /dev/null
 +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
 @@ -0,0 +1,7 @@
@@ -133,6 +144,9 @@
 +	compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
 +};
 \ No newline at end of file
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+new file mode 100644
+index 00000000..f871f0c5
 --- /dev/null
 +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
 @@ -0,0 +1,1419 @@
@@ -1555,6 +1569,8 @@
 +&isp1_mmu {
 +	status = "okay";
 +};
+diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
+index a2aa50c8..70a7bdb5 100644
 --- a/include/dt-bindings/clock/rk3399-cru.h
 +++ b/include/dt-bindings/clock/rk3399-cru.h
 @@ -31,6 +31,7 @@
@@ -1565,3 +1581,6 @@
  #define SCLK_I2C1			65
  #define SCLK_I2C2			66
  #define SCLK_I2C3			67
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+

patch/u-boot/u-boot-rockchip64-mainline/rk3399-populate-child-node-of-syscon.patch

@@ -0,0 +1,31 @@
+From 91cbd5f4fb25281319034c33b6e0c0f9b7d1e12b Mon Sep 17 00:00:00 2001
+Message-Id: <91cbd5f4fb25281319034c33b6e0c0f9b7d1e12b.1585676333.git.aditya@kobol.io>
+In-Reply-To: <ef8793354dbb6bce3027a3492ffc1fee3588f41f.1585676333.git.aditya@kobol.io>
+References: <ef8793354dbb6bce3027a3492ffc1fee3588f41f.1585676333.git.aditya@kobol.io>
+From: Aditya Prayoga <aditya@kobol.io>
+Date: Wed, 4 Mar 2020 22:10:31 +0700
+Subject: [PATCH 4/4] arm:rockchip:rk3399: Populate child node of syscon
+
+U-Boot only populate first level of node.
+Scan child node so device such as PHY can be initialized.
+---
+ arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
+index 259ca44d68..81b04aa7f8 100644
+--- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
++++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
+@@ -21,6 +21,9 @@ U_BOOT_DRIVER(syscon_rk3399) = {
+ 	.name = "rk3399_syscon",
+ 	.id = UCLASS_SYSCON,
+ 	.of_match = rk3399_syscon_ids,
++#if !CONFIG_IS_ENABLED(OF_PLATDATA)
++	.bind = dm_scan_fdt_dev,
++#endif
+ };
+ 
+ #if CONFIG_IS_ENABLED(OF_PLATDATA)
+-- 
+2.17.1
+