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fix bananam2ultra wifi
This commit is contained in:
Martin Ayotte
parent
1921a758bd
commit
c430a2ac3d
5 changed files with 225 additions and 0 deletions
28
patch/kernel/sunxi-dev/board-h3-add-rtc-osc32k-out.patch
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28
patch/kernel/sunxi-dev/board-h3-add-rtc-osc32k-out.patch
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@ -0,0 +1,28 @@
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diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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index c3bff11..48b8447 100644
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--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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@@ -96,6 +112,13 @@
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clock-output-names = "osc32k";
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};
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+ ext_osc32k: ext_osc32k_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <32768>;
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+ clock-output-names = "ext_osc32k";
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+ };
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+
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iosc: internal-osc-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@@ -795,6 +861,9 @@
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reg = <0x01f00000 0x54>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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+ clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
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+ clocks = <&ext_osc32k>;
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+ #clock-cells = <1>;
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};
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r_ccu: clock@1f01400 {
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@ -0,0 +1,42 @@
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diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
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index bd97ca3..a8a522f 100644
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--- a/arch/arm/boot/dts/sun8i-r40.dtsi
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+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
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@@ -68,6 +71,23 @@
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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+
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+ osc24M_32k: clk@1 {
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+ #clock-cells = <0>;
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+ compatible = "fixed-factor-clock";
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+ clock-div = <732>;
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+ clock-mult = <1>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "osc24M_32k";
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+ };
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+
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+ clk_out_a: clk@01c201f0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun7i-a20-out-clk";
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+ reg = <0x01c201f0 0x4>;
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+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
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+ clock-output-names = "clk_out_a";
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+ };
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};
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cpus {
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@@ -265,6 +340,13 @@
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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+ clk_out_a_pin: clk-out-a-pin {
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+ pins = "PI12";
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+ function = "clk_out_a";
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+ drive = <0>;
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+ pull = <0>;
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+ };
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+
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gmac_rgmii_pins: gmac-rgmii-pins {
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pins = "PA0", "PA1", "PA2", "PA3",
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"PA4", "PA5", "PA6", "PA7",
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13
patch/kernel/sunxi-dev/fix-bananapi-m2-plus-wifi.patch
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13
patch/kernel/sunxi-dev/fix-bananapi-m2-plus-wifi.patch
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@ -0,0 +1,13 @@
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diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
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index 195a75d..f3f324e 100644
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--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
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@@ -48,3 +48,8 @@
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model = "Banana Pi BPI-M2-Plus H3";
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compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
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};
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+
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+&wifi_pwrseq {
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+ clocks = <&rtc 1>;
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+ clock-names = "ext_clock";
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+};
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108
patch/kernel/sunxi-dev/fix-bananapi-m2-ultra-wifi.patch
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108
patch/kernel/sunxi-dev/fix-bananapi-m2-ultra-wifi.patch
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@ -0,0 +1,108 @@
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diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
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index 438b7b4..829c67a 100644
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--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
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+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
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@@ -102,6 +102,8 @@
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wifi_pwrseq: wifi_pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
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+ clocks = <&ccu CLK_OUTA>;
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+ clock-names = "ext_clock";
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};
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};
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@@ -178,6 +180,15 @@
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bus-width = <4>;
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non-removable;
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status = "okay";
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+
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+ brcmf: bcrmf@1 {
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+ reg = <1>;
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+ compatible = "brcm,bcm4329-fmac";
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+ interrupt-names = "host-wake";
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+ clocks = <&clk_out_a>;
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+ pinctrl-0 = <&clk_out_a_pin>;
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+ pinctrl-names = "default";
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+ };
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};
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&mmc2 {
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@@ -196,6 +207,11 @@
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status = "okay";
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};
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+&pio {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&clk_out_a_pin>;
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+};
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+
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®_aldo2 {
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regulator-always-on;
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regulator-min-microvolt = <2500000>;
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@@ -251,11 +267,19 @@
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};
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®_dldo2 {
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+ regulator-always-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc-wifi";
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};
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+®_dldo3 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "vcc-wifi-2";
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+};
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+
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®_dldo4 {
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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@@ -278,6 +302,25 @@
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status = "okay";
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};
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+&uart3 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
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+ uart-has-rtscts;
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+ status = "okay";
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+
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+ bluetooth {
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+ compatible = "brcm,bcm43438-bt";
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+ clocks = <&ccu CLK_OUTA>;
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+ clock-names = "lpo";
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+ vbat-supply = <®_dldo2>;
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+ vddio-supply = <®_dldo1>;
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+ device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
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+ /* TODO host wake line connected to PMIC GPIO pins */
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+ shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
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+ max-speed = <1500000>;
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+ };
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+};
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+
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&usbphy {
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usb1_vbus-supply = <®_vcc5v0>;
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usb2_vbus-supply = <®_vcc5v0>;
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diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
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index 6f4c9ca..0781b85 100644
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--- a/arch/arm/boot/dts/sun8i-r40.dtsi
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+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
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@@ -377,6 +401,16 @@
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pins = "PB22", "PB23";
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function = "uart0";
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};
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+
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+ uart3_pg_pins: uart3-pg-pins {
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+ pins = "PG6", "PG7";
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+ function = "uart3";
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+ };
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+
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+ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
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+ pins = "PG8", "PG9";
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+ function = "uart3";
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+ };
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};
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wdt: watchdog@1c20c90 {
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34
patch/kernel/sunxi-dev/wifi-bt-bananapi-m2-plus.patch
Normal file
34
patch/kernel/sunxi-dev/wifi-bt-bananapi-m2-plus.patch
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@ -0,0 +1,34 @@
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diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
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index b3283ae..46a1507 100644
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--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
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+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
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@@ -103,6 +103,8 @@
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compatible = "mmc-pwrseq-simple";
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pinctrl-names = "default";
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reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
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+ clocks = <&rtc 1>;
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+ clock-names = "ext_clock";
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};
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};
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@@ -215,7 +217,19 @@
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
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- status = "okay";
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+ uart-has-rtscts;
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+ status = "okay";
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+
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+ bluetooth {
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+ compatible = "brcm,bcm43438-bt";
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+ clocks = <&rtc 1>;
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+ clock-names = "lpo";
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+ vbat-supply = <®_vcc3v3>;
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+ vddio-supply = <®_vcc3v3>;
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+ device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
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+ host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
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+ shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
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+ };
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};
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&usb_otg {
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