diff --git a/patch/kernel/rockchip-current/4005-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch.disabled b/patch/kernel/rockchip-current/4005-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch similarity index 99% rename from patch/kernel/rockchip-current/4005-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch.disabled rename to patch/kernel/rockchip-current/4005-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch index 21ef1308f..80f6e8632 100644 --- a/patch/kernel/rockchip-current/4005-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch.disabled +++ b/patch/kernel/rockchip-current/4005-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch @@ -37,7 +37,7 @@ index 7f56d8c34..7d7ee5b26 100644 - 148500000, { 0x0000, 0x0038, 0x0038 }, - }, { + 600000000, { 0x0000, 0x0000, 0x0000 }, -+ }, { ++ }, { ~0UL, { 0x0000, 0x0000, 0x0000}, } }; diff --git a/patch/kernel/rockchip-current/4007-drm-rockchip-dw_hdmi-Use-auto-generated-tables.patch.disabled b/patch/kernel/rockchip-current/4007-drm-rockchip-dw_hdmi-Use-auto-generated-tables.patch similarity index 100% rename from patch/kernel/rockchip-current/4007-drm-rockchip-dw_hdmi-Use-auto-generated-tables.patch.disabled rename to patch/kernel/rockchip-current/4007-drm-rockchip-dw_hdmi-Use-auto-generated-tables.patch diff --git a/patch/kernel/rockchip-current/4009-drm-rockchip-dw-hdmi-limit-tmds-to-340mhz.patch b/patch/kernel/rockchip-current/4009-drm-rockchip-dw-hdmi-limit-tmds-to-340mhz.patch new file mode 100644 index 000000000..24547a249 --- /dev/null +++ b/patch/kernel/rockchip-current/4009-drm-rockchip-dw-hdmi-limit-tmds-to-340mhz.patch @@ -0,0 +1,50 @@ +From f83d188f49bd11d085c3f4160b208cb8194daff4 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Wed, 8 Jan 2020 21:07:52 +0000 +Subject: [PATCH] drm/rockchip: dw-hdmi: limit tmds to 340mhz + +RK3228/RK3328 does not provide a stable hdmi signal at TMDS rates +above 371.25MHz (340MHz pixel clock). + +Limit the pixel clock rate to 340MHz to provide a stable signal. +Also limit the pixel clock to the display reported max tmds clock. + +This also enables use of pixel clocks up to 340MHz on RK3288/RK3399. +And limit resolution to 3840x2160 + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++------------ + 1 file changed, 4 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index b5d2cdaa24fa..5f7ab8e6bb72 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -221,19 +221,11 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, + const struct drm_display_info *info, + const struct drm_display_mode *mode) + { +- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; +- int pclk = mode->clock * 1000; +- bool valid = false; +- int i; ++ if (mode->clock > 340000 || ++ (info->max_tmds_clock && mode->clock > info->max_tmds_clock)) ++ return MODE_CLOCK_HIGH; + +- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { +- if (pclk == mpll_cfg[i].mpixelclock) { +- valid = true; +- break; +- } +- } +- +- return (valid) ? MODE_OK : MODE_BAD; ++ return drm_mode_validate_size(mode, 3840, 2160); + } + + static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) +-- +2.26.2 + diff --git a/patch/kernel/rockchip-current/4009-drm-rockchip-dw-hdmi-limit-tmds-to-340mhz.patch.disabled b/patch/kernel/rockchip-current/4009-drm-rockchip-dw-hdmi-limit-tmds-to-340mhz.patch.disabled deleted file mode 100644 index d8d4b0fcc..000000000 --- a/patch/kernel/rockchip-current/4009-drm-rockchip-dw-hdmi-limit-tmds-to-340mhz.patch.disabled +++ /dev/null @@ -1,48 +0,0 @@ -From 13fe05c1a6a0b7b81d7c6768eef9fbc618b75f30 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 3 May 2020 17:09:41 +0000 -Subject: [PATCH 10/14] drm/rockchip: dw-hdmi: limit tmds to 340mhz - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 23 ++++++++++----------- - 1 file changed, 11 insertions(+), 12 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 1a047f9d0..955fc3cf4 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -219,19 +219,18 @@ static enum drm_mode_status - dw_hdmi_rockchip_mode_valid(struct drm_connector *connector, - const struct drm_display_mode *mode) - { -- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; -- int pclk = mode->clock * 1000; -- bool valid = false; -- int i; -- -- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { -- if (pclk == mpll_cfg[i].mpixelclock) { -- valid = true; -- break; -- } -- } -+ struct drm_display_info *info = &connector->display_info; -+ int max_tmds_clock = max(info->max_tmds_clock, 165000); -+ int clock = mode->clock; -+ -+ if (connector->ycbcr_420_allowed && drm_mode_is_420(info, mode) && -+ (info->color_formats & DRM_COLOR_FORMAT_YCRCB420)) -+ clock /= 2; -+ -+ if (clock > max_tmds_clock || clock > 340000) -+ return MODE_CLOCK_HIGH; - -- return (valid) ? MODE_OK : MODE_BAD; -+ return MODE_OK; - } - - static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = { --- -2.26.2 - diff --git a/patch/kernel/rockchip64-current/rk3399-add-overclock-overlay.patch b/patch/kernel/rockchip64-current/overlays-00-add-oc-opp-rk3399.patch similarity index 100% rename from patch/kernel/rockchip64-current/rk3399-add-overclock-overlay.patch rename to patch/kernel/rockchip64-current/overlays-00-add-oc-opp-rk3399.patch diff --git a/patch/kernel/rockchip64-current/overlays-01-add-oc-opp-rk3328.patch b/patch/kernel/rockchip64-current/overlays-01-add-oc-opp-rk3328.patch new file mode 100644 index 000000000..61db1abb2 --- /dev/null +++ b/patch/kernel/rockchip64-current/overlays-01-add-oc-opp-rk3328.patch @@ -0,0 +1,94 @@ +From a053b706be60b3dd13803ece30ff6eb143339bc2 Mon Sep 17 00:00:00 2001 +From: tonymac32 +Date: Thu, 17 Dec 2020 01:33:33 -0500 +Subject: [PATCH] rk3328-oc-opps + +Signed-off-by: tonymac32 +--- + arch/arm64/boot/dts/rockchip/overlay/Makefile | 2 ++ + .../dts/rockchip/overlay/README.rockchip-overlays | 10 ++++++++++ + .../overlay/rockchip-rk3328-opp-1.4ghz.dts | 15 +++++++++++++++ + .../overlay/rockchip-rk3328-opp-1.5ghz.dts | 15 +++++++++++++++ + 4 files changed, 42 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.4ghz.dts + create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.5ghz.dts + +diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile +index 9bc4942bd..9c07d64a1 100644 +--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile ++++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile +@@ -3,6 +3,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ + rockchip-i2c7.dtbo \ + rockchip-i2c8.dtbo \ + rockchip-pcie-gen2.dtbo \ ++ rockchip-rk3328-opp-1.4ghz.dtbo \ ++ rockchip-rk3328-opp-1.5ghz.dtbo \ + rockchip-rk3399-opp-2ghz.dtbo \ + rockchip-spi-jedec-nor.dtbo \ + rockchip-spi-spidev.dtbo \ +diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays +index ce0b84e00..d6979437a 100644 +--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays ++++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays +@@ -29,6 +29,16 @@ I2C8 pins (SCL, SDA): GPIO1-C5, GPIO1-C4 + Enables PCIe Gen2 link speed on RK3399. + WARNING! Not officially supported by Rockchip!!! + ++### rk3328-opp-1.4ghz ++ ++Adds the 1.4GHz opp for overclocking ++WARNING! Not officially supported by Rockchip!!! ++ ++### rk3328-opp-1.5ghz ++ ++Adds the 1.5GHz opp for overclocking ++WARNING! Not officially supported by Rockchip!!! ++ + ### rk3399-opp-2ghz + + Adds the 2GHz big and 1.5 GHz LITTLE opps for overclocking +diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.4ghz.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.4ghz.dts +new file mode 100644 +index 000000000..a7ad9d572 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.4ghz.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++ ++/ { ++ compatible = "rockchip,rk3328"; ++ fragment@0 { ++ target-path = "/opp_table0"; ++ __overlay__ { ++ opp-1392000000 { ++ opp-hz = /bits/ 64 <1392000000>; ++ opp-microvolt = <1400000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.5ghz.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.5ghz.dts +new file mode 100644 +index 000000000..3dfd008ab +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.5ghz.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++ ++/ { ++ compatible = "rockchip,rk3328"; ++ fragment@0 { ++ target-path = "/opp_table0"; ++ __overlay__ { ++ opp-1512000000 { ++ opp-hz = /bits/ 64 <1512000000>; ++ opp-microvolt = <1450000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ }; ++}; +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/kernel/rockchip64-current/rk3328-enable-1512mhz-opp.patch b/patch/kernel/rockchip64-current/rk3328-enable-1512mhz-opp.patch deleted file mode 100644 index 7d67233d6..000000000 --- a/patch/kernel/rockchip64-current/rk3328-enable-1512mhz-opp.patch +++ /dev/null @@ -1,16 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 8dabc6e29..d58c893a6 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -125,6 +125,11 @@ - opp-microvolt = <1300000>; - clock-latency-ns = <40000>; - }; -+ opp-1512000000 { -+ opp-hz = /bits/ 64 <1512000000>; -+ opp-microvolt = <1450000>; -+ clock-latency-ns = <40000>; -+ }; - }; - - amba { diff --git a/patch/kernel/sunxi-dev/0038-ARM-dts-add-gpu-node-to-exynos4.patch b/patch/kernel/sunxi-dev/0038-ARM-dts-add-gpu-node-to-exynos4.patch deleted file mode 100644 index 1503b5f07..000000000 --- a/patch/kernel/sunxi-dev/0038-ARM-dts-add-gpu-node-to-exynos4.patch +++ /dev/null @@ -1,64 +0,0 @@ -From eca91d4d36d78c3176480742532b247fd3d72fe0 Mon Sep 17 00:00:00 2001 -From: Simon Shields -Date: Sat, 13 Jan 2018 14:17:26 +1100 -Subject: [PATCH 038/146] ARM: dts: add gpu node to exynos4 - -v2 (Qiang Yu): - add vender string to exynos4 mali gpu - -Based off a similar commit for the Samsung Mali driver by -Tobias Jakobi - -Signed-off-by: Simon Shields -Signed-off-by: Qiang Yu ---- - arch/arm/boot/dts/exynos4.dtsi | 33 +++++++++++++++++++++++++++++++++ - 1 file changed, 33 insertions(+) - -diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi -index 6085e92ac2d7..362461657136 100644 ---- a/arch/arm/boot/dts/exynos4.dtsi -+++ b/arch/arm/boot/dts/exynos4.dtsi -@@ -730,6 +730,39 @@ - status = "disabled"; - }; - -+ gpu: gpu@13000000 { -+ compatible = "samsung,exynos4-mali", "arm,mali-400"; -+ reg = <0x13000000 0x30000>; -+ power-domains = <&pd_g3d>; -+ -+ /* -+ * Propagate VPLL output clock to SCLK_G3D and -+ * ensure that the DIV_G3D divider is 1. -+ */ -+ assigned-clocks = <&clock CLK_MOUT_G3D1>, <&clock CLK_MOUT_G3D>, -+ <&clock CLK_FOUT_VPLL>, <&clock CLK_SCLK_G3D>; -+ assigned-clock-parents = <&clock CLK_SCLK_VPLL>, -+ <&clock CLK_MOUT_G3D1>; -+ assigned-clock-rates = <0>, <0>, <160000000>, <160000000>; -+ -+ clocks = <&clock CLK_SCLK_G3D>, <&clock CLK_G3D>; -+ clock-names = "bus", "core"; -+ -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-names = "ppmmu0", "ppmmu1", "ppmmu2", "ppmmu3", -+ "gpmmu", "pp0", "pp1", "pp2", "pp3", "gp"; -+ status = "disabled"; -+ }; -+ - tmu: tmu@100c0000 { - interrupt-parent = <&combiner>; - reg = <0x100C0000 0x100>; --- -2.17.1 -