diff --git a/patch/kernel/meson64-dev/arm64-meson-g12-enable-support-for-SPIFC.patch b/patch/kernel/meson64-dev/arm64-meson-g12-enable-support-for-SPIFC.patch new file mode 100644 index 000000000..a655eb925 --- /dev/null +++ b/patch/kernel/meson64-dev/arm64-meson-g12-enable-support-for-SPIFC.patch @@ -0,0 +1,302 @@ +The Khadas VIM3 shares the eMMC pins 4 to 7 with the SPI NOR, in order +to enable the eMMC and the SPI NOR interface, we need to omit the +4 last pins from the eMMC pinctrl. + +As it was done for the Khadas VIM2, split the eMMC pinctrls in ctrl, data +and ds pins with either 4bits data or 8bits data, and update the current +board accordingly. + +Signed-off-by: Neil Armstrong +--- + .../boot/dts/amlogic/meson-g12-common.dtsi | 40 ++++++++++++++----- + .../boot/dts/amlogic/meson-g12a-sei510.dts | 2 +- + .../boot/dts/amlogic/meson-g12a-u200.dts | 2 +- + .../boot/dts/amlogic/meson-g12a-x96-max.dts | 2 +- + .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 2 +- + .../boot/dts/amlogic/meson-g12b-ugoos-am6.dts | 2 +- + .../boot/dts/amlogic/meson-khadas-vim3.dtsi | 2 +- + .../boot/dts/amlogic/meson-sm1-sei610.dts | 2 +- + 8 files changed, 37 insertions(+), 17 deletions(-) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +index 87b9a47a51b9..d09efb86ec33 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +@@ -295,17 +295,9 @@ + }; + }; + +- emmc_pins: emmc { ++ emmc_ctrl_pins: emmc-ctrl { + mux-0 { +- groups = "emmc_nand_d0", +- "emmc_nand_d1", +- "emmc_nand_d2", +- "emmc_nand_d3", +- "emmc_nand_d4", +- "emmc_nand_d5", +- "emmc_nand_d6", +- "emmc_nand_d7", +- "emmc_cmd"; ++ groups = "emmc_cmd"; + function = "emmc"; + bias-pull-up; + drive-strength-microamp = <4000>; +@@ -319,6 +311,34 @@ + }; + }; + ++ emmc_data_4b_pins: emmc-data-4b { ++ mux-0 { ++ groups = "emmc_nand_d0", ++ "emmc_nand_d1", ++ "emmc_nand_d2", ++ "emmc_nand_d3"; ++ function = "emmc"; ++ bias-pull-up; ++ drive-strength-microamp = <4000>; ++ }; ++ }; ++ ++ emmc_data_8b_pins: emmc-data-8b { ++ mux-0 { ++ groups = "emmc_nand_d0", ++ "emmc_nand_d1", ++ "emmc_nand_d2", ++ "emmc_nand_d3", ++ "emmc_nand_d4", ++ "emmc_nand_d5", ++ "emmc_nand_d6", ++ "emmc_nand_d7"; ++ function = "emmc"; ++ bias-pull-up; ++ drive-strength-microamp = <4000>; ++ }; ++ }; ++ + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_nand_ds"; +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +index 168f460e11fa..b00d0468c753 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +@@ -472,7 +472,7 @@ + /* eMMC */ + &sd_emmc_c { + status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +index 2a324f0136e3..a26bfe72550f 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +@@ -271,7 +271,7 @@ + /* eMMC */ + &sd_emmc_c { + status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +index 4f2596d82989..1b07c8c06eac 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +@@ -443,7 +443,7 @@ + /* eMMC */ + &sd_emmc_c { + status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +index 8830d3844885..b59ae1a297f2 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +@@ -435,7 +435,7 @@ + /* eMMC */ + &sd_emmc_c { + status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts +index ccd0bced01e8..325e448eb09c 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts +@@ -485,7 +485,7 @@ + /* eMMC */ + &sd_emmc_c { + status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + +diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +index 90815fa25ec6..b6f22a0bd318 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +@@ -312,7 +312,7 @@ + /* eMMC */ + &sd_emmc_c { + status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + +diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +index a8bb3fa9fec9..71cc730a4913 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +@@ -518,7 +518,7 @@ + /* eMMC */ + &sd_emmc_c { + status = "okay"; +- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + +Add the controller and pinctrl nodes to enable the SPI Flash Controller +on the Amlogic G12A and compatible SoCs. + +Signed-off-by: Neil Armstrong +--- + .../boot/dts/amlogic/meson-g12-common.dtsi | 20 +++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +index d09efb86ec33..56a9f8eadf01 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +@@ -593,6 +593,17 @@ + }; + }; + ++ nor_pins: nor { ++ mux { ++ groups = "nor_d", ++ "nor_q", ++ "nor_c", ++ "nor_cs"; ++ function = "nor"; ++ bias-disable; ++ }; ++ }; ++ + pdm_din0_a_pins: pdm-din0-a { + mux { + groups = "pdm_din0_a"; +@@ -2071,6 +2082,15 @@ + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + }; + ++ spifc: spi@14000 { ++ compatible = "amlogic,meson-gxbb-spifc"; ++ status = "disabled"; ++ reg = <0x0 0x14000 0x0 0x80>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&clkc CLKID_CLK81>; ++ }; ++ + pwm_ef: pwm@19000 { + compatible = "amlogic,meson-g12a-ee-pwm"; + reg = <0x0 0x19000 0x0 0x20>; + +Add disabled SPIFC controller node with instruction on how to enable +it while lowering capabilities of the eMMC controller from 8bits bus +width to 4bits bus width, it's data pins 4 to 7 being shared with +the SPI NOR controller pins. + +Signed-off-by: Neil Armstrong +--- + .../boot/dts/amlogic/meson-khadas-vim3.dtsi | 20 +++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +index b6f22a0bd318..f09854560938 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +@@ -328,6 +328,26 @@ + vqmmc-supply = <&emmc_1v8>; + }; + ++/* ++ * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS ++ * and eMMC Data 4 to 7 pins. ++ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, ++ * and change bus-width to 4 then spifc can be enabled. ++ */ ++&spifc { ++ status = "disabled"; ++ pinctrl-0 = <&nor_pins>; ++ pinctrl-names = "default"; ++ ++ w25q32: spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "winbond,w25q128fw", "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <104000000>; ++ }; ++}; ++ + &uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + +Add disabled SPIFC controller node with instruction on how to enable +it while lowering capabilities of the eMMC controller from 8bits bus +width to 4bits bus width, it's data pins 4 to 7 being shared with +the SPI NOR controller pins. + +Signed-off-by: Neil Armstrong +--- + .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 21 +++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +index b59ae1a297f2..169ea283d4ee 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +@@ -451,6 +451,27 @@ + vqmmc-supply = <&flash_1v8>; + }; + ++/* ++ * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins ++ * and eMMC Data 4 to 7 pins. ++ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, ++ * and change bus-width to 4 then spifc can be enabled. ++ * The SW1 slide should also be set to the correct position. ++ */ ++&spifc { ++ status = "disabled"; ++ pinctrl-0 = <&nor_pins>; ++ pinctrl-names = "default"; ++ ++ mx25u64: spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "mxicy,mx25u6435f", "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <104000000>; ++ }; ++}; ++ + &tdmif_b { + status = "okay"; + };