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Adding NanoPi Air and a few H3 fixes

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This commit is contained in:
ThomasKaiser 2016-08-25 12:46:07 +02:00
parent d00cf8a813
commit c82dadb119
9 changed files with 135 additions and 70 deletions
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11
config/boards/nanopiair.conf Normal file
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@ -0,0 +1,11 @@
# H3 quad core 256/512MB SoC Headless
BOARD_NAME="NanoPi Neo"
LINUXFAMILY=sun8i
BOOTCONFIG=FriendlyARM_NanoPi_NEO_defconfig
MODULES="#gpio-sunxi #w1-sunxi #w1-gpio #w1-therm #sunxi-cir hci_uart rfcomm hidp bcmdhd"
MODULES_NEXT="brcmfmac"
CPUMIN=240000
CPUMAX=912000
CLI_TARGET="jessie,xenial:default"
DESKTOP_TARGET=""
KERNEL_TARGET="default,dev"

2
config/boards/orangepilite.conf
View file

@ -3,7 +3,7 @@ BOARD_NAME="Orange Pi Lite"
LINUXFAMILY=sun8i
BOOTCONFIG=orangepi_one_defconfig
MODULES="8189fs #gpio_sunxi #w1-sunxi #w1-gpio #w1-therm #gc2035 #vfe_v4l2 sunxi-cir g_serial"
MODULES_NEXT=""
MODULES_NEXT="8189fs"
CPUMIN=480000
CPUMAX=1200000
CLI_TARGET="jessie:default"

2
config/boards/orangepipcplus.conf
View file

@ -3,7 +3,7 @@ BOARD_NAME="Orange Pi PC +"
LINUXFAMILY=sun8i
BOOTCONFIG=orangepi_pc_defconfig
MODULES="8189fs #gpio_sunxi #w1-sunxi #w1-gpio #w1-therm #gc2035 #vfe_v4l2 #sunxi-cir"
MODULES_NEXT=""
MODULES_NEXT="8189fs"
CPUMIN=480000
CPUMAX=1296000
CLI_TARGET="jessie:default"

2
config/boards/orangepiplus.conf
View file

@ -3,7 +3,7 @@ BOARD_NAME="Orange Pi+"
LINUXFAMILY=sun8i
BOOTCONFIG=orangepi_plus_defconfig
MODULES="8189es #gpio_sunxi #w1-sunxi #w1-gpio #w1-therm #gc2035 #vfe_v4l2 #sunxi-cir"
MODULES_NEXT=""
MODULES_NEXT="8189es"
CPUMIN=480000
CPUMAX=1296000
CLI_TARGET="jessie:default"

2
config/boards/orangepiplus2e.conf
View file

@ -3,7 +3,7 @@ BOARD_NAME="Orange Pi+ 2E"
LINUXFAMILY=sun8i
BOOTCONFIG=orangepi_pc_defconfig
MODULES="8189fs #gpio_sunxi #w1-sunxi #w1-gpio #w1-therm #gc2035 #vfe_v4l2 #sunxi-cir"
MODULES_NEXT=""
MODULES_NEXT="8189fs"
CPUMIN=480000
CPUMAX=1296000
CLI_TARGET="jessie:default"

44
patch/u-boot/u-boot-default/u-boot-98-tune-h3-dram-pll-to-improve-lock-time.patch Normal file
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@ -0,0 +1,44 @@
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d4dff1e..be9fcfd 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -116,7 +116,9 @@ struct sunxi_ccm_reg {
u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */
u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */
u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */
- u32 reserved21[13];
+ u32 reserved21[5];
+ u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */
+ u32 reserved21_5[7];
u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */
u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */
u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */
@@ -223,6 +225,11 @@ struct sunxi_ccm_reg {
#define CCM_PLL11_CTRL_UPD (0x1 << 30)
#define CCM_PLL11_CTRL_EN (0x1 << 31)
+#define CCM_PLL5_TUN_LOCK_TIME(x) (((x) & 0x7) << 24)
+#define CCM_PLL5_TUN_LOCK_TIME_MASK CCM_PLL5_TUN_LOCK_TIME(0x7)
+#define CCM_PLL5_TUN_INIT_FREQ(x) (((x) & 0x7f) << 16)
+#define CCM_PLL5_TUN_INIT_FREQ_MASK CCM_PLL5_TUN_INIT_FREQ(0x7f)
+
#if defined(CONFIG_MACH_SUN50I)
/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 15272c9..ed8cd9b 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -148,6 +148,12 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
const int max_n = 32;
int k = 1, m = 2;
+#ifdef CONFIG_MACH_SUN8I_H3
+ clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
+ CCM_PLL5_TUN_INIT_FREQ_MASK,
+ CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
+#endif
+
if (sigma_delta_enable)
writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);

49
patch/u-boot/u-boot-default/u-boot-99-add-missing-boards.patch
View file

@ -64,38 +64,6 @@ index 0000000..43562a2
+CONFIG_GPIO=y
+CONFIG_SYS_CLK_FREQ=816000000
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/configs/orangepi_h3_defconfig b/configs/orangepi_h3_defconfig
new file mode 100644
index 0000000..7f61c9a
--- /dev/null
+++ b/configs/orangepi_h3_defconfig
@@ -0,0 +1,26 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SY8106A_POWER=y
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_GPIO=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 7bade8f..d149431 100644
--- a/configs/orangepi_pc_defconfig
@ -108,18 +76,33 @@ index 7bade8f..d149431 100644
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_SY8106A_VOUT1_VOLT=1100
+CONFIG_SYS_CLK_FREQ=1008000000
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index be8afca..8d83174 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_H3=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN="PF6"
diff --git a/configs/FriendlyARM_NanoPi_NEO_defconfig b/configs/FriendlyARM_NanoPi_NEO_defconfig
new file mode 100644
index 0000000..83fae20
--- /dev/null
+++ b/configs/FriendlyARM_NanoPi_NEO_defconfig
@@ -0,0 +1,27 @@
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

44
patch/u-boot/u-boot-dev/u-boot-98-tune-h3-dram-pll-to-improve-lock-time.patch Normal file
View file

@ -0,0 +1,44 @@
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d4dff1e..be9fcfd 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -116,7 +116,9 @@ struct sunxi_ccm_reg {
u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */
u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */
u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */
- u32 reserved21[13];
+ u32 reserved21[5];
+ u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */
+ u32 reserved21_5[7];
u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */
u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */
u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */
@@ -223,6 +225,11 @@ struct sunxi_ccm_reg {
#define CCM_PLL11_CTRL_UPD (0x1 << 30)
#define CCM_PLL11_CTRL_EN (0x1 << 31)
+#define CCM_PLL5_TUN_LOCK_TIME(x) (((x) & 0x7) << 24)
+#define CCM_PLL5_TUN_LOCK_TIME_MASK CCM_PLL5_TUN_LOCK_TIME(0x7)
+#define CCM_PLL5_TUN_INIT_FREQ(x) (((x) & 0x7f) << 16)
+#define CCM_PLL5_TUN_INIT_FREQ_MASK CCM_PLL5_TUN_INIT_FREQ(0x7f)
+
#if defined(CONFIG_MACH_SUN50I)
/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 15272c9..ed8cd9b 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -148,6 +148,12 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
const int max_n = 32;
int k = 1, m = 2;
+#ifdef CONFIG_MACH_SUN8I_H3
+ clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
+ CCM_PLL5_TUN_INIT_FREQ_MASK,
+ CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
+#endif
+
if (sigma_delta_enable)
writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);

49
patch/u-boot/u-boot-dev/u-boot-99-add-missing-boards.patch
View file

@ -64,38 +64,6 @@ index 0000000..43562a2
+CONFIG_GPIO=y
+CONFIG_SYS_CLK_FREQ=816000000
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/configs/orangepi_h3_defconfig b/configs/orangepi_h3_defconfig
new file mode 100644
index 0000000..7f61c9a
--- /dev/null
+++ b/configs/orangepi_h3_defconfig
@@ -0,0 +1,26 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SY8106A_POWER=y
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_GPIO=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 7bade8f..d149431 100644
--- a/configs/orangepi_pc_defconfig
@ -108,18 +76,33 @@ index 7bade8f..d149431 100644
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_SY8106A_VOUT1_VOLT=1320
+CONFIG_SYS_CLK_FREQ=1296000000
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index be8afca..8d83174 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_H3=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN="PF6"
diff --git a/configs/FriendlyARM_NanoPi_NEO_defconfig b/configs/FriendlyARM_NanoPi_NEO_defconfig
new file mode 100644
index 0000000..83fae20
--- /dev/null
+++ b/configs/FriendlyARM_NanoPi_NEO_defconfig
@@ -0,0 +1,27 @@
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set