diff --git a/config/kernel/linux-sunxi-next.config b/config/kernel/linux-sunxi-next.config index b3ccdf585..073ad9121 100644 --- a/config/kernel/linux-sunxi-next.config +++ b/config/kernel/linux-sunxi-next.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 4.17.14 Kernel Configuration +# Linux/arm 4.17.15 Kernel Configuration # CONFIG_ARM=y CONFIG_ARM_HAS_SG_CHAIN=y diff --git a/config/kernel/linux-sunxi64-next.config b/config/kernel/linux-sunxi64-next.config index e5d1f603d..4fc31ad97 100644 --- a/config/kernel/linux-sunxi64-next.config +++ b/config/kernel/linux-sunxi64-next.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 4.17.14 Kernel Configuration +# Linux/arm64 4.17.15 Kernel Configuration # CONFIG_ARM64=y CONFIG_64BIT=y diff --git a/patch/kernel/sunxi-next/board-a83t-1-5-clk-sunxi-ng-Add-maximum-rate-constraint-to-NM-PLLs.patch b/patch/kernel/sunxi-next/board-a83t-1-5-clk-sunxi-ng-Add-maximum-rate-constraint-to-NM-PLLs.patch new file mode 100644 index 000000000..d7e7b6a1a --- /dev/null +++ b/patch/kernel/sunxi-next/board-a83t-1-5-clk-sunxi-ng-Add-maximum-rate-constraint-to-NM-PLLs.patch @@ -0,0 +1,66 @@ +diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c +index 4e2073307f34..6fe3c14f7b2d 100644 +--- a/drivers/clk/sunxi-ng/ccu_nm.c ++++ b/drivers/clk/sunxi-ng/ccu_nm.c +@@ -124,6 +124,13 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate, + return rate; + } + ++ if (nm->max_rate && rate > nm->max_rate) { ++ rate = nm->max_rate; ++ if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) ++ rate /= nm->fixed_post_div; ++ return rate; ++ } ++ + if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) { + if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) + rate /= nm->fixed_post_div; +diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h +index 1d8b459c50b7..de232f2199a6 100644 +--- a/drivers/clk/sunxi-ng/ccu_nm.h ++++ b/drivers/clk/sunxi-ng/ccu_nm.h +@@ -38,6 +38,7 @@ struct ccu_nm { + + unsigned int fixed_post_div; + unsigned int min_rate; ++ unsigned int max_rate; + + struct ccu_common common; + }; +@@ -115,6 +116,35 @@ struct ccu_nm { + }, \ + } + ++#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \ ++ _parent, _reg, \ ++ _min_rate, _max_rate, \ ++ _nshift, _nwidth, \ ++ _mshift, _mwidth, \ ++ _frac_en, _frac_sel, \ ++ _frac_rate_0, \ ++ _frac_rate_1, \ ++ _gate, _lock, _flags) \ ++ struct ccu_nm _struct = { \ ++ .enable = _gate, \ ++ .lock = _lock, \ ++ .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ ++ .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ ++ .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \ ++ _frac_rate_0, \ ++ _frac_rate_1), \ ++ .min_rate = _min_rate, \ ++ .max_rate = _max_rate, \ ++ .common = { \ ++ .reg = _reg, \ ++ .features = CCU_FEATURE_FRACTIONAL, \ ++ .hw.init = CLK_HW_INIT(_name, \ ++ _parent, \ ++ &ccu_nm_ops, \ ++ _flags), \ ++ }, \ ++ } ++ + #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ + _nshift, _nwidth, \ + _mshift, _mwidth, \ diff --git a/patch/kernel/sunxi-next/board-a83t-2-5-clk-sunxi-ng-h3-h5-Add-max.-rate-constraint-to-pll-video.patch b/patch/kernel/sunxi-next/board-a83t-2-5-clk-sunxi-ng-h3-h5-Add-max.-rate-constraint-to-pll-video.patch new file mode 100644 index 000000000..686fcda44 --- /dev/null +++ b/patch/kernel/sunxi-next/board-a83t-2-5-clk-sunxi-ng-h3-h5-Add-max.-rate-constraint-to-pll-video.patch @@ -0,0 +1,36 @@ +diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +index 77ed0b0ba681..eb5c608428fa 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c ++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +@@ -69,18 +69,19 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video_clk, "pll-video", +- "osc24M", 0x0010, +- 192000000, /* Minimum rate */ +- 8, 7, /* N */ +- 0, 4, /* M */ +- BIT(24), /* frac enable */ +- BIT(25), /* frac select */ +- 270000000, /* frac rate 0 */ +- 297000000, /* frac rate 1 */ +- BIT(31), /* gate */ +- BIT(28), /* lock */ +- CLK_SET_RATE_UNGATE); ++static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video_clk, "pll-video", ++ "osc24M", 0x0010, ++ 192000000, /* Minimum rate */ ++ 912000000, /* Maximum rate */ ++ 8, 7, /* N */ ++ 0, 4, /* M */ ++ BIT(24), /* frac enable */ ++ BIT(25), /* frac select */ ++ 270000000, /* frac rate 0 */ ++ 297000000, /* frac rate 1 */ ++ BIT(31), /* gate */ ++ BIT(28), /* lock */ ++ CLK_SET_RATE_UNGATE); + + static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", + "osc24M", 0x0018, diff --git a/patch/kernel/sunxi-next/board-a83t-3-5-clk-sunxi-ng-r40-Add-max.-rate-constraint-to-video-PLLs.patch b/patch/kernel/sunxi-next/board-a83t-3-5-clk-sunxi-ng-r40-Add-max.-rate-constraint-to-video-PLLs.patch new file mode 100644 index 000000000..2612555b6 --- /dev/null +++ b/patch/kernel/sunxi-next/board-a83t-3-5-clk-sunxi-ng-r40-Add-max.-rate-constraint-to-video-PLLs.patch @@ -0,0 +1,70 @@ +diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c +index 0f388f6944d5..582ebd41d20d 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c ++++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c +@@ -65,19 +65,19 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +-/* TODO: The result of N/M is required to be in [8, 25] range. */ +-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0", +- "osc24M", 0x0010, +- 192000000, /* Minimum rate */ +- 8, 7, /* N */ +- 0, 4, /* M */ +- BIT(24), /* frac enable */ +- BIT(25), /* frac select */ +- 270000000, /* frac rate 0 */ +- 297000000, /* frac rate 1 */ +- BIT(31), /* gate */ +- BIT(28), /* lock */ +- CLK_SET_RATE_UNGATE); ++static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0", ++ "osc24M", 0x0010, ++ 192000000, /* Minimum rate */ ++ 1008000000, /* Maximum rate */ ++ 8, 7, /* N */ ++ 0, 4, /* M */ ++ BIT(24), /* frac enable */ ++ BIT(25), /* frac select */ ++ 270000000, /* frac rate 0 */ ++ 297000000, /* frac rate 1 */ ++ BIT(31), /* gate */ ++ BIT(28), /* lock */ ++ CLK_SET_RATE_UNGATE); + + /* TODO: The result of N/M is required to be in [8, 25] range. */ + static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", +@@ -152,19 +152,19 @@ static struct ccu_nk pll_periph1_clk = { + }, + }; + +-/* TODO: The result of N/M is required to be in [8, 25] range. */ +-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1", +- "osc24M", 0x030, +- 192000000, /* Minimum rate */ +- 8, 7, /* N */ +- 0, 4, /* M */ +- BIT(24), /* frac enable */ +- BIT(25), /* frac select */ +- 270000000, /* frac rate 0 */ +- 297000000, /* frac rate 1 */ +- BIT(31), /* gate */ +- BIT(28), /* lock */ +- CLK_SET_RATE_UNGATE); ++static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1", ++ "osc24M", 0x030, ++ 192000000, /* Minimum rate */ ++ 1008000000, /* Maximum rate */ ++ 8, 7, /* N */ ++ 0, 4, /* M */ ++ BIT(24), /* frac enable */ ++ BIT(25), /* frac select */ ++ 270000000, /* frac rate 0 */ ++ 297000000, /* frac rate 1 */ ++ BIT(31), /* gate */ ++ BIT(28), /* lock */ ++ CLK_SET_RATE_UNGATE); + + static struct ccu_nkm pll_sata_clk = { + .enable = BIT(31), diff --git a/patch/kernel/sunxi-next/board-a83t-4-5-clk-sunxi-ng-nkmp-Add-constraint-for-maximum-rate.patch b/patch/kernel/sunxi-next/board-a83t-4-5-clk-sunxi-ng-nkmp-Add-constraint-for-maximum-rate.patch new file mode 100644 index 000000000..c7b429a33 --- /dev/null +++ b/patch/kernel/sunxi-next/board-a83t-4-5-clk-sunxi-ng-nkmp-Add-constraint-for-maximum-rate.patch @@ -0,0 +1,30 @@ +diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c +index ebd9436d2c7c..9b49adb20d07 100644 +--- a/drivers/clk/sunxi-ng/ccu_nkmp.c ++++ b/drivers/clk/sunxi-ng/ccu_nkmp.c +@@ -137,6 +137,13 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate, + if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV) + rate *= nkmp->fixed_post_div; + ++ if (nkmp->max_rate && rate > nkmp->max_rate) { ++ rate = nkmp->max_rate; ++ if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV) ++ rate /= nkmp->fixed_post_div; ++ return rate; ++ } ++ + _nkmp.min_n = nkmp->n.min ?: 1; + _nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width; + _nkmp.min_k = nkmp->k.min ?: 1; +diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.h b/drivers/clk/sunxi-ng/ccu_nkmp.h +index 6940503e7fc4..a9f8c116a745 100644 +--- a/drivers/clk/sunxi-ng/ccu_nkmp.h ++++ b/drivers/clk/sunxi-ng/ccu_nkmp.h +@@ -35,6 +35,7 @@ struct ccu_nkmp { + struct ccu_div_internal p; + + unsigned int fixed_post_div; ++ unsigned int max_rate; + + struct ccu_common common; + }; diff --git a/patch/kernel/sunxi-next/board-a83t-5-5-clk-sunxi-ng-a83t-Add-max.-rate-constraint-to-video-PLLs.patch b/patch/kernel/sunxi-next/board-a83t-5-5-clk-sunxi-ng-a83t-Add-max.-rate-constraint-to-video-PLLs.patch new file mode 100644 index 000000000..faf48a4ce --- /dev/null +++ b/patch/kernel/sunxi-next/board-a83t-5-5-clk-sunxi-ng-a83t-Add-max.-rate-constraint-to-video-PLLs.patch @@ -0,0 +1,20 @@ +diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +index 7d08015b980d..2d6555d73170 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c ++++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +@@ -108,6 +108,7 @@ static struct ccu_nkmp pll_video0_clk = { + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), + .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ + .p = _SUNXI_CCU_DIV(0, 2), /* output divider */ ++ .max_rate = 3000000000UL, + .common = { + .reg = 0x010, + .lock_reg = CCU_SUN8I_A83T_LOCK_REG, +@@ -220,6 +221,7 @@ static struct ccu_nkmp pll_video1_clk = { + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), + .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ + .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */ ++ .max_rate = 3000000000UL, + .common = { + .reg = 0x04c, + .lock_reg = CCU_SUN8I_A83T_LOCK_REG, diff --git a/patch/kernel/sunxi-next/board-h6-clk-sunxi-ng-fix-H6-bus-clocks-divider-position.patch b/patch/kernel/sunxi-next/board-h6-clk-sunxi-ng-fix-H6-bus-clocks-divider-position.patch new file mode 100644 index 000000000..b2c882d83 --- /dev/null +++ b/patch/kernel/sunxi-next/board-h6-clk-sunxi-ng-fix-H6-bus-clocks-divider-position.patch @@ -0,0 +1,36 @@ +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index bdbfe78fe133..0f7a0ffd3f70 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -224,7 +224,7 @@ static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2", + psi_ahb1_ahb2_parents, + 0x510, + 0, 5, /* M */ +- 16, 2, /* P */ ++ 8, 2, /* P */ + 24, 2, /* mux */ + 0); + +@@ -233,19 +233,19 @@ static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k", + "pll-periph0" }; + static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c, + 0, 5, /* M */ +- 16, 2, /* P */ ++ 8, 2, /* P */ + 24, 2, /* mux */ + 0); + + static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520, + 0, 5, /* M */ +- 16, 2, /* P */ ++ 8, 2, /* P */ + 24, 2, /* mux */ + 0); + + static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524, + 0, 5, /* M */ +- 16, 2, /* P */ ++ 8, 2, /* P */ + 24, 2, /* mux */ + 0); +