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Move sunxi/64 current to 5.7, legacy to 5.4 (#2098)
* Move sunxi/64 current to 5.7, legacy to 5.4 * Update sunxidev config
This commit is contained in:
Igor Pečovnik
GitHub
parent
812245def3
commit
caa47bad65
430 changed files with 20432 additions and 75488 deletions
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@ -0,0 +1,18 @@
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diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
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index 1413828..efc9bfd 100644
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -935,6 +935,13 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
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{ "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
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+ /* BergMicro Flashes */
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+ { "bg25q80", INFO(0xe04014, 0, 64 * 1024, 16, SECT_4K) },
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+ { "bg25q16", INFO(0xe04015, 0, 64 * 1024, 32, SECT_4K) },
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+ { "bg25q32", INFO(0xe04016, 0, 64 * 1024, 64, SECT_4K) },
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+ { "bg25q64", INFO(0xe04017, 0, 64 * 1024, 128, SECT_4K) },
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+ { "bg25q128", INFO(0xe04018, 0, 64 * 1024, 256, SECT_4K) },
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+
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/* EON -- en25xxx */
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{ "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
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{ "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
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7138
patch/kernel/sunxi-current/check/general-sunxi-overlays.patch
Normal file
7138
patch/kernel/sunxi-current/check/general-sunxi-overlays.patch
Normal file
File diff suppressed because it is too large
Load diff
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@ -0,0 +1,200 @@
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diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
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index 2334e0548..66c23cff2 100644
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--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
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+++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
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@@ -14,6 +14,10 @@ dtbo-$(CONFIG_ARCH_SUNXI) += \
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sun50i-a64-w1-gpio.dtbo \
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sun50i-h5-analog-codec.dtbo \
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sun50i-h5-cir.dtbo \
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+ sun50i-h5-cpu-clock-1.0GHz-1.1v.dtbo \
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+ sun50i-h5-cpu-clock-1.2GHz-1.3v.dtbo \
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+ sun50i-h5-cpu-clock-1.3GHz-1.3v.dtbo \
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+ sun50i-h5-gpio-regulator-1.3v.dtbo \
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sun50i-h5-i2c0.dtbo \
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sun50i-h5-i2c1.dtbo \
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sun50i-h5-i2c2.dtbo \
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diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dts
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new file mode 100644
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index 000000000..a8079e825
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dts
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@@ -0,0 +1,31 @@
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+// DT overlay for CPU frequency operating points to up to 1.0GHz at a maximum CPU voltage of 1.1v
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+
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ fragment@0 {
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+ target = <&cpu0_opp_table>;
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+
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+ __overlay__ {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ // in order to match the H5 DT cooling-maps, update the existing OP table in-place
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+ // with the new voltages
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+
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+ opp-960000000 {
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+ opp-hz = /bits/ 64 <960000000>;
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+ opp-microvolt = <1100000 1100000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <1100000 1100000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+ };
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+};
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+
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diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dts
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new file mode 100644
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index 000000000..81fd378b9
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dts
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@@ -0,0 +1,31 @@
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+// DT overlay for CPU frequency operating points to up to 1.2GHz at a maximum CPU voltage of 1.3v
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+
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ fragment@0 {
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+ target = <&cpu0_opp_table>;
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+
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+ __overlay__ {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ // in order to match the H5 DT cooling-maps, update the existing OP table in-place
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+ // with the new voltages
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+
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+ opp-1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+ };
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+};
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+
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diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dts
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new file mode 100644
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index 000000000..ed0d9ac63
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dts
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@@ -0,0 +1,61 @@
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+// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v
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+
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ fragment@0 {
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+ target = <&cpu0_opp_table>;
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+
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+ __overlay__ {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ // in order to match the H5 DT cooling-maps, update the existing OP table in-place
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+ // with the new voltages
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+
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+ opp-1056000000 {
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+ opp-hz = /bits/ 64 <1056000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1152000000 {
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+ opp-hz = /bits/ 64 <1152000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1224000000 {
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+ opp-hz = /bits/ 64 <1224000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1248000000 {
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+ opp-hz = /bits/ 64 <1248000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1296000000 {
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+ opp-hz = /bits/ 64 <1296000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+ };
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+};
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+
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diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dts
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new file mode 100644
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index 000000000..8d2755c3d
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dts
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@@ -0,0 +1,38 @@
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ compatible = "allwinner,sun50i-h5";
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+
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+ fragment@0 {
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+ target-path = "/";
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+
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+ __overlay__ {
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+ reg_vdd_cpux: gpio-regulator {
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+ compatible = "regulator-gpio";
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+ regulator-name = "vdd-cpux";
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+ regulator-type = "voltage";
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+ regulator-boot-on;
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+ regulator-always-on;
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+ regulator-min-microvolt = <1100000>;
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+ regulator-max-microvolt = <1300000>;
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+ regulator-ramp-delay = <50>; /* 4ms */
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+
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+ gpios = <&r_pio 0 6 0>; /* PL6 */
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+ enable-active-high;
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+ gpios-states = <0x1>;
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+ states = <1100000 0x0
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+ 1300000 0x1>;
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+ };
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&cpu0>;
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+
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+ __overlay__ {
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+ cpu-supply = <®_vdd_cpux>;
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+ };
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+ };
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+};
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+
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@ -0,0 +1,111 @@
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diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
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index fbd2daaa4..7f55788e8 100644
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--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
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+++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
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@@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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dtbo-$(CONFIG_ARCH_SUNXI) += \
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+ sun50i-a64-boe-hb140wx1-501.dtbo \
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sun50i-a64-i2c0.dtbo \
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sun50i-a64-i2c1.dtbo \
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sun50i-a64-pps-gpio.dtbo \
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diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
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index cd9dbc686..672ebd5bd 100644
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--- a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
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+++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
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@@ -18,6 +18,7 @@ on supported boards, so this controller is not supported in provided overlays
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### Provided overlays:
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+- boe-hb140wx1-501
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- i2c0
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- i2c1
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- pps-gpio
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@@ -32,6 +33,10 @@ on supported boards, so this controller is not supported in provided overlays
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### Overlay details:
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+### boe-hb140wx1-501
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+
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+Provides EDID for BOE HB140WX1-501 LCD panel for early 14" pinebook models.
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+
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### i2c0
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Activates TWI/I2C bus 0
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diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-boe-hb140wx1-501.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-boe-hb140wx1-501.dts
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new file mode 100644
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index 000000000..217a1290d
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-boe-hb140wx1-501.dts
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@@ -0,0 +1,71 @@
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ fragment {
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+ target = <&anx6345>;
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+ __overlay__ {
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+ edid = [
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+ /* Header */
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+ 00 ff ff ff ff ff ff 00
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+ /* ID Manufacturer Name */
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+ 09 e5
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+ /* ID Product Code */
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+ 37 00
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+ /* 32-bit serial No. */
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+ 00 00 00 00
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+ /* Week of manufacture */
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+ 01
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+ /* Year of manufacture */
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+ 16
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+ /* EDID Structure Ver. */
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+ 01
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+ /* EDID revision # */
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+ 04
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+ /* Video input definition */
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+ 80
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+ /* Max H image size */
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+ 1f
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+ /* Max V image size */
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+ 11
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+ /* Display Gamma */
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+ 78
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+ /* Feature support */
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+ 0a
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+ /* Color bits */
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+ b0 90 97 58 54 92 26 1d 50 54
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+ /* Established timings */
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+ 00 00 00
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+ /* Standard timings */
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+ 01 01
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+ 01 01
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+ 01 01
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+ 01 01
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+ 01 01
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+ 01 01
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+ 01 01
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+ 01 01
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+ /* Detailed timing/monitor descriptor #1 */
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+ 3e 1c 56 a0 50 00 16 30
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+ 30 20 36 00 35 ad 10 00
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+ 00 1a
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+ /* Detailed timing/monitor descriptor #2 */
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+ 3e 1c 56 a0 50 00 16 30
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+ 30 20 36 00 35 ad 10 00
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+ 00 1a
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+ /* Detailed timing/monitor descriptor #3 */
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+ 00 00 00 fe 00 42 4f 45
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+ 20 48 46 0a 20 20 20 20
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+ 20 20
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+ /* Detailed timing/monitor descriptor #4 */
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+ 00 00 00 fe 00 48 42 31
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+ 34 30 57 58 31 2d 35 30
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+ 31 0a
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+ /* Extension flag */
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+ 00
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+ /* Checksum */
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+ 81
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+ ];
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+ };
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+ };
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+};
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