Move Mvebu64 / Espressobin dev kernel to 5.4.y (#1635)

* Espressobin (mvebu64) moving to 5.4.y

config/boards/espressobin.conf

@@ -3,4 +3,4 @@ BOARD_NAME="Espressobin"
 BOARDFAMILY="mvebu64"
 BOOTCONFIG="mvebu_espressobin-88f3720_defconfig"
 BUILD_DESKTOP="no"
-KERNEL_TARGET="legacy,current"
+KERNEL_TARGET="legacy,current,dev"

config/kernel/linux-mvebu64-current.config

@@ -1 +0,0 @@
-linux-mvebu64-next.config

config/kernel/linux-mvebu64-dev.config

@@ -1,16 +1,17 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 5.3.1 Kernel Configuration
+# Linux/arm64 5.4.0 Kernel Configuration
 #
 
 #
-# Compiler: aarch64-linux-gnu-gcc (Linaro GCC 7.4-2019.02) 7.4.1 20181213 [linaro-7.4-2019.02 revision 56ec6f6b99cc167ff0c2f8e1a2eed33b1edc85d4]
+# Compiler: aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0
 #
 CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=70401
+CONFIG_GCC_VERSION=80300
 CONFIG_CLANG_VERSION=0
 CONFIG_CC_CAN_LINK=y
 CONFIG_CC_HAS_ASM_GOTO=y
+CONFIG_CC_HAS_ASM_INLINE=y
 CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y
 CONFIG_IRQ_WORK=y
 CONFIG_BUILDTIME_EXTABLE_SORT=y
@@ -329,6 +330,7 @@ CONFIG_CAVIUM_ERRATUM_23144=y
 CONFIG_CAVIUM_ERRATUM_23154=y
 CONFIG_CAVIUM_ERRATUM_27456=y
 CONFIG_CAVIUM_ERRATUM_30115=y
+CONFIG_CAVIUM_TX2_ERRATUM_219=y
 CONFIG_QCOM_FALKOR_ERRATUM_1003=y
 CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
 CONFIG_QCOM_FALKOR_ERRATUM_1009=y
@@ -389,6 +391,7 @@ CONFIG_HARDEN_EL2_VECTORS=y
 CONFIG_ARM64_SSBD=y
 CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
 # CONFIG_ARM64_SW_TTBR0_PAN is not set
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
 CONFIG_COMPAT=y
 CONFIG_KUSER_HELPERS=y
 # CONFIG_ARMV8_DEPRECATED is not set
@@ -482,6 +485,7 @@ CONFIG_DT_IDLE_STATES=y
 # ARM CPU Idle Drivers
 #
 CONFIG_ARM_CPUIDLE=y
+# CONFIG_ARM_PSCI_CPUIDLE is not set
 # end of ARM CPU Idle Drivers
 # end of CPU Idle
 
@@ -529,6 +533,7 @@ CONFIG_DMIID=y
 # CONFIG_DMI_SYSFS is not set
 # CONFIG_ISCSI_IBFT is not set
 # CONFIG_FW_CFG_SYSFS is not set
+# CONFIG_TURRIS_MOX_RWTM is not set
 CONFIG_HAVE_ARM_SMCCC=y
 CONFIG_ARM_PSCI_FW=y
 # CONFIG_ARM_PSCI_CHECKER is not set
@@ -646,6 +651,7 @@ CONFIG_JUMP_LABEL=y
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
 CONFIG_HAVE_NMI=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
 CONFIG_HAVE_DMA_CONTIGUOUS=y
@@ -656,6 +662,7 @@ CONFIG_ARCH_HAS_KEEPINITRD=y
 CONFIG_ARCH_HAS_SET_MEMORY=y
 CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
 CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
 CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
 CONFIG_HAVE_RSEQ=y
 CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
@@ -690,6 +697,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
 CONFIG_ARCH_MMAP_RND_BITS=18
 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_OLD_SIGSUSPEND3=y
 CONFIG_COMPAT_OLD_SIGACTION=y
@@ -727,6 +735,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 # CONFIG_MODULE_SIG is not set
 # CONFIG_MODULE_COMPRESS is not set
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_TRIM_UNUSED_KSYMS is not set
 CONFIG_MODULES_TREE_LOOKUP=y
 CONFIG_BLOCK=y
@@ -740,6 +750,7 @@ CONFIG_BLK_DEV_THROTTLING=y
 CONFIG_BLK_CMDLINE_PARSER=y
 # CONFIG_BLK_WBT is not set
 # CONFIG_BLK_CGROUP_IOLATENCY is not set
+# CONFIG_BLK_CGROUP_IOCOST is not set
 CONFIG_BLK_DEBUG_FS=y
 # CONFIG_BLK_SED_OPAL is not set
 
@@ -844,6 +855,7 @@ CONFIG_ARCH_HAS_PTE_DEVMAP=y
 CONFIG_FRAME_VECTOR=y
 # CONFIG_PERCPU_STATS is not set
 # CONFIG_GUP_BENCHMARK is not set
+# CONFIG_READ_ONLY_THP_FOR_FS is not set
 CONFIG_ARCH_HAS_PTE_SPECIAL=y
 # end of Memory Management options
 
@@ -1386,9 +1398,7 @@ CONFIG_NET_DSA_TAG_GSWIP=m
 CONFIG_NET_DSA_TAG_DSA=m
 CONFIG_NET_DSA_TAG_EDSA=m
 CONFIG_NET_DSA_TAG_MTK=m
-CONFIG_NET_DSA_TAG_KSZ_COMMON=m
 CONFIG_NET_DSA_TAG_KSZ=m
-CONFIG_NET_DSA_TAG_KSZ9477=m
 CONFIG_NET_DSA_TAG_QCA=m
 CONFIG_NET_DSA_TAG_LAN9303=m
 CONFIG_NET_DSA_TAG_SJA1105=m
@@ -1514,6 +1524,7 @@ CONFIG_NET_ACT_CONNMARK=m
 # CONFIG_NET_ACT_IFE is not set
 # CONFIG_NET_ACT_TUNNEL_KEY is not set
 # CONFIG_NET_ACT_CT is not set
+# CONFIG_NET_TC_SKB_EXT is not set
 CONFIG_NET_SCH_FIFO=y
 CONFIG_DCB=y
 CONFIG_DNS_RESOLVER=y
@@ -1566,6 +1577,7 @@ CONFIG_CAN=m
 CONFIG_CAN_RAW=m
 CONFIG_CAN_BCM=m
 CONFIG_CAN_GW=m
+CONFIG_CAN_J1939=m
 
 #
 # CAN Device Drivers
@@ -1577,6 +1589,7 @@ CONFIG_CAN_DEV=m
 CONFIG_CAN_CALC_BITTIMING=y
 CONFIG_CAN_FLEXCAN=m
 CONFIG_CAN_GRCAN=m
+CONFIG_CAN_KVASER_PCIEFD=m
 CONFIG_CAN_XILINXCAN=m
 CONFIG_CAN_C_CAN=m
 CONFIG_CAN_C_CAN_PLATFORM=m
@@ -1586,15 +1599,18 @@ CONFIG_CAN_CC770_ISA=m
 CONFIG_CAN_CC770_PLATFORM=m
 # CONFIG_CAN_IFI_CANFD is not set
 CONFIG_CAN_M_CAN=m
+CONFIG_CAN_M_CAN_PLATFORM=m
+CONFIG_CAN_M_CAN_TCAN4X5X=m
 CONFIG_CAN_PEAK_PCIEFD=m
 CONFIG_CAN_SJA1000=m
-CONFIG_CAN_SJA1000_ISA=m
-CONFIG_CAN_SJA1000_PLATFORM=m
 CONFIG_CAN_EMS_PCI=m
+CONFIG_CAN_F81601=m
+CONFIG_CAN_KVASER_PCI=m
 CONFIG_CAN_PEAK_PCI=m
 CONFIG_CAN_PEAK_PCIEC=y
-CONFIG_CAN_KVASER_PCI=m
 CONFIG_CAN_PLX_PCI=m
+CONFIG_CAN_SJA1000_ISA=m
+CONFIG_CAN_SJA1000_PLATFORM=m
 CONFIG_CAN_SOFTING=m
 
 #
@@ -1834,6 +1850,7 @@ CONFIG_PCI_HOST_GENERIC=y
 # CONFIG_PCIE_ARMADA_8K is not set
 # CONFIG_PCIE_KIRIN is not set
 # CONFIG_PCI_MESON is not set
+# CONFIG_PCIE_AL is not set
 # end of DesignWare PCI Core Support
 # end of PCI controller drivers
 
@@ -1896,6 +1913,7 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y
 #
 CONFIG_ARM_CCI=y
 # CONFIG_BRCMSTB_GISB_ARB is not set
+# CONFIG_MOXTET is not set
 # CONFIG_SIMPLE_PM_BUS is not set
 CONFIG_VEXPRESS_CONFIG=y
 # end of Bus devices
@@ -1904,13 +1922,13 @@ CONFIG_VEXPRESS_CONFIG=y
 # CONFIG_GNSS is not set
 CONFIG_MTD=y
 # CONFIG_MTD_TESTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_OF_PARTS=y
-# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # Partition parsers
 #
+# CONFIG_MTD_AR7_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # end of Partition parsers
@@ -1958,7 +1976,6 @@ CONFIG_MTD_CFI_I2=y
 #
 # CONFIG_MTD_PMC551 is not set
 # CONFIG_MTD_DATAFLASH is not set
-CONFIG_MTD_M25P80=y
 # CONFIG_MTD_MCHP23K256 is not set
 # CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
@@ -1987,6 +2004,7 @@ CONFIG_MTD_RAW_NAND=m
 # CONFIG_MTD_NAND_CAFE is not set
 CONFIG_MTD_NAND_MARVELL=m
 # CONFIG_MTD_NAND_BRCMNAND is not set
+CONFIG_MTD_NAND_MXIC=m
 # CONFIG_MTD_NAND_GPIO is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 
@@ -2048,6 +2066,7 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
 CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_DRBD=m
+# CONFIG_DRBD_FAULT_INJECTION is not set
 CONFIG_BLK_DEV_NBD=m
 # CONFIG_BLK_DEV_SKD is not set
 # CONFIG_BLK_DEV_SX8 is not set
@@ -2081,7 +2100,6 @@ CONFIG_NVME_TCP=m
 # CONFIG_AD525X_DPOT is not set
 # CONFIG_DUMMY_IRQ is not set
 # CONFIG_PHANTOM is not set
-# CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
 # CONFIG_ICS932S401 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -2389,6 +2407,7 @@ CONFIG_DM_CACHE=m
 CONFIG_DM_CACHE_SMQ=m
 CONFIG_DM_WRITECACHE=m
 # CONFIG_DM_ERA is not set
+CONFIG_DM_CLONE=m
 CONFIG_DM_MIRROR=m
 # CONFIG_DM_LOG_USERSPACE is not set
 CONFIG_DM_RAID=m
@@ -2465,12 +2484,16 @@ CONFIG_NET_DSA_LOOP=m
 # CONFIG_NET_DSA_LANTIQ_GSWIP is not set
 CONFIG_NET_DSA_MT7530=m
 # CONFIG_NET_DSA_MV88E6060 is not set
+CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
 # CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set
+CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
+CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
 CONFIG_NET_DSA_MV88E6XXX=m
 CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
 # CONFIG_NET_DSA_MV88E6XXX_PTP is not set
 CONFIG_NET_DSA_SJA1105=m
 # CONFIG_NET_DSA_SJA1105_PTP is not set
+# CONFIG_NET_DSA_SJA1105_TAS is not set
 # CONFIG_NET_DSA_QCA8K is not set
 CONFIG_NET_DSA_REALTEK_SMI=m
 CONFIG_NET_DSA_SMSC_LAN9303=m
@@ -2630,10 +2653,11 @@ CONFIG_NET_VENDOR_OKI=y
 CONFIG_NET_VENDOR_PACKET_ENGINES=y
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
+CONFIG_NET_VENDOR_PENSANDO=y
+CONFIG_IONIC=m
 CONFIG_NET_VENDOR_QLOGIC=y
 # CONFIG_QLA3XXX is not set
 # CONFIG_QLCNIC is not set
-# CONFIG_QLGE is not set
 # CONFIG_NETXEN_NIC is not set
 # CONFIG_QED is not set
 CONFIG_NET_VENDOR_QUALCOMM=y
@@ -2716,6 +2740,7 @@ CONFIG_SWPHY=y
 # MII PHY device drivers
 #
 # CONFIG_SFP is not set
+CONFIG_ADIN_PHY=m
 # CONFIG_AMD_PHY is not set
 # CONFIG_AQUANTIA_PHY is not set
 CONFIG_AX88796B_PHY=m
@@ -2842,6 +2867,7 @@ CONFIG_ATH9K_WOW=y
 CONFIG_ATH9K_RFKILL=y
 CONFIG_ATH9K_CHANNEL_CONTEXT=y
 CONFIG_ATH9K_PCOEM=y
+CONFIG_ATH9K_PCI_NO_EEPROM=m
 CONFIG_ATH9K_HTC=m
 # CONFIG_ATH9K_HTC_DEBUGFS is not set
 # CONFIG_ATH9K_HWRNG is not set
@@ -2942,7 +2968,6 @@ CONFIG_IWLDVM=m
 CONFIG_IWLMVM=m
 CONFIG_IWLWIFI_OPMODE_MODULAR=y
 CONFIG_IWLWIFI_BCAST_FILTERING=y
-# CONFIG_IWLWIFI_PCIE_RTPM is not set
 
 #
 # Debugging Options
@@ -3232,10 +3257,10 @@ CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 # CONFIG_SERIAL_8250_EXTENDED is not set
 CONFIG_SERIAL_8250_ASPEED_VUART=m
+CONFIG_SERIAL_8250_DWLIB=y
 CONFIG_SERIAL_8250_FSL=y
 CONFIG_SERIAL_8250_DW=y
 # CONFIG_SERIAL_8250_RT288X is not set
-# CONFIG_SERIAL_8250_MOXA is not set
 CONFIG_SERIAL_OF_PLATFORM=y
 
 #
@@ -3262,6 +3287,7 @@ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
 # CONFIG_SERIAL_ARC is not set
 # CONFIG_SERIAL_RP2 is not set
 # CONFIG_SERIAL_FSL_LPUART is not set
+CONFIG_SERIAL_FSL_LINFLEXUART=m
 # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
 CONFIG_SERIAL_MVEBU_UART=y
 CONFIG_SERIAL_MVEBU_CONSOLE=y
@@ -3292,6 +3318,8 @@ CONFIG_DEVPORT=y
 # CONFIG_XILLYBUS is not set
 # end of Character devices
 
+# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
+
 #
 # I2C support
 #
@@ -3623,6 +3651,7 @@ CONFIG_SENSORS_ADT7411=m
 CONFIG_SENSORS_ADT7462=m
 CONFIG_SENSORS_ADT7470=m
 CONFIG_SENSORS_ADT7475=m
+CONFIG_SENSORS_AS370=m
 CONFIG_SENSORS_ASC7621=m
 CONFIG_SENSORS_ARM_SCPI=m
 CONFIG_SENSORS_ASPEED=m
@@ -3697,6 +3726,7 @@ CONFIG_PMBUS=m
 CONFIG_SENSORS_PMBUS=m
 CONFIG_SENSORS_ADM1275=m
 # CONFIG_SENSORS_IBM_CFFPS is not set
+CONFIG_SENSORS_INSPUR_IPSPS=m
 CONFIG_SENSORS_IR35221=m
 CONFIG_SENSORS_IR38064=m
 # CONFIG_SENSORS_IRPS5401 is not set
@@ -3732,7 +3762,6 @@ CONFIG_SENSORS_SMSC47B397=m
 CONFIG_SENSORS_STTS751=m
 CONFIG_SENSORS_SMM665=m
 CONFIG_SENSORS_ADC128D818=m
-CONFIG_SENSORS_ADS1015=m
 CONFIG_SENSORS_ADS7828=m
 CONFIG_SENSORS_ADS7871=m
 CONFIG_SENSORS_AMC6821=m
@@ -3826,7 +3855,6 @@ CONFIG_MFD_CORE=y
 # CONFIG_MFD_BCM590XX is not set
 # CONFIG_MFD_BD9571MWV is not set
 # CONFIG_MFD_AXP20X_I2C is not set
-# CONFIG_MFD_CROS_EC is not set
 CONFIG_MFD_MADERA=m
 CONFIG_MFD_MADERA_I2C=m
 # CONFIG_MFD_MADERA_SPI is not set
@@ -3964,6 +3992,7 @@ CONFIG_REGULATOR_MAX77650=m
 CONFIG_REGULATOR_PWM=m
 # CONFIG_REGULATOR_SLG51000 is not set
 # CONFIG_REGULATOR_SY8106A is not set
+CONFIG_REGULATOR_SY8824X=m
 # CONFIG_REGULATOR_TPS51632 is not set
 # CONFIG_REGULATOR_TPS62360 is not set
 # CONFIG_REGULATOR_TPS65023 is not set
@@ -4002,6 +4031,7 @@ CONFIG_MEDIA_SDR_SUPPORT=y
 # CONFIG_MEDIA_CONTROLLER is not set
 CONFIG_VIDEO_DEV=m
 CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L2_I2C=y
 # CONFIG_VIDEO_ADV_DEBUG is not set
 # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
 
@@ -4399,6 +4429,7 @@ CONFIG_HID_CHICONY=y
 # CONFIG_HID_COUGAR is not set
 CONFIG_HID_MACALLY=m
 # CONFIG_HID_CMEDIA is not set
+CONFIG_HID_CREATIVE_SB0540=m
 CONFIG_HID_CYPRESS=y
 # CONFIG_HID_DRAGONRISE is not set
 # CONFIG_HID_EMS_FF is not set
@@ -4491,6 +4522,9 @@ CONFIG_USB_HID=y
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_COMMON=y
+# CONFIG_USB_LED_TRIG is not set
+# CONFIG_USB_ULPI_BUS is not set
+# CONFIG_USB_CONN_GPIO is not set
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB=y
 CONFIG_USB_PCI=y
@@ -4507,7 +4541,6 @@ CONFIG_USB_DEFAULT_PERSIST=y
 # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
 CONFIG_USB_AUTOSUSPEND_DELAY=2
 # CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB_CBAF is not set
 
 #
 # USB Host Controller Drivers
@@ -4577,6 +4610,10 @@ CONFIG_USB_UAS=m
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
 # CONFIG_USBIP_CORE is not set
+CONFIG_USB_CDNS3=m
+# CONFIG_USB_CDNS3_GADGET is not set
+# CONFIG_USB_CDNS3_HOST is not set
+CONFIG_USB_CDNS3_PCI_WRAP=m
 # CONFIG_USB_MUSB_HDRC is not set
 # CONFIG_USB_DWC3 is not set
 # CONFIG_USB_DWC2 is not set
@@ -4652,7 +4689,6 @@ CONFIG_USB_SERIAL_FTDI_SIO=m
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
 # CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
@@ -4755,9 +4791,6 @@ CONFIG_TYPEC_FUSB302=m
 # end of USB Type-C Alternate Mode drivers
 
 CONFIG_USB_ROLE_SWITCH=m
-# CONFIG_USB_LED_TRIG is not set
-# CONFIG_USB_ULPI_BUS is not set
-# CONFIG_UWB is not set
 CONFIG_MMC=y
 CONFIG_PWRSEQ_EMMC=y
 # CONFIG_PWRSEQ_SD8787 is not set
@@ -4778,6 +4811,7 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ACPI=m
 CONFIG_MMC_SDHCI_PLTFM=y
 # CONFIG_MMC_SDHCI_OF_ARASAN is not set
+CONFIG_MMC_SDHCI_OF_ASPEED=m
 # CONFIG_MMC_SDHCI_OF_AT91 is not set
 # CONFIG_MMC_SDHCI_OF_DWCMSHC is not set
 # CONFIG_MMC_SDHCI_CADENCE is not set
@@ -4916,7 +4950,6 @@ CONFIG_RTC_DRV_PCF85363=m
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_BD70528 is not set
 # CONFIG_RTC_DRV_BQ32K is not set
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
@@ -5032,6 +5065,7 @@ CONFIG_DMA_ENGINE_RAID=y
 #
 # CONFIG_SYNC_FILE is not set
 # CONFIG_UDMABUF is not set
+CONFIG_DMABUF_SELFTESTS=m
 # end of DMABUF options
 
 # CONFIG_AUXDISPLAY is not set
@@ -5085,6 +5119,7 @@ CONFIG_XEN_EFI=y
 CONFIG_XEN_AUTO_XLATE=y
 # end of Xen driver support
 
+# CONFIG_GREYBUS is not set
 CONFIG_STAGING=y
 # CONFIG_PRISM2_USB is not set
 # CONFIG_COMEDI is not set
@@ -5122,7 +5157,6 @@ CONFIG_VT6656=m
 # CONFIG_WILC1000_SPI is not set
 # CONFIG_MOST is not set
 # CONFIG_KS7010 is not set
-# CONFIG_GREYBUS is not set
 # CONFIG_PI433 is not set
 
 #
@@ -5132,9 +5166,20 @@ CONFIG_VT6656=m
 # end of Gasket devices
 
 # CONFIG_XIL_AXIS_FIFO is not set
-# CONFIG_EROFS_FS is not set
 # CONFIG_FIELDBUS_DEV is not set
+# CONFIG_USB_WUSB_CBAF is not set
+# CONFIG_UWB is not set
+CONFIG_EXFAT_FS=m
+CONFIG_EXFAT_DONT_MOUNT_VFAT=y
+CONFIG_EXFAT_DISCARD=y
+# CONFIG_EXFAT_DELAYED_SYNC is not set
+# CONFIG_EXFAT_KERNEL_DEBUG is not set
+# CONFIG_EXFAT_DEBUG_MSG is not set
+CONFIG_EXFAT_DEFAULT_CODEPAGE=437
+CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
+# CONFIG_QLGE is not set
 # CONFIG_GOLDFISH is not set
+# CONFIG_MFD_CROS_EC is not set
 # CONFIG_CHROME_PLATFORMS is not set
 # CONFIG_MELLANOX_PLATFORM is not set
 CONFIG_CLKDEV_LOOKUP=y
@@ -5164,6 +5209,7 @@ CONFIG_COMMON_CLK_PWM=m
 # CONFIG_COMMON_CLK_VC5 is not set
 CONFIG_COMMON_CLK_BD718XX=m
 # CONFIG_COMMON_CLK_FIXED_MMIO is not set
+CONFIG_ARMADA_AP_CP_HELPER=y
 CONFIG_ARMADA_37XX_CLK=y
 CONFIG_ARMADA_AP806_SYSCON=y
 CONFIG_ARMADA_CP110_SYSCON=y
@@ -5460,6 +5506,7 @@ CONFIG_EXPORTFS=y
 CONFIG_FILE_LOCKING=y
 CONFIG_MANDATORY_FILE_LOCKING=y
 CONFIG_FS_ENCRYPTION=y
+# CONFIG_FS_VERITY is not set
 CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -5476,6 +5523,7 @@ CONFIG_AUTOFS4_FS=y
 CONFIG_AUTOFS_FS=y
 CONFIG_FUSE_FS=m
 CONFIG_CUSE=m
+# CONFIG_VIRTIO_FS is not set
 CONFIG_OVERLAY_FS=m
 # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
 CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
@@ -5571,23 +5619,7 @@ CONFIG_UBIFS_FS_SECURITY=y
 # CONFIG_PSTORE is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-CONFIG_AUFS_FS=m
+# CONFIG_EROFS_FS is not set
-CONFIG_AUFS_BRANCH_MAX_127=y
-# CONFIG_AUFS_BRANCH_MAX_511 is not set
-# CONFIG_AUFS_BRANCH_MAX_1023 is not set
-# CONFIG_AUFS_BRANCH_MAX_32767 is not set
-CONFIG_AUFS_SBILIST=y
-# CONFIG_AUFS_HNOTIFY is not set
-# CONFIG_AUFS_EXPORT is not set
-# CONFIG_AUFS_XATTR is not set
-# CONFIG_AUFS_FHSM is not set
-# CONFIG_AUFS_RDU is not set
-# CONFIG_AUFS_DIRREN is not set
-# CONFIG_AUFS_SHWH is not set
-# CONFIG_AUFS_BR_RAMFS is not set
-# CONFIG_AUFS_BR_FUSE is not set
-CONFIG_AUFS_BDEV_LOOP=y
-# CONFIG_AUFS_DEBUG is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V2=y
@@ -5710,6 +5742,7 @@ CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
 # CONFIG_SECURITY_LOADPIN is not set
 # CONFIG_SECURITY_YAMA is not set
 # CONFIG_SECURITY_SAFESETID is not set
+# CONFIG_SECURITY_LOCKDOWN_LSM is not set
 CONFIG_INTEGRITY=y
 # CONFIG_INTEGRITY_SIGNATURE is not set
 CONFIG_INTEGRITY_AUDIT=y
@@ -5791,10 +5824,6 @@ CONFIG_CRYPTO_CCM=m
 CONFIG_CRYPTO_GCM=m
 # CONFIG_CRYPTO_CHACHA20POLY1305 is not set
 # CONFIG_CRYPTO_AEGIS128 is not set
-CONFIG_CRYPTO_AEGIS128L=m
-CONFIG_CRYPTO_AEGIS256=m
-CONFIG_CRYPTO_MORUS640=m
-CONFIG_CRYPTO_MORUS1280=m
 CONFIG_CRYPTO_SEQIV=y
 CONFIG_CRYPTO_ECHAINIV=m
 
@@ -5813,6 +5842,7 @@ CONFIG_CRYPTO_XTS=y
 CONFIG_CRYPTO_KEYWRAP=m
 CONFIG_CRYPTO_NHPOLY1305=m
 # CONFIG_CRYPTO_ADIANTUM is not set
+CONFIG_CRYPTO_ESSIV=m
 
 #
 # Hash modes
@@ -5839,6 +5869,7 @@ CONFIG_CRYPTO_RMD160=y
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
 CONFIG_CRYPTO_SHA3=m
@@ -5850,6 +5881,7 @@ CONFIG_CRYPTO_WP512=y
 #
 # Ciphers
 #
+CONFIG_CRYPTO_LIB_AES=y
 CONFIG_CRYPTO_AES=y
 CONFIG_CRYPTO_AES_TI=m
 CONFIG_CRYPTO_ANUBIS=m
@@ -5861,6 +5893,7 @@ CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_CAST_COMMON=m
 CONFIG_CRYPTO_CAST5=m
 CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_LIB_DES=m
 CONFIG_CRYPTO_DES=m
 CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_KHAZAD=m
@@ -5912,6 +5945,9 @@ CONFIG_CRYPTO_DEV_VIRTIO=m
 CONFIG_CRYPTO_DEV_SAFEXCEL=m
 CONFIG_CRYPTO_DEV_CCREE=m
 # CONFIG_CRYPTO_DEV_HISI_SEC is not set
+CONFIG_CRYPTO_DEV_HISI_QM=m
+CONFIG_CRYPTO_HISI_SGL=m
+CONFIG_CRYPTO_DEV_HISI_ZIP=m
 CONFIG_ASYMMETRIC_KEY_TYPE=y
 CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
 CONFIG_X509_CERTIFICATE_PARSER=y
@@ -6013,7 +6049,6 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
 CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
 CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
 CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
-CONFIG_ARCH_HAS_DMA_MMAP_PGPROT=y
 CONFIG_SWIOTLB=y
 CONFIG_DMA_REMAP=y
 CONFIG_DMA_DIRECT_REMAP=y
@@ -6035,21 +6070,20 @@ CONFIG_DQL=y
 CONFIG_GLOB=y
 # CONFIG_GLOB_SELFTEST is not set
 CONFIG_NLATTR=y
+CONFIG_LRU_CACHE=m
 CONFIG_CLZ_TAB=y
 # CONFIG_IRQ_POLL is not set
 CONFIG_MPILIB=y
-CONFIG_DIMLIB=y
 CONFIG_LIBFDT=y
 CONFIG_OID_REGISTRY=y
 CONFIG_UCS2_STRING=y
 CONFIG_HAVE_GENERIC_VDSO=y
 CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_COMPAT_VDSO=y
-CONFIG_CROSS_COMPILE_COMPAT_VDSO=""
 CONFIG_FONT_SUPPORT=y
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
+CONFIG_SG_SPLIT=y
 CONFIG_SG_POOL=y
 CONFIG_SBITMAP=y
 # CONFIG_STRING_SELFTEST is not set
@@ -6079,10 +6113,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=2048
 # CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_READABLE_ASM is not set
-# CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_INSTALL is not set
-# CONFIG_OPTIMIZE_INLINING is not set
+CONFIG_OPTIMIZE_INLINING=y
 # CONFIG_DEBUG_SECTION_MISMATCH is not set
 CONFIG_SECTION_MISMATCH_WARN_ONLY=y
 CONFIG_ARCH_WANT_FRAME_POINTERS=y

config/kernel/linux-mvebu64-legacy.config

@@ -1 +0,0 @@
-linux-mvebu64-default.config

config/sources/families/mvebu64.conf

@@ -27,7 +27,7 @@ fi
 
 case $BRANCH in
 
-	legacy|default)
+	legacy)
 
 		KERNELSOURCE='https://github.com/MarvellEmbeddedProcessors/linux-marvell.git'
 		KERNELBRANCH='branch:linux-4.14.22-armada-18.06'
@@ -36,14 +36,14 @@ case $BRANCH in
 
 	;;
 
-	current|next)
+	current)
 
 		KERNELBRANCH='branch:linux-4.19.y'
 
 	;;
 
         dev)
-		:
+		KERNELBRANCH='branch:linux-5.4.y'
         ;;
 
 esac

patch/kernel/mvebu64-dev

@@ -1 +0,0 @@
-mvebu64-current

patch/kernel/mvebu64-dev/0004-ARM64-dts-marvell-armada37xx-Enable-USB2-on-espresso.patch

@@ -0,0 +1,33 @@
+From d71549275ca1e2bee8e7914501526b625e9f8a53 Mon Sep 17 00:00:00 2001
+From: Marc Zyngier <Marc.Zyngier@arm.com>
+Date: Sat, 1 Jul 2017 15:16:37 +0100
+Subject: [PATCH 04/11] ARM64: dts: marvell: armada37xx: Enable USB2 on
+ espressobin
+
+The Espressobin SBC has a USB2 interface available on J8. Let's
+enable it.
+
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+---
+ arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+index e3a136ed77b0..b1af3f988b29 100644
+--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+@@ -81,6 +81,11 @@
+ 	status = "okay";
+ };
+ 
++/* J8 */
++&usb2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	switch0: switch0@1 {
+ 		compatible = "marvell,mv88e6085";
+-- 
+2.13.3
+

patch/kernel/mvebu64-dev/0007-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch

@@ -0,0 +1,25 @@
+From 8440f9edeb29c10cc0ec29c55c07d4e5e5b67c5b Mon Sep 17 00:00:00 2001
+From: Kevin Mihelich <kevin@archlinuxarm.org>
+Date: Tue, 4 Jul 2017 19:25:28 -0600
+Subject: [PATCH 07/11] arm64: dts: marvell: armada37xx: Add eth0 alias
+
+Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
+---
+ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+index a78195b4ef7a..14248957b2dd 100644
+--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+@@ -54,6 +54,7 @@
+ 	#size-cells = <2>;
+ 
+ 	aliases {
++		ethernet0 = &eth0;
+ 		serial0 = &uart0;
+ 	};
+ 
+-- 
+2.13.3
+

patch/kernel/mvebu64-dev/0011-espressobin-enable-emmc.patch

@@ -0,0 +1,20 @@
+diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+index 2ce52ba..a759fd1 100644
+--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+@@ -96,6 +96,15 @@
+ 	status = "okay";
+ };
+ 
++&sdhci0 {
++	non-removable;
++	bus-width = <8>;
++	mmc-ddr-1_8v;
++	mmc-hs400-1_8v;
++	marvell,pad-type = "fixed-1-8v";
++	status = "okay";
++};
++
+ /* Exported on the micro USB connector J5 through an FTDI */
+ &uart0 {
+ 	status = "okay";

patch/kernel/mvebu64-dev/12-add-linux-partition-spi-flash.patch

@@ -0,0 +1,17 @@
+diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+index b3cf091a..ab2d8e2e 100644
+--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+@@ -86,6 +86,12 @@
+ 				label = "ubootenv";
+ 				reg = <0x180000 0x10000>;
+ 			};
++			
++			partition@190000 {
++				label = "Linux";
++				reg = <0x190000 0xDF0000>;
++			}; 
++			
+ 		};
+ 	};
+ };

patch/kernel/mvebu64-dev/2002-clk_mvebu_armada-37xx-periph_save_the_IP_base_address_in_the_driver_data.patch.disabled

@@ -0,0 +1,70 @@
+From d9d95e78cff80c3fe43e757ba90644cd766302ac Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 13 Jul 2018 15:44:45 +0200
+Subject: clk: mvebu: armada-37xx-periph: save the IP base address in the
+ driver data
+
+Prepare the introduction of suspend/resume hooks by having an easy way
+to access all the registers in one go just from a device: add the IP
+base address in the driver data.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mvebu/armada-37xx-periph.c | 15 +++++++--------
+ 1 file changed, 7 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
+index 499f5962c8b0..78048c2e3774 100644
+--- a/drivers/clk/mvebu/armada-37xx-periph.c
++++ b/drivers/clk/mvebu/armada-37xx-periph.c
+@@ -56,6 +56,7 @@
+ struct clk_periph_driver_data {
+ 	struct clk_hw_onecell_data *hw_data;
+ 	spinlock_t lock;
++	void __iomem *reg;
+ };
+ 
+ struct clk_double_div {
+@@ -680,7 +681,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	int num_periph = 0, i, ret;
+ 	struct resource *res;
+-	void __iomem *reg;
+ 
+ 	data = of_device_get_match_data(dev);
+ 	if (!data)
+@@ -689,11 +689,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
+ 	while (data[num_periph].name)
+ 		num_periph++;
+ 
+-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	reg = devm_ioremap_resource(dev, res);
+-	if (IS_ERR(reg))
+-		return PTR_ERR(reg);
+-
+ 	driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
+ 	if (!driver_data)
+ 		return -ENOMEM;
+@@ -706,12 +701,16 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
+ 		return -ENOMEM;
+ 	driver_data->hw_data->num = num_periph;
+ 
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	driver_data->reg = devm_ioremap_resource(dev, res);
++	if (IS_ERR(driver_data->reg))
++		return PTR_ERR(driver_data->reg);
++
+ 	spin_lock_init(&driver_data->lock);
+ 
+ 	for (i = 0; i < num_periph; i++) {
+ 		struct clk_hw **hw = &driver_data->hw_data->hws[i];
+-
+-		if (armada_3700_add_composite_clk(&data[i], reg,
++		if (armada_3700_add_composite_clk(&data[i], driver_data->reg,
+ 						  &driver_data->lock, dev, hw))
+ 			dev_err(dev, "Can't register periph clock %s\n",
+ 				data[i].name);
+-- 
+cgit 1.2-0.3.lf.el7
+

patch/kernel/mvebu64-dev/add-board-espressobinv7.patch

@@ -0,0 +1,219 @@
+diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
+index ea9d49f2a911..d80da8f5d82d 100644
+--- a/arch/arm64/boot/dts/marvell/Makefile
++++ b/arch/arm64/boot/dts/marvell/Makefile
+@@ -2,6 +2,7 @@
+ # Mvebu SoC Family
+ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
+ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
++dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobinv7.dtb
+ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb
+ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb
+ dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
+diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobinv7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobinv7.dts
+new file mode 100644
+index 000000000000..6385b2488e45
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobinv7.dts
+@@ -0,0 +1,201 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Globalscale Marvell ESPRESSOBin Board
++ * Copyright (C) 2016 Marvell
++ *
++ * Romain Perier <romain.perier@free-electrons.com>
++ *
++ */
++/*
++ * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include "armada-372x.dtsi"
++
++/ {
++	model = "Globalscale Marvell ESPRESSOBin Board";
++	compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	memory@0 {
++		device_type = "memory";
++		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
++	};
++
++	vcc_sd_reg1: regulator {
++		compatible = "regulator-gpio";
++		regulator-name = "vcc_sd1";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++
++		gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
++		gpios-states = <0>;
++		states = <1800000 0x1
++			  3300000 0x0>;
++		enable-active-high;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		red {
++			label = "espressobin:red:usr";
++			gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
++		};
++	};
++};
++
++/* J9 */
++&pcie0 {
++	status = "okay";
++};
++
++/* J6 */
++&sata {
++	status = "okay";
++};
++
++/* J1 */
++&sdhci1 {
++	wp-inverted;
++	bus-width = <4>;
++	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
++	marvell,pad-type = "sd";
++	vqmmc-supply = <&vcc_sd_reg1>;
++	status = "okay";
++};
++
++&spi0 {
++	status = "okay";
++
++	flash@0 {
++		reg = <0>;
++		/*
++		 * Originally "winbond,w25q32dw", but since the manufacturer is known
++		 * to have replaced the part with "macronix,mx25u3235f" in some board
++		 * batches, just use the generic "jedec,spi-nor" and let the actual
++		 * chip type be probed. The partition table still depends on the chip
++		 * being 4 MiB in size.
++		 */
++		compatible = "jedec,spi-nor";
++		spi-max-frequency = <104000000>;
++		m25p,fast-read;
++		status = "okay";
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "uboot";
++				reg = <0 0x3f0000>;
++			};
++
++			partition@3f0000 {
++				label = "ubootenv";
++				reg = <0x3f0000 0x10000>;
++			};
++		};
++	};
++};
++
++/* Exported on the micro USB connector J5 through an FTDI */
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>;
++	status = "okay";
++};
++
++/*
++ * Connector J17 and J18 expose a number of different features. Some pins are
++ * multiplexed. This is the case for instance for the following features:
++ * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
++ *   how to enable it. Beware that the signals are 1.8V TTL.
++ * - I2C
++ * - SPI
++ * - MMC
++ */
++
++/* J7 */
++&usb3 {
++	status = "okay";
++};
++
++/* J8 */
++&usb2 {
++	status = "okay";
++};
++
++&mdio {
++	switch0: switch0@1 {
++		compatible = "marvell,mv88e6085";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <1>;
++
++		dsa,member = <0 0>;
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++				label = "cpu";
++				ethernet = <&eth0>;
++			};
++
++			port@1 {
++				reg = <1>;
++				label = "lan1";
++				phy-handle = <&switch0phy0>;
++			};
++
++			port@2 {
++				reg = <2>;
++				label = "lan0";
++				phy-handle = <&switch0phy1>;
++			};
++
++			port@3 {
++				reg = <3>;
++				label = "wan";
++				phy-handle = <&switch0phy2>;
++			};
++
++		};
++
++		mdio {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			switch0phy0: switch0phy0@11 {
++				reg = <0x11>;
++			};
++			switch0phy1: switch0phy1@12 {
++				reg = <0x12>;
++			};
++			switch0phy2: switch0phy2@13 {
++				reg = <0x13>;
++			};
++		};
++	};
++};
++
++&eth0 {
++	phy-mode = "rgmii-id";
++	status = "okay";
++
++	fixed-link {
++		speed = <1000>;
++		full-duplex;
++	};
++};

patch/kernel/mvebu64-dev/adjust-espresso-dts.patch

@@ -0,0 +1,91 @@
+diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+index cd5fbfa38..a81391164 100644
+--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+@@ -41,6 +41,16 @@
+ 			  3300000 0x0>;
+ 		enable-active-high;
+ 	};
++	
++	leds {
++		compatible = "gpio-leds";
++
++		red {
++			label = "espressobin:red:usr";
++			gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
++		};
++	};
++	
+ };
+ 
+ /* J9 */
+@@ -95,19 +105,35 @@
+ 
+ 	flash@0 {
+ 		reg = <0>;
++		/*
++		 * Originally "winbond,w25q32dw", but since the manufacturer is known
++		 * to have replaced the part with "macronix,mx25u3235f" in some board
++		 * batches, just use the generic "jedec,spi-nor" and let the actual
++		 * chip type be probed. The partition table still depends on the chip
++		 * being 4 MiB in size.
++		 */
+ 		compatible = "jedec,spi-nor";
+ 		spi-max-frequency = <104000000>;
+ 		m25p,fast-read;
+-	};
+-};
++		status = "okay";
++		
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
+ 
+-&sdhci0 {
+-	non-removable;
+-	bus-width = <8>;
+-	mmc-ddr-1_8v;
+-	mmc-hs400-1_8v;
+-	marvell,pad-type = "fixed-1-8v";
+-	status = "okay";
++			partition@0 {
++				label = "uboot";
++				reg = <0 0x3f0000>;
++			};
++
++			partition@180000 {
++				label = "ubootenv";
++				reg = <0x3f0000 0x10000>;
++			};
++		};
++		
++	};
+ };
+ 
+ /* Exported on the micro USB connector J5 through an FTDI */
+@@ -137,11 +163,6 @@
+ 	status = "okay";
+ };
+ 
+-/* J8 */
+-&usb2 {
+-	status = "okay";
+-};
+-
+ &mdio {
+ 	switch0: switch0@1 {
+ 		compatible = "marvell,mv88e6085";
+@@ -199,12 +220,6 @@
+ 			switch0phy2: switch0phy2@13 {
+ 				reg = <0x13>;
+ 			};
+-			
+-			partition@190000 {
+-				label = "Linux";
+-				reg = <0x190000 0xDF0000>;
+-			}; 
+-			
+ 		};
+ 	};
+ };

patch/kernel/mvebu64-dev/armada-37xx-cpufreq.patch.disabled

@@ -0,0 +1,80 @@
+diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
+index 75491fc84..c2adf380b 100644
+--- a/drivers/cpufreq/armada-37xx-cpufreq.c
++++ b/drivers/cpufreq/armada-37xx-cpufreq.c
+@@ -162,11 +162,25 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
+ 	}
+ 
+ 	/*
+-	 * Set cpu clock source, for all the level we keep the same
+-	 * clock source that the one already configured. For this one
+-	 * we need to use the clock framework
+-	 */
++	* Set CPU clock source, for all the level we keep the same
++	* clock source that the one already configured with DVS
++	* disabled. For this one we need to use the clock framewor
++	*/
+ 	parent = clk_get_parent(clk);
++
++	/*
++	* Unset parent clock to force the clock framework setting again
++	* the clock parent
++	*/
++	clk_set_parent(clk, NULL);
++
++	/*
++	* For the Armada 37xx CPU clocks, setting the parent will
++	* actually configure the parent when DVFS is enabled. At
++	* hardware level it will be a different register from the one
++	* read when doing clk_get_parent that will be set with
++	* clk_set_parent.
++	*/
+ 	clk_set_parent(clk, parent);
+ }
+ 
+@@ -359,11 +373,11 @@ static int __init armada37xx_cpufreq_driver_init(void)
+ 	struct armada_37xx_dvfs *dvfs;
+ 	struct platform_device *pdev;
+ 	unsigned long freq;
+-	unsigned int cur_frequency;
++	unsigned int cur_frequency, base_frequency;
+ 	struct regmap *nb_pm_base, *avs_base;
+ 	struct device *cpu_dev;
+ 	int load_lvl, ret;
+-	struct clk *clk;
++	struct clk *clk, *parent;
+ 
+ 	nb_pm_base =
+ 		syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
+@@ -399,6 +413,22 @@ static int __init armada37xx_cpufreq_driver_init(void)
+ 		return PTR_ERR(clk);
+ 	}
+ 
++	parent = clk_get_parent(clk);
++	if (IS_ERR(parent)) {
++		dev_err(cpu_dev, "Cannot get parent clock for CPU0\n");
++		clk_put(clk);
++		return PTR_ERR(parent);
++	}
++
++	/* Get parent CPU frequency */
++	base_frequency =  clk_get_rate(parent);
++
++	if (!base_frequency) {
++		dev_err(cpu_dev, "Failed to get parent clock rate for CPU\n");
++		clk_put(clk);
++		return -EINVAL;
++	}
++
+ 	/* Get nominal (current) CPU frequency */
+ 	cur_frequency = clk_get_rate(clk);
+ 	if (!cur_frequency) {
+@@ -431,7 +461,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
+ 	for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
+ 	     load_lvl++) {
+ 		unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
+-		freq = cur_frequency / dvfs->divider[load_lvl];
++		freq = base_frequency / dvfs->divider[load_lvl];
+ 		ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
+ 		if (ret)
+ 			goto remove_opp;

patch/kernel/mvebu64-dev/armada-37xx-xtal-correct-pin.patch

@@ -0,0 +1,30 @@
+From 80d4cec4cef8282e5ac3aaf98ce3e68fb299a134 Mon Sep 17 00:00:00 2001
+From: Terry Zhou <bjzhou@marvell.com>
+Date: Mon, 29 Jan 2018 15:01:31 +0800
+Subject: [PATCH] clk: mvebu: a3700: fix the XTAL MODE pin to SB MPP9
+
+There is an error in the current code that the XTAL MODE
+pin was set to SB MPP31 which should be SB MPP9
+The latch register of SB MPP9 has different offset of 0x8
+
+Change-Id: I73d41d0c053808fd18944ed1d191aea817b6d21a
+Signed-off-by: Terry Zhou <bjzhou@marvell.com>
+---
+ drivers/clk/mvebu/armada-37xx-xtal.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/mvebu/armada-37xx-xtal.c b/drivers/clk/mvebu/armada-37xx-xtal.c
+index 612d65ede10a..5370514959e1 100644
+--- a/drivers/clk/mvebu/armada-37xx-xtal.c
++++ b/drivers/clk/mvebu/armada-37xx-xtal.c
+@@ -15,8 +15,8 @@
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ 
+-#define NB_GPIO1_LATCH	0xC
+-#define XTAL_MODE	    BIT(31)
++#define NB_GPIO1_LATCH	0x8
++#define XTAL_MODE	    BIT(9)
+ 
+ static int armada_3700_xtal_clock_probe(struct platform_device *pdev)
+ {

patch/kernel/mvebu64-dev/enable_ath10_cards.patch

@@ -0,0 +1,16 @@
+diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
+index a42a040..1754456
+--- a/drivers/pci/controller/pci-aardvark.c
++++ b/drivers/pci/controller/pci-aardvark.c
+@@ -312,9 +312,10 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
+ 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+
+ 	/* Set GEN2 */
++	/* Set GEN1 */
+ 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+ 	reg &= ~PCIE_GEN_SEL_MSK;
+-	reg |= SPEED_GEN_2;
++	reg |= SPEED_GEN_1;
+ 	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+
+ 	/* Set lane X1 */

patch/kernel/mvebu64-dev/fix_problem_with_cpu_scaling_not_working.patch.disabled

@@ -0,0 +1,57 @@
+From 8fe9a4c4a024a6353e810a1dbb5e4bc78bff60a8 Mon Sep 17 00:00:00 2001
+From: FlashBurnGitHub <33546258+FlashBurnGitHub@users.noreply.github.com>
+Date: Wed, 6 Mar 2019 17:25:46 +0100
+Subject: [PATCH] Fix problem with cpu scaling not working
+
+This fixes a problem that the cpu scaling is not working.
+
+First one needs to first unset the parent clock, before setting the same old parent clock again. This solves the problem that the wrong TBG clock source was used for the cpu.
+
+Also one needs to multiply the current cpu frequency with the used divider so that the right cpu frequency gets calculated when applying the dividers. This was need for a 600MHz final cpu frequency to work
+---
+ drivers/cpufreq/armada-37xx-cpufreq.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
+index 75491fc841a6..5c744092f819 100644
+--- a/drivers/cpufreq/armada-37xx-cpufreq.c
++++ b/drivers/cpufreq/armada-37xx-cpufreq.c
+@@ -167,6 +167,11 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
+ 	 * we need to use the clock framework
+ 	 */
+ 	parent = clk_get_parent(clk);
++	
++	/* Unset parent clock */
++	clk_set_parent(clk, NULL);
++	
++	/* set old parent; this triggers setting needed values for right CPU clock in hardware regs */
+ 	clk_set_parent(clk, parent);
+ }
+ 
+@@ -360,6 +365,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
+ 	struct platform_device *pdev;
+ 	unsigned long freq;
+ 	unsigned int cur_frequency;
++	unsigned int base_frequency;
+ 	struct regmap *nb_pm_base, *avs_base;
+ 	struct device *cpu_dev;
+ 	int load_lvl, ret;
+@@ -412,6 +418,9 @@ static int __init armada37xx_cpufreq_driver_init(void)
+ 		clk_put(clk);
+ 		return -EINVAL;
+ 	}
++	
++	/* Get base CPU frequency without divider */
++	base_frequency = cur_frequency * dvfs->divider[ARMADA_37XX_DVFS_LOAD_0];
+ 
+ 	armada37xx_cpufreq_state = kmalloc(sizeof(*armada37xx_cpufreq_state),
+ 					   GFP_KERNEL);
+@@ -431,7 +440,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
+ 	for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
+ 	     load_lvl++) {
+ 		unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
+-		freq = cur_frequency / dvfs->divider[load_lvl];
++		freq = base_frequency / dvfs->divider[load_lvl];
+ 		ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
+ 		if (ret)
+ 			goto remove_opp;

patch/kernel/mvebu64-dev/spi-nor.c.patch

@@ -0,0 +1,12 @@
+diff --git linux-4.18.7/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
+index f028277fb..e4886c95c 100644
+--- linux-4.18.7/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -1085,6 +1085,7 @@ static const struct flash_info spi_nor_ids[] = {
+ 	{ "mx25u2033e",  INFO(0xc22532, 0, 64 * 1024,   4, SECT_4K) },
+ 	{ "mx25u4035",   INFO(0xc22533, 0, 64 * 1024,   8, SECT_4K) },
+ 	{ "mx25u8035",   INFO(0xc22534, 0, 64 * 1024,  16, SECT_4K) },
++	{ "mx25u3235f",  INFO(0xc22536, 0, 64 * 1024,  64, SECT_4K) },
+ 	{ "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
+ 	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
+ 	{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },

patch/kernel/mvebu64-dev/unlock_atheros_regulatory_restrictions.patch

@@ -0,0 +1,72 @@
+diff --git a/drivers/net/wireless/ath/regd.c b/drivers/net/wireless/ath/regd.c
+index ccc4c71..71a4d00 100644
+--- a/drivers/net/wireless/ath/regd.c
++++ b/drivers/net/wireless/ath/regd.c
+@@ -49,12 +49,9 @@ static int __ath_regd_init(struct ath_regulatory *reg);
+ #define ATH9K_5GHZ_5725_5850	REG_RULE(5725-10, 5850+10, 40, 0, 30,\
+ 				NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
+ 
+-#define ATH9K_2GHZ_ALL		ATH9K_2GHZ_CH01_11, \
+-				ATH9K_2GHZ_CH12_13, \
+-				ATH9K_2GHZ_CH14
++#define ATH9K_2GHZ_ALL     REG_RULE(2400, 2483, 40, 0, 30, 0)
+ 
+-#define ATH9K_5GHZ_ALL		ATH9K_5GHZ_5150_5350, \
+-				ATH9K_5GHZ_5470_5850
++#define ATH9K_5GHZ_ALL     REG_RULE(5140, 5860, 40, 0, 30, 0)
+ 
+ /* This one skips what we call "mid band" */
+ #define ATH9K_5GHZ_NO_MIDBAND	ATH9K_5GHZ_5150_5350, \
+@@ -76,9 +73,8 @@ static const struct ieee80211_regdomain ath_world_regdom_63_65 = {
+ 	.n_reg_rules = 4,
+ 	.alpha2 =  "99",
+ 	.reg_rules = {
+-		ATH9K_2GHZ_CH01_11,
+-		ATH9K_2GHZ_CH12_13,
+-		ATH9K_5GHZ_NO_MIDBAND,
++		ATH9K_2GHZ_ALL,
++		ATH9K_5GHZ_ALL,
+ 	}
+ };
+ 
+@@ -87,8 +83,8 @@ static const struct ieee80211_regdomain ath_world_regdom_64 = {
+ 	.n_reg_rules = 3,
+ 	.alpha2 =  "99",
+ 	.reg_rules = {
+-		ATH9K_2GHZ_CH01_11,
+-		ATH9K_5GHZ_NO_MIDBAND,
++		ATH9K_2GHZ_ALL,
++		ATH9K_5GHZ_ALL,
+ 	}
+ };
+ 
+@@ -97,7 +93,7 @@ static const struct ieee80211_regdomain ath_world_regdom_66_69 = {
+ 	.n_reg_rules = 3,
+ 	.alpha2 =  "99",
+ 	.reg_rules = {
+-		ATH9K_2GHZ_CH01_11,
++		ATH9K_2GHZ_ALL,
+ 		ATH9K_5GHZ_ALL,
+ 	}
+ };
+@@ -107,8 +103,7 @@ static const struct ieee80211_regdomain ath_world_regdom_67_68_6A_6C = {
+ 	.n_reg_rules = 4,
+ 	.alpha2 =  "99",
+ 	.reg_rules = {
+-		ATH9K_2GHZ_CH01_11,
+-		ATH9K_2GHZ_CH12_13,
++		ATH9K_2GHZ_ALL,
+ 		ATH9K_5GHZ_ALL,
+ 	}
+ };
+@@ -253,9 +253,7 @@ static bool ath_is_radar_freq(u16 center_freq,
+ 			      struct ath_regulatory *reg)
+ 
+ {
+-	if (reg->country_code == CTRY_INDIA)
+-		return (center_freq >= 5500 && center_freq <= 5700);
+-	return (center_freq >= 5260 && center_freq <= 5700);
++	return false;
+ }
+ 
+ static void ath_force_clear_no_ir_chan(struct wiphy *wiphy,