diff --git a/patch/kernel/sun8i-dev/add_missing_SPI_for-H3_v4.9.x.patch b/patch/kernel/sun8i-dev/add_missing_SPI_for-H3_v4.9.x.patch index 07f045304..a42ca484d 100644 --- a/patch/kernel/sun8i-dev/add_missing_SPI_for-H3_v4.9.x.patch +++ b/patch/kernel/sun8i-dev/add_missing_SPI_for-H3_v4.9.x.patch @@ -88,88 +88,3 @@ index cc2a8b4..70b2607 100644 emac: ethernet@1c30000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; -diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c -index 9918a57..e311483 100644 ---- a/drivers/spi/spi-sun6i.c -+++ b/drivers/spi/spi-sun6i.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -24,6 +25,7 @@ - #include - - #define SUN6I_FIFO_DEPTH 128 -+#define SUN8I_FIFO_DEPTH 64 - - #define SUN6I_GBL_CTL_REG 0x04 - #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) -@@ -90,6 +92,7 @@ struct sun6i_spi { - const u8 *tx_buf; - u8 *rx_buf; - int len; -+ unsigned long fifo_depth; - }; - - static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) -@@ -155,7 +158,9 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) - - static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) - { -- return SUN6I_FIFO_DEPTH - 1; -+ struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); -+ -+ return sspi->fifo_depth - 1; - } - - static int sun6i_spi_transfer_one(struct spi_master *master, -@@ -170,7 +175,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master, - u32 reg; - - /* We don't support transfer larger than the FIFO */ -- if (tfr->len > SUN6I_FIFO_DEPTH) -+ if (tfr->len > sspi->fifo_depth) - return -EINVAL; - - reinit_completion(&sspi->done); -@@ -265,7 +270,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master, - SUN6I_BURST_CTL_CNT_STC(tx_len)); - - /* Fill the TX FIFO */ -- sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH); -+ sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); - - /* Enable the interrupts */ - sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); -@@ -288,7 +293,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master, - goto out; - } - -- sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); -+ sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); - - out: - sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); -@@ -398,6 +403,8 @@ static int sun6i_spi_probe(struct platform_device *pdev) - } - - sspi->master = master; -+ sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); -+ - master->max_speed_hz = 100 * 1000 * 1000; - master->min_speed_hz = 3 * 1000; - master->set_cs = sun6i_spi_set_cs; -@@ -470,7 +477,8 @@ static int sun6i_spi_remove(struct platform_device *pdev) - } - - static const struct of_device_id sun6i_spi_match[] = { -- { .compatible = "allwinner,sun6i-a31-spi", }, -+ { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, -+ { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, - {} - }; - MODULE_DEVICE_TABLE(of, sun6i_spi_match); diff --git a/patch/kernel/sun8i-dev/spi-sun6i-allow-large-transfers.patch b/patch/kernel/sun8i-dev/spi-sun6i-allow-large-transfers.patch new file mode 100644 index 000000000..d66ed3dab --- /dev/null +++ b/patch/kernel/sun8i-dev/spi-sun6i-allow-large-transfers.patch @@ -0,0 +1,207 @@ +diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c +index 9918a57..36c50bd 100644 +--- a/drivers/spi/spi-sun6i.c ++++ b/drivers/spi/spi-sun6i.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -24,6 +25,7 @@ + #include + + #define SUN6I_FIFO_DEPTH 128 ++#define SUN8I_FIFO_DEPTH 64 + + #define SUN6I_GBL_CTL_REG 0x04 + #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) +@@ -44,6 +46,8 @@ + #define SUN6I_TFR_CTL_XCH BIT(31) + + #define SUN6I_INT_CTL_REG 0x10 ++#define SUN6I_INT_CTL_RF_FUL BIT(2) ++#define SUN6I_INT_CTL_TF_EMP BIT(5) + #define SUN6I_INT_CTL_RF_OVF BIT(8) + #define SUN6I_INT_CTL_TC BIT(12) + +@@ -66,11 +70,13 @@ + #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) + #define SUN6I_CLK_CTL_DRS BIT(12) + ++#define SUN6I_MAX_XFER_SIZE 0xffffff ++ + #define SUN6I_BURST_CNT_REG 0x30 +-#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff) ++#define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) + + #define SUN6I_XMIT_CNT_REG 0x34 +-#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff) ++#define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) + + #define SUN6I_BURST_CTL_CNT_REG 0x38 + #define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff) +@@ -90,6 +96,7 @@ struct sun6i_spi { + const u8 *tx_buf; + u8 *rx_buf; + int len; ++ unsigned long fifo_depth; + }; + + static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) +@@ -102,6 +109,31 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) + writel(value, sspi->base_addr + reg); + } + ++static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) ++{ ++ u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); ++ ++ reg >>= SUN6I_FIFO_STA_TF_CNT_BITS; ++ ++ return reg & SUN6I_FIFO_STA_TF_CNT_MASK; ++} ++ ++static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask) ++{ ++ u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); ++ ++ reg |= mask; ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); ++} ++ ++static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) ++{ ++ u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); ++ ++ reg &= ~mask; ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); ++} ++ + static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) + { + u32 reg, cnt; +@@ -124,10 +156,13 @@ static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) + + static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len) + { ++ u32 cnt; + u8 byte; + +- if (len > sspi->len) +- len = sspi->len; ++ /* See how much data we can fit */ ++ cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); ++ ++ len = min3(len, (int)cnt, sspi->len); + + while (len--) { + byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; +@@ -155,7 +190,7 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) + + static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) + { +- return SUN6I_FIFO_DEPTH - 1; ++ return SUN6I_MAX_XFER_SIZE - 1; + } + + static int sun6i_spi_transfer_one(struct spi_master *master, +@@ -169,8 +204,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master, + int ret = 0; + u32 reg; + +- /* We don't support transfer larger than the FIFO */ +- if (tfr->len > SUN6I_FIFO_DEPTH) ++ if (tfr->len > SUN6I_MAX_XFER_SIZE) + return -EINVAL; + + reinit_completion(&sspi->done); +@@ -265,10 +299,18 @@ static int sun6i_spi_transfer_one(struct spi_master *master, + SUN6I_BURST_CTL_CNT_STC(tx_len)); + + /* Fill the TX FIFO */ +- sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH); ++ sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); ++ ++// dev_warn(&master->dev, "%s: Filling FIFO with %lu bytes", dev_name(&spi->dev), sspi->fifo_depth); + + /* Enable the interrupts */ +- sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); ++ /* Only enable Tx FIFO interrupt if we really need it */ ++ if (tx_len > sspi->fifo_depth) ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, ++ SUN6I_INT_CTL_TC | SUN6I_INT_CTL_RF_FUL | SUN6I_INT_CTL_TF_EMP); ++ else ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, ++ SUN6I_INT_CTL_TC | SUN6I_INT_CTL_RF_FUL); + + /* Start the transfer */ + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); +@@ -288,7 +330,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master, + goto out; + } + +- sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); ++ dev_warn(&master->dev, ++ "%s: transfered %u bytes@%iHz for %i(%i)ms", ++ dev_name(&spi->dev), tfr->len, tfr->speed_hz, ++ jiffies_to_msecs(end - start), tx_time); + + out: + sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); +@@ -304,10 +349,33 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) + /* Transfer complete */ + if (status & SUN6I_INT_CTL_TC) { + sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); ++ sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); + complete(&sspi->done); + return IRQ_HANDLED; + } + ++ /* Receive FIFO Full */ ++ if (status & SUN6I_INT_CTL_RF_FUL) { ++ sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); ++ /* Only clear the interrupt _after_ draining the FIFO */ ++ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_FUL); ++ return IRQ_HANDLED; ++ } ++ ++ /* Transmit FIFO 3/4 empty */ ++ if (status & SUN6I_INT_CTL_TF_EMP) { ++ sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); ++ ++ if (!sspi->len) ++ /* nothing left to transmit */ ++ sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_EMP); ++ ++ /* Only clear the interrupt _after_ re-seeding the FIFO */ ++ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_EMP); ++ ++ return IRQ_HANDLED; ++ } ++ + return IRQ_NONE; + } + +@@ -398,6 +466,9 @@ static int sun6i_spi_probe(struct platform_device *pdev) + } + + sspi->master = master; ++ sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); ++ dev_warn(&pdev->dev, "sspi->fifo_depth = %lu", sspi->fifo_depth); ++ + master->max_speed_hz = 100 * 1000 * 1000; + master->min_speed_hz = 3 * 1000; + master->set_cs = sun6i_spi_set_cs; +@@ -470,7 +541,8 @@ static int sun6i_spi_remove(struct platform_device *pdev) + } + + static const struct of_device_id sun6i_spi_match[] = { +- { .compatible = "allwinner,sun6i-a31-spi", }, ++ { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, ++ { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, + {} + }; + MODULE_DEVICE_TABLE(of, sun6i_spi_match);