mirror of
https://github.com/Fishwaldo/build.git
synced 2025-03-16 03:41:26 +00:00
Merge branch 'master' into desktop
This commit is contained in:
armbianworker
commit
d9fe436c02
161 changed files with 30410 additions and 5923 deletions
|
|
@ -2,7 +2,7 @@
|
|||
BOARD_NAME="Odroid C1"
|
||||
BOARDFAMILY="meson8b"
|
||||
BOOTCONFIG="odroidc_config"
|
||||
KERNEL_TARGET="legacy,current"
|
||||
KERNEL_TARGET="legacy,current,dev"
|
||||
BUILD_DESKTOP=no
|
||||
BOOTSIZE="200"
|
||||
BOOTFS_TYPE="fat"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1 +0,0 @@
|
|||
linux-mvebu-current.config
|
||||
7277
config/kernel/linux-mvebu-dev.config
Normal file
7277
config/kernel/linux-mvebu-dev.config
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -6893,7 +6893,21 @@ CONFIG_UBIFS_FS_XATTR=y
|
|||
CONFIG_UBIFS_FS_SECURITY=y
|
||||
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_SQUASHFS is not set
|
||||
CONFIG_SQUASHFS=y
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
# CONFIG_SQUASHFS_XATTR is not set
|
||||
CONFIG_SQUASHFS_ZLIB=y
|
||||
CONFIG_SQUASHFS_LZ4=y
|
||||
CONFIG_SQUASHFS_LZO=y
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_SQUASHFS_ZSTD=y
|
||||
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
|
||||
# CONFIG_SQUASHFS_EMBEDDED is not set
|
||||
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_OMFS_FS is not set
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
linux-mvebu64-current.config
|
||||
7734
config/kernel/linux-mvebu64-dev.config
Normal file
7734
config/kernel/linux-mvebu64-dev.config
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 5.10.12 Kernel Configuration
|
||||
# Linux/arm 5.11.0 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
|
|
@ -261,7 +261,6 @@ CONFIG_MMU=y
|
|||
CONFIG_ARCH_MMAP_RND_BITS_MIN=8
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=16
|
||||
CONFIG_ARCH_MULTIPLATFORM=y
|
||||
# CONFIG_ARCH_EBSA110 is not set
|
||||
# CONFIG_ARCH_EP93XX is not set
|
||||
# CONFIG_ARCH_FOOTBRIDGE is not set
|
||||
# CONFIG_ARCH_IOP32X is not set
|
||||
|
|
@ -466,11 +465,9 @@ CONFIG_SCHED_HRTICK=y
|
|||
CONFIG_ARM_PATCH_IDIV=y
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
|
||||
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_ARCH_FLATMEM_ENABLE=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HIGHPTE=y
|
||||
CONFIG_CPU_SW_DOMAIN_PAN=y
|
||||
|
|
@ -483,6 +480,7 @@ CONFIG_ALIGNMENT_TRAP=y
|
|||
# CONFIG_PARAVIRT is not set
|
||||
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
|
||||
# CONFIG_XEN is not set
|
||||
# CONFIG_STACKPROTECTOR_PER_TASK is not set
|
||||
# end of Kernel Features
|
||||
|
||||
#
|
||||
|
|
@ -667,6 +665,7 @@ CONFIG_HAVE_ARCH_SECCOMP=y
|
|||
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
||||
CONFIG_SECCOMP=y
|
||||
CONFIG_SECCOMP_FILTER=y
|
||||
# CONFIG_SECCOMP_CACHE_DEBUG is not set
|
||||
CONFIG_HAVE_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
|
|
@ -693,6 +692,7 @@ CONFIG_STRICT_MODULE_RWX=y
|
|||
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
|
||||
# CONFIG_LOCK_EVENT_COUNTS is not set
|
||||
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
|
||||
#
|
||||
# GCOV-based kernel profiling
|
||||
|
|
@ -702,6 +702,9 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
|
|||
# end of GCOV-based kernel profiling
|
||||
|
||||
CONFIG_HAVE_GCC_PLUGINS=y
|
||||
CONFIG_GCC_PLUGINS=y
|
||||
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
|
||||
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
|
||||
# end of General architecture-dependent options
|
||||
|
||||
CONFIG_RT_MUTEXES=y
|
||||
|
|
@ -834,7 +837,8 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
|
|||
# CONFIG_IDLE_PAGE_TRACKING is not set
|
||||
CONFIG_FRAME_VECTOR=y
|
||||
# CONFIG_PERCPU_STATS is not set
|
||||
# CONFIG_GUP_BENCHMARK is not set
|
||||
# CONFIG_GUP_TEST is not set
|
||||
CONFIG_KMAP_LOCAL=y
|
||||
# end of Memory Management options
|
||||
|
||||
CONFIG_NET=y
|
||||
|
|
@ -1045,6 +1049,7 @@ CONFIG_NF_DUP_NETDEV=m
|
|||
CONFIG_NFT_DUP_NETDEV=m
|
||||
CONFIG_NFT_FWD_NETDEV=m
|
||||
CONFIG_NFT_FIB_NETDEV=m
|
||||
CONFIG_NFT_REJECT_NETDEV=m
|
||||
CONFIG_NF_FLOW_TABLE_INET=m
|
||||
CONFIG_NF_FLOW_TABLE=m
|
||||
CONFIG_NETFILTER_XTABLES=y
|
||||
|
|
@ -1350,6 +1355,7 @@ CONFIG_BRIDGE=m
|
|||
CONFIG_BRIDGE_IGMP_SNOOPING=y
|
||||
CONFIG_BRIDGE_VLAN_FILTERING=y
|
||||
# CONFIG_BRIDGE_MRP is not set
|
||||
# CONFIG_BRIDGE_CFM is not set
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
# CONFIG_NET_DSA is not set
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
@ -1496,9 +1502,7 @@ CONFIG_BATMAN_ADV_BLA=y
|
|||
CONFIG_BATMAN_ADV_DAT=y
|
||||
CONFIG_BATMAN_ADV_NC=y
|
||||
CONFIG_BATMAN_ADV_MCAST=y
|
||||
CONFIG_BATMAN_ADV_DEBUGFS=y
|
||||
# CONFIG_BATMAN_ADV_DEBUG is not set
|
||||
CONFIG_BATMAN_ADV_SYSFS=y
|
||||
# CONFIG_BATMAN_ADV_TRACING is not set
|
||||
CONFIG_OPENVSWITCH=m
|
||||
CONFIG_OPENVSWITCH_GRE=m
|
||||
|
|
@ -1673,7 +1677,6 @@ CONFIG_MAC80211_LEDS=y
|
|||
# CONFIG_MAC80211_MESSAGE_TRACING is not set
|
||||
# CONFIG_MAC80211_DEBUG_MENU is not set
|
||||
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
|
||||
# CONFIG_WIMAX is not set
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_RFKILL_LEDS=y
|
||||
CONFIG_RFKILL_INPUT=y
|
||||
|
|
@ -1796,6 +1799,13 @@ CONFIG_BLK_DEV=y
|
|||
CONFIG_BLK_DEV_NULL_BLK=m
|
||||
CONFIG_CDROM=m
|
||||
CONFIG_ZRAM=m
|
||||
CONFIG_ZRAM_DEF_COMP_LZORLE=y
|
||||
# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZO is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_842 is not set
|
||||
CONFIG_ZRAM_DEF_COMP="lzo-rle"
|
||||
CONFIG_ZRAM_WRITEBACK=y
|
||||
# CONFIG_ZRAM_MEMORY_TRACKING is not set
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
|
|
@ -1949,6 +1959,7 @@ CONFIG_DM_MULTIPATH=m
|
|||
CONFIG_DM_MULTIPATH_QL=m
|
||||
CONFIG_DM_MULTIPATH_ST=m
|
||||
CONFIG_DM_MULTIPATH_HST=m
|
||||
CONFIG_DM_MULTIPATH_IOA=m
|
||||
CONFIG_DM_DELAY=m
|
||||
CONFIG_DM_DUST=m
|
||||
# CONFIG_DM_INIT is not set
|
||||
|
|
@ -2003,6 +2014,7 @@ CONFIG_VETH=m
|
|||
CONFIG_VIRTIO_NET=m
|
||||
# CONFIG_NLMON is not set
|
||||
# CONFIG_NET_VRF is not set
|
||||
CONFIG_MHI_NET=m
|
||||
CONFIG_ATM_DRIVERS=y
|
||||
CONFIG_ATM_DUMMY=m
|
||||
CONFIG_ATM_TCP=m
|
||||
|
|
@ -2230,6 +2242,7 @@ CONFIG_USB_SIERRA_NET=m
|
|||
CONFIG_USB_VL600=m
|
||||
CONFIG_USB_NET_CH9200=m
|
||||
CONFIG_USB_NET_AQC111=m
|
||||
# CONFIG_USB_RTL8153_ECM is not set
|
||||
CONFIG_WLAN=y
|
||||
CONFIG_WLAN_VENDOR_ADMTEK=y
|
||||
CONFIG_ATH_COMMON=m
|
||||
|
|
@ -2360,6 +2373,7 @@ CONFIG_WLAN_VENDOR_TI=y
|
|||
CONFIG_RTL8723DU=m
|
||||
CONFIG_RTL8723DS=m
|
||||
CONFIG_RTL8822BU=m
|
||||
CONFIG_RTL8188EU=m
|
||||
CONFIG_RTL8821CU=m
|
||||
CONFIG_88XXAU=m
|
||||
CONFIG_RTL8192EU=m
|
||||
|
|
@ -2373,10 +2387,6 @@ CONFIG_WLAN_VENDOR_QUANTENNA=y
|
|||
# CONFIG_MAC80211_HWSIM is not set
|
||||
CONFIG_USB_NET_RNDIS_WLAN=m
|
||||
CONFIG_VIRT_WIFI=m
|
||||
|
||||
#
|
||||
# Enable WiMAX (Networking options) to see the WiMAX drivers
|
||||
#
|
||||
CONFIG_WAN=y
|
||||
CONFIG_HDLC=m
|
||||
CONFIG_HDLC_RAW=m
|
||||
|
|
@ -2388,8 +2398,6 @@ CONFIG_HDLC_PPP=m
|
|||
#
|
||||
# X.25/LAPB support is disabled
|
||||
#
|
||||
CONFIG_DLCI=m
|
||||
CONFIG_DLCI_MAX=8
|
||||
CONFIG_IEEE802154_DRIVERS=m
|
||||
# CONFIG_IEEE802154_FAKELB is not set
|
||||
# CONFIG_IEEE802154_AT86RF230 is not set
|
||||
|
|
@ -2411,7 +2419,6 @@ CONFIG_NET_FAILOVER=m
|
|||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_LEDS=m
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
CONFIG_INPUT_POLLDEV=m
|
||||
# CONFIG_INPUT_SPARSEKMAP is not set
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
|
||||
|
|
@ -2513,7 +2520,6 @@ CONFIG_JOYSTICK_FSIA6B=m
|
|||
CONFIG_INPUT_TABLET=y
|
||||
CONFIG_TABLET_USB_ACECAD=m
|
||||
CONFIG_TABLET_USB_AIPTEK=m
|
||||
CONFIG_TABLET_USB_GTCO=m
|
||||
CONFIG_TABLET_USB_HANWANG=m
|
||||
CONFIG_TABLET_USB_KBTAB=m
|
||||
# CONFIG_TABLET_USB_PEGASUS is not set
|
||||
|
|
@ -2604,6 +2610,7 @@ CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
|
|||
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
|
||||
CONFIG_TOUCHSCREEN_IQS5XX=m
|
||||
CONFIG_TOUCHSCREEN_ZINITIX=m
|
||||
CONFIG_TOUCHSCREEN_DWAV_USB_MT=m
|
||||
CONFIG_INPUT_MISC=y
|
||||
# CONFIG_INPUT_AD714X is not set
|
||||
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
|
||||
|
|
@ -2627,6 +2634,7 @@ CONFIG_INPUT_UINPUT=y
|
|||
# CONFIG_INPUT_PWM_BEEPER is not set
|
||||
# CONFIG_INPUT_PWM_VIBRA is not set
|
||||
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
|
||||
CONFIG_INPUT_DA7280_HAPTICS=m
|
||||
# CONFIG_INPUT_ADXL34X is not set
|
||||
# CONFIG_INPUT_IMS_PCU is not set
|
||||
CONFIG_INPUT_IQS269A=m
|
||||
|
|
@ -2733,6 +2741,8 @@ CONFIG_SERIAL_FSL_LINFLEXUART=m
|
|||
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
|
||||
# CONFIG_SERIAL_ST_ASC is not set
|
||||
CONFIG_SERIAL_SPRD=m
|
||||
CONFIG_SERIAL_LITEUART=m
|
||||
CONFIG_SERIAL_LITEUART_MAX_PORTS=1
|
||||
# end of Serial drivers
|
||||
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
|
|
@ -2907,6 +2917,7 @@ CONFIG_GENERIC_PINCONF=y
|
|||
# CONFIG_PINCTRL_SX150X is not set
|
||||
CONFIG_PINCTRL_STMFX=m
|
||||
# CONFIG_PINCTRL_OCELOT is not set
|
||||
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
|
||||
|
||||
#
|
||||
# Renesas pinctrl drivers
|
||||
|
|
@ -2921,7 +2932,6 @@ CONFIG_GPIOLIB=y
|
|||
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_CDEV=y
|
||||
CONFIG_GPIO_CDEV_V1=y
|
||||
|
||||
|
|
@ -2988,8 +2998,13 @@ CONFIG_GPIO_TQMX86=m
|
|||
#
|
||||
# end of USB GPIO expanders
|
||||
|
||||
#
|
||||
# Virtual GPIO drivers
|
||||
#
|
||||
CONFIG_GPIO_AGGREGATOR=m
|
||||
# CONFIG_GPIO_MOCKUP is not set
|
||||
# end of Virtual GPIO drivers
|
||||
|
||||
CONFIG_W1=m
|
||||
CONFIG_W1_CON=y
|
||||
|
||||
|
|
@ -3033,6 +3048,7 @@ CONFIG_POWER_RESET=y
|
|||
CONFIG_POWER_RESET_GPIO=y
|
||||
CONFIG_POWER_RESET_GPIO_RESTART=y
|
||||
# CONFIG_POWER_RESET_LTC2952 is not set
|
||||
# CONFIG_POWER_RESET_REGULATOR is not set
|
||||
# CONFIG_POWER_RESET_RESTART is not set
|
||||
# CONFIG_POWER_RESET_VERSATILE is not set
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
|
|
@ -3114,6 +3130,7 @@ CONFIG_SENSORS_AXI_FAN_CONTROL=m
|
|||
# CONFIG_SENSORS_ASPEED is not set
|
||||
# CONFIG_SENSORS_ATXP1 is not set
|
||||
CONFIG_SENSORS_CORSAIR_CPRO=m
|
||||
CONFIG_SENSORS_CORSAIR_PSU=m
|
||||
# CONFIG_SENSORS_DS620 is not set
|
||||
# CONFIG_SENSORS_DS1621 is not set
|
||||
# CONFIG_SENSORS_F71805F is not set
|
||||
|
|
@ -3137,6 +3154,7 @@ CONFIG_SENSORS_LTC2947=m
|
|||
CONFIG_SENSORS_LTC2947_I2C=m
|
||||
CONFIG_SENSORS_LTC2947_SPI=m
|
||||
# CONFIG_SENSORS_LTC2990 is not set
|
||||
CONFIG_SENSORS_LTC2992=m
|
||||
# CONFIG_SENSORS_LTC4151 is not set
|
||||
# CONFIG_SENSORS_LTC4215 is not set
|
||||
# CONFIG_SENSORS_LTC4222 is not set
|
||||
|
|
@ -3144,6 +3162,7 @@ CONFIG_SENSORS_LTC2947_SPI=m
|
|||
# CONFIG_SENSORS_LTC4260 is not set
|
||||
# CONFIG_SENSORS_LTC4261 is not set
|
||||
# CONFIG_SENSORS_MAX1111 is not set
|
||||
CONFIG_SENSORS_MAX127=m
|
||||
# CONFIG_SENSORS_MAX16065 is not set
|
||||
# CONFIG_SENSORS_MAX1619 is not set
|
||||
# CONFIG_SENSORS_MAX1668 is not set
|
||||
|
|
@ -3189,6 +3208,7 @@ CONFIG_SENSORS_OCC=m
|
|||
# CONFIG_SENSORS_PCF8591 is not set
|
||||
# CONFIG_PMBUS is not set
|
||||
CONFIG_SENSORS_PWM_FAN=y
|
||||
CONFIG_SENSORS_SBTSI=m
|
||||
# CONFIG_SENSORS_SHT15 is not set
|
||||
# CONFIG_SENSORS_SHT21 is not set
|
||||
# CONFIG_SENSORS_SHT3x is not set
|
||||
|
|
@ -3419,6 +3439,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
|||
# CONFIG_REGULATOR_BD70528 is not set
|
||||
CONFIG_REGULATOR_BD71828=m
|
||||
CONFIG_REGULATOR_CROS_EC=m
|
||||
CONFIG_REGULATOR_DA9121=m
|
||||
# CONFIG_REGULATOR_DA9210 is not set
|
||||
# CONFIG_REGULATOR_DA9211 is not set
|
||||
# CONFIG_REGULATOR_FAN53555 is not set
|
||||
|
|
@ -3452,6 +3473,7 @@ CONFIG_REGULATOR_MPQ7920=m
|
|||
# CONFIG_REGULATOR_MT6311 is not set
|
||||
CONFIG_REGULATOR_MT6360=m
|
||||
CONFIG_REGULATOR_PCA9450=m
|
||||
CONFIG_REGULATOR_PF8X00=m
|
||||
# CONFIG_REGULATOR_PFUZE100 is not set
|
||||
# CONFIG_REGULATOR_PV88060 is not set
|
||||
# CONFIG_REGULATOR_PV88080 is not set
|
||||
|
|
@ -3805,7 +3827,7 @@ CONFIG_VIDEO_CX25840=m
|
|||
# Camera sensor devices
|
||||
#
|
||||
CONFIG_VIDEO_APTINA_PLL=m
|
||||
CONFIG_VIDEO_SMIAPP_PLL=m
|
||||
CONFIG_VIDEO_CCS_PLL=m
|
||||
CONFIG_VIDEO_HI556=m
|
||||
CONFIG_VIDEO_IMX214=m
|
||||
CONFIG_VIDEO_IMX219=m
|
||||
|
|
@ -3814,6 +3836,7 @@ CONFIG_VIDEO_IMX274=m
|
|||
CONFIG_VIDEO_IMX290=m
|
||||
CONFIG_VIDEO_IMX319=m
|
||||
CONFIG_VIDEO_IMX355=m
|
||||
CONFIG_VIDEO_OV02A10=m
|
||||
CONFIG_VIDEO_OV2640=m
|
||||
CONFIG_VIDEO_OV2659=m
|
||||
CONFIG_VIDEO_OV2680=m
|
||||
|
|
@ -3853,7 +3876,7 @@ CONFIG_VIDEO_S5K6AA=m
|
|||
CONFIG_VIDEO_S5K6A3=m
|
||||
CONFIG_VIDEO_S5K4ECGX=m
|
||||
CONFIG_VIDEO_S5K5BAF=m
|
||||
CONFIG_VIDEO_SMIAPP=m
|
||||
CONFIG_VIDEO_CCS=m
|
||||
CONFIG_VIDEO_ET8EK8=m
|
||||
CONFIG_VIDEO_S5C73M3=m
|
||||
# end of Camera sensor devices
|
||||
|
|
@ -4136,6 +4159,7 @@ CONFIG_DRM_PANEL=y
|
|||
#
|
||||
# Display Panels
|
||||
#
|
||||
CONFIG_DRM_PANEL_ABT_Y030XX067A=m
|
||||
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
|
||||
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
|
||||
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
|
||||
|
|
@ -4157,6 +4181,7 @@ CONFIG_DRM_PANEL_SAMSUNG_LD9040=y
|
|||
# CONFIG_DRM_PANEL_LG_LG4573 is not set
|
||||
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
|
||||
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
|
||||
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
|
||||
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
|
||||
|
|
@ -4173,6 +4198,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y
|
|||
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y
|
||||
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
|
||||
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
|
||||
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
|
||||
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
|
||||
|
|
@ -4182,6 +4208,7 @@ CONFIG_DRM_PANEL_SITRONIX_ST7703=m
|
|||
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
|
||||
CONFIG_DRM_PANEL_SONY_ACX424AKP=m
|
||||
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
|
||||
CONFIG_DRM_PANEL_TDO_TL070WSH30=m
|
||||
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
|
||||
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
|
||||
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
|
||||
|
|
@ -4200,6 +4227,7 @@ CONFIG_DRM_PANEL_BRIDGE=y
|
|||
CONFIG_DRM_CHRONTEL_CH7033=m
|
||||
CONFIG_DRM_DISPLAY_CONNECTOR=m
|
||||
CONFIG_DRM_LONTIUM_LT9611=m
|
||||
CONFIG_DRM_LONTIUM_LT9611UXC=m
|
||||
CONFIG_DRM_LVDS_CODEC=m
|
||||
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
|
||||
CONFIG_DRM_NWL_MIPI_DSI=m
|
||||
|
|
@ -4222,6 +4250,7 @@ CONFIG_DRM_TI_TPD12S015=m
|
|||
CONFIG_DRM_ANALOGIX_ANX6345=m
|
||||
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
|
||||
CONFIG_DRM_ANALOGIX_DP=y
|
||||
CONFIG_DRM_ANALOGIX_ANX7625=m
|
||||
# CONFIG_DRM_I2C_ADV7511 is not set
|
||||
CONFIG_DRM_CDNS_MHDP8546=m
|
||||
# end of Display Interface Bridges
|
||||
|
|
@ -4235,6 +4264,7 @@ CONFIG_DRM_CDNS_MHDP8546=m
|
|||
# CONFIG_TINYDRM_ILI9225 is not set
|
||||
# CONFIG_TINYDRM_ILI9341 is not set
|
||||
CONFIG_TINYDRM_ILI9486=m
|
||||
CONFIG_TINYDRM_ILI9488_PIO=m
|
||||
# CONFIG_TINYDRM_MI0283QT is not set
|
||||
# CONFIG_TINYDRM_REPAPER is not set
|
||||
# CONFIG_TINYDRM_ST7586 is not set
|
||||
|
|
@ -4398,6 +4428,9 @@ CONFIG_SND_USB_TONEPORT=m
|
|||
CONFIG_SND_USB_VARIAX=m
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
|
||||
CONFIG_SND_SOC_ADI=m
|
||||
CONFIG_SND_SOC_ADI_AXI_I2S=m
|
||||
CONFIG_SND_SOC_ADI_AXI_SPDIF=m
|
||||
# CONFIG_SND_SOC_AMD_ACP is not set
|
||||
# CONFIG_SND_ATMEL_SOC is not set
|
||||
CONFIG_SND_BCM63XX_I2S_WHISTLER=m
|
||||
|
|
@ -4417,6 +4450,7 @@ CONFIG_SND_SOC_FSL_AUDMIX=m
|
|||
# CONFIG_SND_SOC_FSL_SPDIF is not set
|
||||
# CONFIG_SND_SOC_FSL_ESAI is not set
|
||||
CONFIG_SND_SOC_FSL_MICFIL=m
|
||||
CONFIG_SND_SOC_FSL_XCVR=m
|
||||
# CONFIG_SND_SOC_IMX_AUDMUX is not set
|
||||
# end of SoC Audio for Freescale CPUs
|
||||
|
||||
|
|
@ -4454,6 +4488,10 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
|
|||
#
|
||||
CONFIG_SND_SOC_WM_HUBS=m
|
||||
# CONFIG_SND_SOC_AC97_CODEC is not set
|
||||
CONFIG_SND_SOC_ADAU_UTILS=m
|
||||
CONFIG_SND_SOC_ADAU1372=m
|
||||
CONFIG_SND_SOC_ADAU1372_I2C=m
|
||||
CONFIG_SND_SOC_ADAU1372_SPI=m
|
||||
# CONFIG_SND_SOC_ADAU1701 is not set
|
||||
# CONFIG_SND_SOC_ADAU1761_I2C is not set
|
||||
# CONFIG_SND_SOC_ADAU1761_SPI is not set
|
||||
|
|
@ -4527,6 +4565,7 @@ CONFIG_SND_SOC_PCM3060_I2C=m
|
|||
CONFIG_SND_SOC_PCM3060_SPI=m
|
||||
# CONFIG_SND_SOC_PCM3168A_I2C is not set
|
||||
# CONFIG_SND_SOC_PCM3168A_SPI is not set
|
||||
CONFIG_SND_SOC_PCM5102A=m
|
||||
# CONFIG_SND_SOC_PCM512x_I2C is not set
|
||||
# CONFIG_SND_SOC_PCM512x_SPI is not set
|
||||
CONFIG_SND_SOC_RK3328=m
|
||||
|
|
@ -4534,6 +4573,7 @@ CONFIG_SND_SOC_RK3328=m
|
|||
CONFIG_SND_SOC_RT5631=m
|
||||
# CONFIG_SND_SOC_SGTL5000 is not set
|
||||
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
|
||||
CONFIG_SND_SOC_SIMPLE_MUX=m
|
||||
# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set
|
||||
CONFIG_SND_SOC_SPDIF=y
|
||||
# CONFIG_SND_SOC_SSM2305 is not set
|
||||
|
|
@ -4594,11 +4634,14 @@ CONFIG_SND_SOC_ZL38060=m
|
|||
# CONFIG_SND_SOC_MT6351 is not set
|
||||
CONFIG_SND_SOC_MT6358=m
|
||||
CONFIG_SND_SOC_MT6660=m
|
||||
CONFIG_SND_SOC_NAU8315=m
|
||||
# CONFIG_SND_SOC_NAU8540 is not set
|
||||
# CONFIG_SND_SOC_NAU8810 is not set
|
||||
CONFIG_SND_SOC_NAU8822=m
|
||||
# CONFIG_SND_SOC_NAU8824 is not set
|
||||
# CONFIG_SND_SOC_TPA6130A2 is not set
|
||||
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
|
||||
CONFIG_SND_SOC_LPASS_VA_MACRO=m
|
||||
# end of CODEC drivers
|
||||
|
||||
CONFIG_SND_SIMPLE_CARD_UTILS=y
|
||||
|
|
@ -4905,7 +4948,6 @@ CONFIG_USB_SERIAL_SIERRAWIRELESS=m
|
|||
CONFIG_USB_SERIAL_SYMBOL=m
|
||||
CONFIG_USB_SERIAL_TI=m
|
||||
CONFIG_USB_SERIAL_CYBERJACK=m
|
||||
CONFIG_USB_SERIAL_XIRCOM=m
|
||||
CONFIG_USB_SERIAL_WWAN=m
|
||||
CONFIG_USB_SERIAL_OPTION=m
|
||||
CONFIG_USB_SERIAL_OMNINET=m
|
||||
|
|
@ -5130,6 +5172,11 @@ CONFIG_LEDS_MAX8997=y
|
|||
# CONFIG_LEDS_TI_LMU_COMMON is not set
|
||||
CONFIG_LEDS_SGM3140=m
|
||||
|
||||
#
|
||||
# Flash and Torch LED drivers
|
||||
#
|
||||
CONFIG_LEDS_RT8515=m
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
#
|
||||
|
|
@ -5226,7 +5273,6 @@ CONFIG_RTC_DRV_S5M=y
|
|||
# CONFIG_RTC_DRV_MAX6916 is not set
|
||||
# CONFIG_RTC_DRV_R9701 is not set
|
||||
# CONFIG_RTC_DRV_RX4581 is not set
|
||||
# CONFIG_RTC_DRV_RX6110 is not set
|
||||
# CONFIG_RTC_DRV_RS5C348 is not set
|
||||
# CONFIG_RTC_DRV_MAX6902 is not set
|
||||
# CONFIG_RTC_DRV_PCF2123 is not set
|
||||
|
|
@ -5239,6 +5285,7 @@ CONFIG_RTC_I2C_AND_SPI=y
|
|||
# CONFIG_RTC_DRV_DS3232 is not set
|
||||
# CONFIG_RTC_DRV_PCF2127 is not set
|
||||
# CONFIG_RTC_DRV_RV3029C2 is not set
|
||||
# CONFIG_RTC_DRV_RX6110 is not set
|
||||
|
||||
#
|
||||
# Platform RTC drivers
|
||||
|
|
@ -5276,6 +5323,7 @@ CONFIG_RTC_DRV_S3C=y
|
|||
# HID Sensor RTC drivers
|
||||
#
|
||||
CONFIG_RTC_DRV_HID_SENSOR_TIME=m
|
||||
CONFIG_RTC_DRV_GOLDFISH=m
|
||||
CONFIG_DMADEVICES=y
|
||||
# CONFIG_DMADEVICES_DEBUG is not set
|
||||
|
||||
|
|
@ -5331,6 +5379,7 @@ CONFIG_VIRTIO_INPUT=m
|
|||
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
|
||||
CONFIG_VDPA=m
|
||||
CONFIG_VDPA_SIM=m
|
||||
CONFIG_VDPA_SIM_NET=m
|
||||
CONFIG_VHOST_IOTLB=m
|
||||
CONFIG_VHOST_RING=m
|
||||
CONFIG_VHOST=m
|
||||
|
|
@ -5494,6 +5543,7 @@ CONFIG_FIELDBUS_DEV=m
|
|||
CONFIG_HMS_ANYBUSS_BUS=m
|
||||
CONFIG_ARCX_ANYBUS_CONTROLLER=m
|
||||
CONFIG_HMS_PROFINET=m
|
||||
# CONFIG_WIMAX is not set
|
||||
CONFIG_WFX=m
|
||||
# CONFIG_GOLDFISH is not set
|
||||
CONFIG_CHROME_PLATFORMS=y
|
||||
|
|
@ -5525,13 +5575,19 @@ CONFIG_COMMON_CLK_MAX77686=y
|
|||
# CONFIG_COMMON_CLK_CDCE925 is not set
|
||||
# CONFIG_COMMON_CLK_CS2000_CP is not set
|
||||
CONFIG_COMMON_CLK_S2MPS11=y
|
||||
# CONFIG_CLK_QORIQ is not set
|
||||
# CONFIG_COMMON_CLK_PWM is not set
|
||||
# CONFIG_COMMON_CLK_VC5 is not set
|
||||
CONFIG_COMMON_CLK_BD718XX=m
|
||||
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
|
||||
CONFIG_COMMON_CLK_SAMSUNG=y
|
||||
CONFIG_EXYNOS_3250_COMMON_CLK=y
|
||||
CONFIG_EXYNOS_4_COMMON_CLK=y
|
||||
CONFIG_EXYNOS_5250_COMMON_CLK=y
|
||||
CONFIG_EXYNOS_5260_COMMON_CLK=y
|
||||
CONFIG_EXYNOS_5410_COMMON_CLK=y
|
||||
CONFIG_EXYNOS_5420_COMMON_CLK=y
|
||||
CONFIG_EXYNOS_AUDSS_CLK_CON=y
|
||||
CONFIG_EXYNOS_CLKOUT=m
|
||||
# CONFIG_HWSPINLOCK is not set
|
||||
|
||||
#
|
||||
|
|
@ -5589,11 +5645,6 @@ CONFIG_EXYNOS_IOMMU=y
|
|||
#
|
||||
# end of Amlogic SoC drivers
|
||||
|
||||
#
|
||||
# Aspeed SoC drivers
|
||||
#
|
||||
# end of Aspeed SoC drivers
|
||||
|
||||
#
|
||||
# Broadcom SoC drivers
|
||||
#
|
||||
|
|
@ -5612,6 +5663,13 @@ CONFIG_EXYNOS_IOMMU=y
|
|||
#
|
||||
# end of i.MX SoC drivers
|
||||
|
||||
#
|
||||
# Enable LiteX SoC Builder specific drivers
|
||||
#
|
||||
CONFIG_LITEX=y
|
||||
CONFIG_LITEX_SOC_CONTROLLER=m
|
||||
# end of Enable LiteX SoC Builder specific drivers
|
||||
|
||||
#
|
||||
# Qualcomm SoC drivers
|
||||
#
|
||||
|
|
@ -5670,6 +5728,7 @@ CONFIG_EXTCON_MAX8997=y
|
|||
# CONFIG_EXTCON_SM5502 is not set
|
||||
# CONFIG_EXTCON_USB_GPIO is not set
|
||||
# CONFIG_EXTCON_USBC_CROS_EC is not set
|
||||
CONFIG_EXTCON_USBC_TUSB320=m
|
||||
CONFIG_MEMORY=y
|
||||
CONFIG_DDR=y
|
||||
# CONFIG_ARM_PL172_MPMC is not set
|
||||
|
|
@ -5772,6 +5831,7 @@ CONFIG_MAX1241=m
|
|||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
# CONFIG_MCP3911 is not set
|
||||
CONFIG_MEDIATEK_MT6360_ADC=m
|
||||
CONFIG_MP2629_ADC=m
|
||||
# CONFIG_NAU7802 is not set
|
||||
# CONFIG_SD_ADC_MODULATOR is not set
|
||||
|
|
@ -6156,8 +6216,10 @@ CONFIG_HID_SENSOR_TEMP=m
|
|||
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
CONFIG_PWM_ATMEL_TCB=m
|
||||
# CONFIG_PWM_CROS_EC is not set
|
||||
# CONFIG_PWM_FSL_FTM is not set
|
||||
CONFIG_PWM_GPIO=m
|
||||
CONFIG_PWM_IQS620A=m
|
||||
# CONFIG_PWM_PCA9685 is not set
|
||||
CONFIG_PWM_SAMSUNG=y
|
||||
|
|
@ -6441,24 +6503,6 @@ CONFIG_EROFS_FS_XATTR=y
|
|||
CONFIG_EROFS_FS_POSIX_ACL=y
|
||||
CONFIG_EROFS_FS_SECURITY=y
|
||||
# CONFIG_EROFS_FS_ZIP is not set
|
||||
CONFIG_AUFS_FS=m
|
||||
CONFIG_AUFS_BRANCH_MAX_127=y
|
||||
# CONFIG_AUFS_BRANCH_MAX_511 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_1023 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_32767 is not set
|
||||
CONFIG_AUFS_SBILIST=y
|
||||
# CONFIG_AUFS_HNOTIFY is not set
|
||||
# CONFIG_AUFS_EXPORT is not set
|
||||
# CONFIG_AUFS_XATTR is not set
|
||||
# CONFIG_AUFS_FHSM is not set
|
||||
# CONFIG_AUFS_RDU is not set
|
||||
# CONFIG_AUFS_DIRREN is not set
|
||||
# CONFIG_AUFS_SHWH is not set
|
||||
# CONFIG_AUFS_BR_RAMFS is not set
|
||||
# CONFIG_AUFS_BR_FUSE is not set
|
||||
CONFIG_AUFS_BR_HFSPLUS=y
|
||||
CONFIG_AUFS_BDEV_LOOP=y
|
||||
# CONFIG_AUFS_DEBUG is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=m
|
||||
CONFIG_NFS_V2=m
|
||||
|
|
@ -6512,6 +6556,7 @@ CONFIG_CIFS_XATTR=y
|
|||
CONFIG_CIFS_POSIX=y
|
||||
# CONFIG_CIFS_DEBUG is not set
|
||||
CONFIG_CIFS_DFS_UPCALL=y
|
||||
# CONFIG_CIFS_SWN_UPCALL is not set
|
||||
CONFIG_CIFS_FSCACHE=y
|
||||
# CONFIG_CODA_FS is not set
|
||||
# CONFIG_AFS_FS is not set
|
||||
|
|
@ -6627,6 +6672,9 @@ CONFIG_LSM="yama,loadpin,safesetid,integrity"
|
|||
# Memory initialization
|
||||
#
|
||||
CONFIG_INIT_STACK_NONE=y
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
|
||||
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
|
||||
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
|
||||
# end of Memory initialization
|
||||
|
|
@ -6950,6 +6998,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y
|
|||
# CONFIG_CMA_SIZE_SEL_MAX is not set
|
||||
CONFIG_CMA_ALIGNMENT=8
|
||||
# CONFIG_DMA_API_DEBUG is not set
|
||||
# CONFIG_DMA_MAP_BENCHMARK is not set
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_DQL=y
|
||||
|
|
@ -6982,6 +7031,8 @@ CONFIG_SBITMAP=y
|
|||
# CONFIG_STRING_SELFTEST is not set
|
||||
# end of Library routines
|
||||
|
||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
|
|
@ -7003,7 +7054,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
|
|||
#
|
||||
# Compile-time checks and compiler options
|
||||
#
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_FRAME_WARN=1024
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_HEADERS_INSTALL is not set
|
||||
|
|
@ -7040,8 +7090,10 @@ CONFIG_HAVE_ARCH_KGDB=y
|
|||
CONFIG_HAVE_DEBUG_KMEMLEAK=y
|
||||
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_HAVE_ARCH_KASAN=y
|
||||
CONFIG_CC_HAS_KASAN_GENERIC=y
|
||||
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
|
||||
# CONFIG_KASAN is not set
|
||||
# end of Memory Debugging
|
||||
|
||||
#
|
||||
|
|
@ -7122,9 +7174,9 @@ CONFIG_PROBE_EVENTS=y
|
|||
# CONFIG_RING_BUFFER_BENCHMARK is not set
|
||||
# CONFIG_TRACE_EVAL_MAP_FILE is not set
|
||||
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
|
||||
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
|
||||
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
|
||||
# CONFIG_STRICT_DEVMEM is not set
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 5.10.9 Kernel Configuration
|
||||
# Linux/arm 5.10.16 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
|
|
@ -2388,6 +2388,7 @@ CONFIG_WLAN_VENDOR_TI=y
|
|||
CONFIG_RTL8723DU=m
|
||||
CONFIG_RTL8723DS=m
|
||||
CONFIG_RTL8822BU=m
|
||||
CONFIG_RTL8188EU=m
|
||||
CONFIG_RTL8821CU=m
|
||||
CONFIG_88XXAU=m
|
||||
# CONFIG_RTL8192EU is not set
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
linux-rockchip-current.config
|
||||
7367
config/kernel/linux-rockchip-dev.config
Normal file
7367
config/kernel/linux-rockchip-dev.config
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm64 5.10.6 Kernel Configuration
|
||||
# Linux/arm64 5.10.16 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
|
|
@ -3234,6 +3234,7 @@ CONFIG_WILINK_PLATFORM_DATA=y
|
|||
CONFIG_RTL8723DU=m
|
||||
CONFIG_RTL8723DS=m
|
||||
CONFIG_RTL8822BU=m
|
||||
CONFIG_RTL8188EU=m
|
||||
CONFIG_RTL8821CU=m
|
||||
CONFIG_88XXAU=m
|
||||
# CONFIG_RTL8192EU is not set
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm64 5.10.6 Kernel Configuration
|
||||
# Linux/arm64 5.11.0 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
|
|
@ -294,6 +294,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y
|
|||
CONFIG_ARCH_SUNXI=y
|
||||
# CONFIG_ARCH_ALPINE is not set
|
||||
# CONFIG_ARCH_BCM2835 is not set
|
||||
# CONFIG_ARCH_BCM4908 is not set
|
||||
# CONFIG_ARCH_BCM_IPROC is not set
|
||||
# CONFIG_ARCH_BERLIN is not set
|
||||
# CONFIG_ARCH_BITMAIN is not set
|
||||
|
|
@ -397,11 +398,9 @@ CONFIG_HZ_250=y
|
|||
# CONFIG_HZ_1000 is not set
|
||||
CONFIG_HZ=250
|
||||
CONFIG_SCHED_HRTICK=y
|
||||
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
|
||||
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
CONFIG_HW_PERF_EVENTS=y
|
||||
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
|
||||
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
|
||||
|
|
@ -431,6 +430,7 @@ CONFIG_SETEND_EMULATION=y
|
|||
#
|
||||
CONFIG_ARM64_HW_AFDBM=y
|
||||
CONFIG_ARM64_PAN=y
|
||||
CONFIG_AS_HAS_LDAPR=y
|
||||
CONFIG_ARM64_LSE_ATOMICS=y
|
||||
CONFIG_ARM64_USE_LSE_ATOMICS=y
|
||||
CONFIG_ARM64_VHE=y
|
||||
|
|
@ -439,7 +439,6 @@ CONFIG_ARM64_VHE=y
|
|||
#
|
||||
# ARMv8.2 architectural features
|
||||
#
|
||||
CONFIG_ARM64_UAO=y
|
||||
# CONFIG_ARM64_PMEM is not set
|
||||
CONFIG_ARM64_RAS_EXTN=y
|
||||
CONFIG_ARM64_CNP=y
|
||||
|
|
@ -464,6 +463,7 @@ CONFIG_ARM64_TLB_RANGE=y
|
|||
#
|
||||
# ARMv8.5 architectural features
|
||||
#
|
||||
CONFIG_AS_HAS_ARMV8_5=y
|
||||
CONFIG_ARM64_BTI=y
|
||||
CONFIG_ARM64_E0PD=y
|
||||
CONFIG_ARCH_RANDOM=y
|
||||
|
|
@ -632,7 +632,6 @@ CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
|
|||
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
|
||||
CONFIG_HAVE_KVM_IRQ_BYPASS=y
|
||||
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
|
||||
CONFIG_KVM_ARM_PMU=y
|
||||
CONFIG_ARM64_CRYPTO=y
|
||||
CONFIG_CRYPTO_SHA256_ARM64=y
|
||||
CONFIG_CRYPTO_SHA512_ARM64=y
|
||||
|
|
@ -659,7 +658,6 @@ CONFIG_CRYPTO_AES_ARM64_BS=y
|
|||
#
|
||||
CONFIG_CRASH_CORE=y
|
||||
CONFIG_KEXEC_CORE=y
|
||||
CONFIG_SET_FS=y
|
||||
# CONFIG_KPROBES is not set
|
||||
CONFIG_JUMP_LABEL=y
|
||||
# CONFIG_STATIC_KEYS_SELFTEST is not set
|
||||
|
|
@ -698,6 +696,7 @@ CONFIG_HAVE_ARCH_SECCOMP=y
|
|||
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
||||
CONFIG_SECCOMP=y
|
||||
CONFIG_SECCOMP_FILTER=y
|
||||
# CONFIG_SECCOMP_CACHE_DEBUG is not set
|
||||
CONFIG_HAVE_ARCH_STACKLEAK=y
|
||||
CONFIG_HAVE_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
|
|
@ -705,6 +704,7 @@ CONFIG_STACKPROTECTOR_STRONG=y
|
|||
CONFIG_HAVE_CONTEXT_TRACKING=y
|
||||
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
|
||||
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_HAVE_MOVE_PUD=y
|
||||
CONFIG_HAVE_MOVE_PMD=y
|
||||
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_HAVE_ARCH_HUGE_VMAP=y
|
||||
|
|
@ -732,6 +732,8 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y
|
|||
# CONFIG_LOCK_EVENT_COUNTS is not set
|
||||
CONFIG_ARCH_HAS_RELR=y
|
||||
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
|
||||
|
||||
#
|
||||
# GCOV-based kernel profiling
|
||||
|
|
@ -741,6 +743,10 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
|
|||
# end of GCOV-based kernel profiling
|
||||
|
||||
CONFIG_HAVE_GCC_PLUGINS=y
|
||||
CONFIG_GCC_PLUGINS=y
|
||||
# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
|
||||
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
|
||||
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
|
||||
# end of General architecture-dependent options
|
||||
|
||||
CONFIG_RT_MUTEXES=y
|
||||
|
|
@ -901,7 +907,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
|
|||
CONFIG_ARCH_HAS_PTE_DEVMAP=y
|
||||
CONFIG_FRAME_VECTOR=y
|
||||
# CONFIG_PERCPU_STATS is not set
|
||||
# CONFIG_GUP_BENCHMARK is not set
|
||||
# CONFIG_GUP_TEST is not set
|
||||
# CONFIG_READ_ONLY_THP_FOR_FS is not set
|
||||
CONFIG_ARCH_HAS_PTE_SPECIAL=y
|
||||
# end of Memory Management options
|
||||
|
|
@ -1121,6 +1127,7 @@ CONFIG_NF_DUP_NETDEV=m
|
|||
CONFIG_NFT_DUP_NETDEV=m
|
||||
CONFIG_NFT_FWD_NETDEV=m
|
||||
CONFIG_NFT_FIB_NETDEV=m
|
||||
CONFIG_NFT_REJECT_NETDEV=m
|
||||
CONFIG_NF_FLOW_TABLE_INET=m
|
||||
CONFIG_NF_FLOW_TABLE=m
|
||||
CONFIG_NETFILTER_XTABLES=m
|
||||
|
|
@ -1430,6 +1437,7 @@ CONFIG_BRIDGE=m
|
|||
CONFIG_BRIDGE_IGMP_SNOOPING=y
|
||||
CONFIG_BRIDGE_VLAN_FILTERING=y
|
||||
# CONFIG_BRIDGE_MRP is not set
|
||||
# CONFIG_BRIDGE_CFM is not set
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
CONFIG_NET_DSA=m
|
||||
CONFIG_NET_DSA_TAG_8021Q=m
|
||||
|
|
@ -1437,7 +1445,9 @@ CONFIG_NET_DSA_TAG_AR9331=m
|
|||
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
|
||||
CONFIG_NET_DSA_TAG_BRCM=m
|
||||
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
|
||||
CONFIG_NET_DSA_TAG_HELLCREEK=m
|
||||
CONFIG_NET_DSA_TAG_GSWIP=m
|
||||
CONFIG_NET_DSA_TAG_DSA_COMMON=m
|
||||
CONFIG_NET_DSA_TAG_DSA=m
|
||||
CONFIG_NET_DSA_TAG_EDSA=m
|
||||
CONFIG_NET_DSA_TAG_MTK=m
|
||||
|
|
@ -1592,9 +1602,7 @@ CONFIG_BATMAN_ADV_BLA=y
|
|||
CONFIG_BATMAN_ADV_DAT=y
|
||||
CONFIG_BATMAN_ADV_NC=y
|
||||
CONFIG_BATMAN_ADV_MCAST=y
|
||||
CONFIG_BATMAN_ADV_DEBUGFS=y
|
||||
CONFIG_BATMAN_ADV_DEBUG=y
|
||||
CONFIG_BATMAN_ADV_SYSFS=y
|
||||
# CONFIG_BATMAN_ADV_TRACING is not set
|
||||
CONFIG_OPENVSWITCH=m
|
||||
CONFIG_OPENVSWITCH_GRE=m
|
||||
|
|
@ -1683,6 +1691,7 @@ CONFIG_CAN_CC770_ISA=m
|
|||
CONFIG_CAN_CC770_PLATFORM=m
|
||||
# CONFIG_CAN_IFI_CANFD is not set
|
||||
CONFIG_CAN_M_CAN=m
|
||||
CONFIG_CAN_M_CAN_PCI=m
|
||||
CONFIG_CAN_M_CAN_PLATFORM=m
|
||||
CONFIG_CAN_M_CAN_TCAN4X5X=m
|
||||
CONFIG_CAN_PEAK_PCIEFD=m
|
||||
|
|
@ -1816,8 +1825,6 @@ CONFIG_MAC80211_LEDS=y
|
|||
# CONFIG_MAC80211_MESSAGE_TRACING is not set
|
||||
# CONFIG_MAC80211_DEBUG_MENU is not set
|
||||
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
|
||||
CONFIG_WIMAX=m
|
||||
CONFIG_WIMAX_DEBUG_LEVEL=8
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_RFKILL_LEDS=y
|
||||
CONFIG_RFKILL_INPUT=y
|
||||
|
|
@ -1868,6 +1875,7 @@ CONFIG_NFC_NXP_NCI=m
|
|||
CONFIG_NFC_NXP_NCI_I2C=m
|
||||
CONFIG_NFC_S3FWRN5=m
|
||||
CONFIG_NFC_S3FWRN5_I2C=m
|
||||
CONFIG_NFC_S3FWRN82_UART=m
|
||||
CONFIG_NFC_ST95HF=m
|
||||
# end of Near Field Communication (NFC) devices
|
||||
|
||||
|
|
@ -2042,6 +2050,7 @@ CONFIG_SUNXI_RSB=m
|
|||
CONFIG_VEXPRESS_CONFIG=y
|
||||
CONFIG_MHI_BUS=m
|
||||
# CONFIG_MHI_BUS_DEBUG is not set
|
||||
CONFIG_MHI_BUS_PCI_GENERIC=m
|
||||
# end of Bus devices
|
||||
|
||||
CONFIG_CONNECTOR=m
|
||||
|
|
@ -2137,6 +2146,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
|
|||
#
|
||||
# ECC engine support
|
||||
#
|
||||
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
|
||||
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
|
||||
# end of ECC engine support
|
||||
# end of NAND
|
||||
|
||||
|
|
@ -2148,6 +2159,9 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
|
|||
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
|
||||
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
|
||||
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
|
||||
# CONFIG_MTD_UBI is not set
|
||||
CONFIG_MTD_HYPERBUS=m
|
||||
CONFIG_HBMC_AM654=m
|
||||
|
|
@ -2172,6 +2186,13 @@ CONFIG_BLK_DEV=y
|
|||
CONFIG_CDROM=m
|
||||
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
|
||||
CONFIG_ZRAM=m
|
||||
CONFIG_ZRAM_DEF_COMP_LZORLE=y
|
||||
# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZO is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_842 is not set
|
||||
CONFIG_ZRAM_DEF_COMP="lzo-rle"
|
||||
CONFIG_ZRAM_WRITEBACK=y
|
||||
# CONFIG_ZRAM_MEMORY_TRACKING is not set
|
||||
CONFIG_BLK_DEV_UMEM=m
|
||||
|
|
@ -2503,6 +2524,7 @@ CONFIG_DM_MULTIPATH=m
|
|||
CONFIG_DM_MULTIPATH_QL=m
|
||||
CONFIG_DM_MULTIPATH_ST=m
|
||||
# CONFIG_DM_MULTIPATH_HST is not set
|
||||
CONFIG_DM_MULTIPATH_IOA=m
|
||||
CONFIG_DM_DELAY=m
|
||||
CONFIG_DM_DUST=m
|
||||
CONFIG_DM_UEVENT=y
|
||||
|
|
@ -2567,6 +2589,7 @@ CONFIG_VETH=m
|
|||
CONFIG_VIRTIO_NET=m
|
||||
CONFIG_NLMON=m
|
||||
CONFIG_NET_VRF=m
|
||||
CONFIG_MHI_NET=m
|
||||
# CONFIG_ARCNET is not set
|
||||
CONFIG_ATM_DRIVERS=y
|
||||
CONFIG_ATM_DUMMY=m
|
||||
|
|
@ -2603,6 +2626,7 @@ CONFIG_B53_SRAB_DRIVER=m
|
|||
CONFIG_B53_SERDES=m
|
||||
CONFIG_NET_DSA_BCM_SF2=m
|
||||
CONFIG_NET_DSA_LOOP=m
|
||||
CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
|
||||
CONFIG_NET_DSA_LANTIQ_GSWIP=m
|
||||
CONFIG_NET_DSA_MT7530=m
|
||||
CONFIG_NET_DSA_MV88E6060=m
|
||||
|
|
@ -3016,8 +3040,8 @@ CONFIG_USB_SIERRA_NET=m
|
|||
CONFIG_USB_VL600=m
|
||||
CONFIG_USB_NET_CH9200=m
|
||||
CONFIG_USB_NET_AQC111=m
|
||||
# CONFIG_USB_RTL8153_ECM is not set
|
||||
CONFIG_WLAN=y
|
||||
CONFIG_WIRELESS_WDS=y
|
||||
# CONFIG_WLAN_VENDOR_ADMTEK is not set
|
||||
CONFIG_ATH_COMMON=m
|
||||
CONFIG_WLAN_VENDOR_ATH=y
|
||||
|
|
@ -3234,6 +3258,7 @@ CONFIG_WILINK_PLATFORM_DATA=y
|
|||
CONFIG_RTL8723DU=m
|
||||
CONFIG_RTL8723DS=m
|
||||
CONFIG_RTL8822BU=m
|
||||
CONFIG_RTL8188EU=m
|
||||
CONFIG_RTL8821CU=m
|
||||
CONFIG_88XXAU=m
|
||||
# CONFIG_RTL8192EU is not set
|
||||
|
|
@ -3249,15 +3274,6 @@ CONFIG_QTNFMAC_PCIE=m
|
|||
CONFIG_MAC80211_HWSIM=m
|
||||
CONFIG_USB_NET_RNDIS_WLAN=m
|
||||
CONFIG_VIRT_WIFI=m
|
||||
|
||||
#
|
||||
# WiMAX Wireless Broadband devices
|
||||
#
|
||||
CONFIG_WIMAX_I2400M=m
|
||||
CONFIG_WIMAX_I2400M_USB=m
|
||||
CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8
|
||||
# end of WiMAX Wireless Broadband devices
|
||||
|
||||
# CONFIG_WAN is not set
|
||||
CONFIG_IEEE802154_DRIVERS=m
|
||||
CONFIG_IEEE802154_FAKELB=m
|
||||
|
|
@ -3285,7 +3301,6 @@ CONFIG_NET_FAILOVER=m
|
|||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_LEDS=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
CONFIG_INPUT_POLLDEV=m
|
||||
# CONFIG_INPUT_SPARSEKMAP is not set
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
|
||||
|
|
@ -3516,6 +3531,7 @@ CONFIG_INPUT_UINPUT=m
|
|||
# CONFIG_INPUT_PWM_VIBRA is not set
|
||||
CONFIG_INPUT_RK805_PWRKEY=y
|
||||
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
|
||||
CONFIG_INPUT_DA7280_HAPTICS=m
|
||||
# CONFIG_INPUT_ADXL34X is not set
|
||||
# CONFIG_INPUT_IMS_PCU is not set
|
||||
# CONFIG_INPUT_IQS269A is not set
|
||||
|
|
@ -3620,6 +3636,7 @@ CONFIG_SERIAL_SC16IS7XX_CORE=m
|
|||
CONFIG_SERIAL_SC16IS7XX=m
|
||||
CONFIG_SERIAL_SC16IS7XX_I2C=y
|
||||
CONFIG_SERIAL_SC16IS7XX_SPI=y
|
||||
CONFIG_SERIAL_BCM63XX=m
|
||||
CONFIG_SERIAL_ALTERA_JTAGUART=m
|
||||
CONFIG_SERIAL_ALTERA_UART=m
|
||||
CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
|
||||
|
|
@ -3635,6 +3652,8 @@ CONFIG_SERIAL_FSL_LPUART=m
|
|||
CONFIG_SERIAL_FSL_LINFLEXUART=m
|
||||
CONFIG_SERIAL_CONEXANT_DIGICOLOR=m
|
||||
CONFIG_SERIAL_SPRD=m
|
||||
CONFIG_SERIAL_LITEUART=m
|
||||
CONFIG_SERIAL_LITEUART_MAX_PORTS=1
|
||||
# end of Serial drivers
|
||||
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
|
|
@ -3644,7 +3663,6 @@ CONFIG_CYCLADES=m
|
|||
# CONFIG_CYZ_INTR is not set
|
||||
CONFIG_MOXA_INTELLIO=m
|
||||
CONFIG_MOXA_SMARTIO=m
|
||||
CONFIG_SYNCLINKMP=m
|
||||
CONFIG_SYNCLINK_GT=m
|
||||
CONFIG_ISI=m
|
||||
CONFIG_N_HDLC=m
|
||||
|
|
@ -3782,6 +3800,7 @@ CONFIG_I2C_SLAVE_EEPROM=m
|
|||
CONFIG_I3C=m
|
||||
CONFIG_CDNS_I3C_MASTER=m
|
||||
CONFIG_DW_I3C_MASTER=m
|
||||
CONFIG_MIPI_I3C_HCI=m
|
||||
CONFIG_SPI=y
|
||||
# CONFIG_SPI_DEBUG is not set
|
||||
CONFIG_SPI_MASTER=y
|
||||
|
|
@ -3859,6 +3878,7 @@ CONFIG_DP83640_PHY=m
|
|||
CONFIG_PTP_1588_CLOCK_INES=m
|
||||
CONFIG_PTP_1588_CLOCK_IDT82P33=m
|
||||
CONFIG_PTP_1588_CLOCK_IDTCM=m
|
||||
CONFIG_PTP_1588_CLOCK_OCP=m
|
||||
# end of PTP clock support
|
||||
|
||||
CONFIG_PINCTRL=y
|
||||
|
|
@ -3878,6 +3898,7 @@ CONFIG_PINCTRL_STMFX=m
|
|||
CONFIG_PINCTRL_MAX77620=y
|
||||
CONFIG_PINCTRL_RK805=y
|
||||
# CONFIG_PINCTRL_OCELOT is not set
|
||||
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
|
||||
|
||||
#
|
||||
# Renesas pinctrl drivers
|
||||
|
|
@ -4001,8 +4022,13 @@ CONFIG_GPIO_XRA1403=m
|
|||
#
|
||||
# end of USB GPIO expanders
|
||||
|
||||
#
|
||||
# Virtual GPIO drivers
|
||||
#
|
||||
# CONFIG_GPIO_AGGREGATOR is not set
|
||||
CONFIG_GPIO_MOCKUP=m
|
||||
# end of Virtual GPIO drivers
|
||||
|
||||
CONFIG_W1=m
|
||||
CONFIG_W1_CON=y
|
||||
|
||||
|
|
@ -4047,6 +4073,7 @@ CONFIG_POWER_RESET_BRCMSTB=y
|
|||
# CONFIG_POWER_RESET_GPIO is not set
|
||||
# CONFIG_POWER_RESET_GPIO_RESTART is not set
|
||||
# CONFIG_POWER_RESET_LTC2952 is not set
|
||||
# CONFIG_POWER_RESET_REGULATOR is not set
|
||||
# CONFIG_POWER_RESET_RESTART is not set
|
||||
CONFIG_POWER_RESET_VEXPRESS=y
|
||||
CONFIG_POWER_RESET_XGENE=y
|
||||
|
|
@ -4135,6 +4162,7 @@ CONFIG_SENSORS_ARM_SCPI=m
|
|||
CONFIG_SENSORS_ASPEED=m
|
||||
CONFIG_SENSORS_ATXP1=m
|
||||
# CONFIG_SENSORS_CORSAIR_CPRO is not set
|
||||
CONFIG_SENSORS_CORSAIR_PSU=m
|
||||
CONFIG_SENSORS_DRIVETEMP=m
|
||||
CONFIG_SENSORS_DS620=m
|
||||
CONFIG_SENSORS_DS1621=m
|
||||
|
|
@ -4159,6 +4187,7 @@ CONFIG_SENSORS_LTC2947=m
|
|||
CONFIG_SENSORS_LTC2947_I2C=m
|
||||
CONFIG_SENSORS_LTC2947_SPI=m
|
||||
CONFIG_SENSORS_LTC2990=m
|
||||
CONFIG_SENSORS_LTC2992=m
|
||||
CONFIG_SENSORS_LTC4151=m
|
||||
CONFIG_SENSORS_LTC4215=m
|
||||
CONFIG_SENSORS_LTC4222=m
|
||||
|
|
@ -4166,6 +4195,7 @@ CONFIG_SENSORS_LTC4245=m
|
|||
CONFIG_SENSORS_LTC4260=m
|
||||
CONFIG_SENSORS_LTC4261=m
|
||||
CONFIG_SENSORS_MAX1111=m
|
||||
CONFIG_SENSORS_MAX127=m
|
||||
CONFIG_SENSORS_MAX16065=m
|
||||
CONFIG_SENSORS_MAX1619=m
|
||||
CONFIG_SENSORS_MAX1668=m
|
||||
|
|
@ -4232,7 +4262,9 @@ CONFIG_SENSORS_MAX31785=m
|
|||
CONFIG_SENSORS_MAX34440=m
|
||||
CONFIG_SENSORS_MAX8688=m
|
||||
# CONFIG_SENSORS_MP2975 is not set
|
||||
CONFIG_SENSORS_PM6764TR=m
|
||||
CONFIG_SENSORS_PXE1610=m
|
||||
CONFIG_SENSORS_Q54SJ108A2=m
|
||||
CONFIG_SENSORS_TPS40422=m
|
||||
CONFIG_SENSORS_TPS53679=m
|
||||
CONFIG_SENSORS_UCD9000=m
|
||||
|
|
@ -4240,6 +4272,7 @@ CONFIG_SENSORS_UCD9200=m
|
|||
CONFIG_SENSORS_XDPE122=m
|
||||
CONFIG_SENSORS_ZL6100=m
|
||||
CONFIG_SENSORS_PWM_FAN=m
|
||||
CONFIG_SENSORS_SBTSI=m
|
||||
CONFIG_SENSORS_SHT15=m
|
||||
CONFIG_SENSORS_SHT21=m
|
||||
CONFIG_SENSORS_SHT3x=m
|
||||
|
|
@ -4418,6 +4451,7 @@ CONFIG_MFD_CROS_EC_DEV=y
|
|||
# CONFIG_HTC_I2CPLD is not set
|
||||
# CONFIG_LPC_ICH is not set
|
||||
# CONFIG_LPC_SCH is not set
|
||||
CONFIG_MFD_INTEL_PMT=m
|
||||
CONFIG_MFD_IQS62X=m
|
||||
# CONFIG_MFD_JANZ_CMODIO is not set
|
||||
# CONFIG_MFD_KEMPLD is not set
|
||||
|
|
@ -4516,6 +4550,7 @@ CONFIG_REGULATOR_AXP20X=m
|
|||
CONFIG_REGULATOR_BD70528=m
|
||||
CONFIG_REGULATOR_BD71828=m
|
||||
# CONFIG_REGULATOR_CROS_EC is not set
|
||||
CONFIG_REGULATOR_DA9121=m
|
||||
# CONFIG_REGULATOR_DA9210 is not set
|
||||
# CONFIG_REGULATOR_DA9211 is not set
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
|
|
@ -4544,6 +4579,7 @@ CONFIG_REGULATOR_MP886X=m
|
|||
CONFIG_REGULATOR_MPQ7920=m
|
||||
# CONFIG_REGULATOR_MT6311 is not set
|
||||
# CONFIG_REGULATOR_PCA9450 is not set
|
||||
CONFIG_REGULATOR_PF8X00=m
|
||||
# CONFIG_REGULATOR_PFUZE100 is not set
|
||||
# CONFIG_REGULATOR_PV88060 is not set
|
||||
# CONFIG_REGULATOR_PV88080 is not set
|
||||
|
|
@ -4897,6 +4933,7 @@ CONFIG_SMS_SIANO_RC=y
|
|||
# CONFIG_V4L_PLATFORM_DRIVERS is not set
|
||||
CONFIG_V4L_MEM2MEM_DRIVERS=y
|
||||
# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
|
||||
CONFIG_VIDEO_MESON_GE2D=m
|
||||
CONFIG_VIDEO_ROCKCHIP_RGA=m
|
||||
CONFIG_VIDEO_SUN8I_DEINTERLACE=m
|
||||
CONFIG_VIDEO_SUN8I_ROTATE=m
|
||||
|
|
@ -5030,7 +5067,7 @@ CONFIG_VIDEO_ST_MIPID02=m
|
|||
# Camera sensor devices
|
||||
#
|
||||
CONFIG_VIDEO_APTINA_PLL=m
|
||||
CONFIG_VIDEO_SMIAPP_PLL=m
|
||||
CONFIG_VIDEO_CCS_PLL=m
|
||||
CONFIG_VIDEO_HI556=m
|
||||
CONFIG_VIDEO_IMX214=m
|
||||
CONFIG_VIDEO_IMX219=m
|
||||
|
|
@ -5039,6 +5076,7 @@ CONFIG_VIDEO_IMX274=m
|
|||
CONFIG_VIDEO_IMX290=m
|
||||
CONFIG_VIDEO_IMX319=m
|
||||
CONFIG_VIDEO_IMX355=m
|
||||
CONFIG_VIDEO_OV02A10=m
|
||||
CONFIG_VIDEO_OV2640=m
|
||||
CONFIG_VIDEO_OV2659=m
|
||||
CONFIG_VIDEO_OV2680=m
|
||||
|
|
@ -5078,7 +5116,7 @@ CONFIG_VIDEO_S5K6AA=m
|
|||
CONFIG_VIDEO_S5K6A3=m
|
||||
CONFIG_VIDEO_S5K4ECGX=m
|
||||
CONFIG_VIDEO_S5K5BAF=m
|
||||
CONFIG_VIDEO_SMIAPP=m
|
||||
CONFIG_VIDEO_CCS=m
|
||||
CONFIG_VIDEO_ET8EK8=m
|
||||
CONFIG_VIDEO_S5C73M3=m
|
||||
# end of Camera sensor devices
|
||||
|
|
@ -5347,7 +5385,6 @@ CONFIG_DRM_FBDEV_OVERALLOC=100
|
|||
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
|
||||
CONFIG_DRM_DP_CEC=y
|
||||
CONFIG_DRM_TTM=m
|
||||
CONFIG_DRM_TTM_DMA_PAGE_POOL=y
|
||||
CONFIG_DRM_VRAM_HELPER=m
|
||||
CONFIG_DRM_TTM_HELPER=m
|
||||
CONFIG_DRM_GEM_CMA_HELPER=y
|
||||
|
|
@ -5408,6 +5445,7 @@ CONFIG_DRM_PANEL=y
|
|||
#
|
||||
# Display Panels
|
||||
#
|
||||
CONFIG_DRM_PANEL_ABT_Y030XX067A=m
|
||||
CONFIG_DRM_PANEL_ARM_VERSATILE=m
|
||||
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
|
||||
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
|
||||
|
|
@ -5429,6 +5467,7 @@ CONFIG_DRM_PANEL_LG_LB035Q02=m
|
|||
# CONFIG_DRM_PANEL_LG_LG4573 is not set
|
||||
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
|
||||
# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
|
||||
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
|
||||
|
|
@ -5445,6 +5484,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
|
|||
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
|
||||
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
|
||||
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
|
||||
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
||||
|
|
@ -5454,6 +5494,7 @@ CONFIG_DRM_PANEL_SITRONIX_ST7701=m
|
|||
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
|
||||
CONFIG_DRM_PANEL_SONY_ACX424AKP=m
|
||||
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
|
||||
CONFIG_DRM_PANEL_TDO_TL070WSH30=m
|
||||
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
|
||||
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
|
||||
CONFIG_DRM_PANEL_TPO_TPG110=m
|
||||
|
|
@ -5472,6 +5513,7 @@ CONFIG_DRM_CDNS_DSI=m
|
|||
# CONFIG_DRM_CHRONTEL_CH7033 is not set
|
||||
CONFIG_DRM_DISPLAY_CONNECTOR=m
|
||||
# CONFIG_DRM_LONTIUM_LT9611 is not set
|
||||
CONFIG_DRM_LONTIUM_LT9611UXC=m
|
||||
CONFIG_DRM_LVDS_CODEC=m
|
||||
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
|
||||
# CONFIG_DRM_NWL_MIPI_DSI is not set
|
||||
|
|
@ -5494,6 +5536,7 @@ CONFIG_DRM_TI_TPD12S015=m
|
|||
CONFIG_DRM_ANALOGIX_ANX6345=m
|
||||
CONFIG_DRM_ANALOGIX_ANX78XX=m
|
||||
CONFIG_DRM_ANALOGIX_DP=m
|
||||
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
|
||||
CONFIG_DRM_I2C_ADV7511=m
|
||||
# CONFIG_DRM_I2C_ADV7511_AUDIO is not set
|
||||
CONFIG_DRM_I2C_ADV7511_CEC=y
|
||||
|
|
@ -5792,6 +5835,9 @@ CONFIG_SND_USB_TONEPORT=m
|
|||
CONFIG_SND_USB_VARIAX=m
|
||||
CONFIG_SND_SOC=m
|
||||
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
|
||||
CONFIG_SND_SOC_ADI=m
|
||||
CONFIG_SND_SOC_ADI_AXI_I2S=m
|
||||
CONFIG_SND_SOC_ADI_AXI_SPDIF=m
|
||||
# CONFIG_SND_SOC_AMD_ACP is not set
|
||||
# CONFIG_SND_ATMEL_SOC is not set
|
||||
CONFIG_SND_BCM63XX_I2S_WHISTLER=m
|
||||
|
|
@ -5812,6 +5858,7 @@ CONFIG_SND_SOC_FSL_AUDMIX=m
|
|||
# CONFIG_SND_SOC_FSL_SPDIF is not set
|
||||
# CONFIG_SND_SOC_FSL_ESAI is not set
|
||||
CONFIG_SND_SOC_FSL_MICFIL=m
|
||||
CONFIG_SND_SOC_FSL_XCVR=m
|
||||
# CONFIG_SND_SOC_IMX_AUDMUX is not set
|
||||
# end of SoC Audio for Freescale CPUs
|
||||
|
||||
|
|
@ -5882,6 +5929,10 @@ CONFIG_SND_SOC_I2C_AND_SPI=m
|
|||
# CODEC drivers
|
||||
#
|
||||
# CONFIG_SND_SOC_AC97_CODEC is not set
|
||||
CONFIG_SND_SOC_ADAU_UTILS=m
|
||||
CONFIG_SND_SOC_ADAU1372=m
|
||||
CONFIG_SND_SOC_ADAU1372_I2C=m
|
||||
CONFIG_SND_SOC_ADAU1372_SPI=m
|
||||
# CONFIG_SND_SOC_ADAU1701 is not set
|
||||
# CONFIG_SND_SOC_ADAU1761_I2C is not set
|
||||
# CONFIG_SND_SOC_ADAU1761_SPI is not set
|
||||
|
|
@ -5974,6 +6025,7 @@ CONFIG_SND_SOC_RT5645=m
|
|||
CONFIG_SND_SOC_RT5651=m
|
||||
CONFIG_SND_SOC_SGTL5000=m
|
||||
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
|
||||
CONFIG_SND_SOC_SIMPLE_MUX=m
|
||||
CONFIG_SND_SOC_SIRF_AUDIO_CODEC=m
|
||||
CONFIG_SND_SOC_SPDIF=m
|
||||
CONFIG_SND_SOC_SSM2305=m
|
||||
|
|
@ -6037,11 +6089,14 @@ CONFIG_SND_SOC_MAX9759=m
|
|||
CONFIG_SND_SOC_MT6351=m
|
||||
CONFIG_SND_SOC_MT6358=m
|
||||
CONFIG_SND_SOC_MT6660=m
|
||||
CONFIG_SND_SOC_NAU8315=m
|
||||
CONFIG_SND_SOC_NAU8540=m
|
||||
CONFIG_SND_SOC_NAU8810=m
|
||||
CONFIG_SND_SOC_NAU8822=m
|
||||
CONFIG_SND_SOC_NAU8824=m
|
||||
CONFIG_SND_SOC_TPA6130A2=m
|
||||
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
|
||||
CONFIG_SND_SOC_LPASS_VA_MACRO=m
|
||||
# end of CODEC drivers
|
||||
|
||||
CONFIG_SND_SIMPLE_CARD_UTILS=m
|
||||
|
|
@ -6378,7 +6433,6 @@ CONFIG_USB_SERIAL_SIERRAWIRELESS=m
|
|||
CONFIG_USB_SERIAL_SYMBOL=m
|
||||
CONFIG_USB_SERIAL_TI=m
|
||||
CONFIG_USB_SERIAL_CYBERJACK=m
|
||||
CONFIG_USB_SERIAL_XIRCOM=m
|
||||
CONFIG_USB_SERIAL_WWAN=m
|
||||
CONFIG_USB_SERIAL_OPTION=m
|
||||
CONFIG_USB_SERIAL_OMNINET=m
|
||||
|
|
@ -6678,6 +6732,10 @@ CONFIG_LEDS_USER=y
|
|||
# CONFIG_LEDS_SPI_BYTE is not set
|
||||
# CONFIG_LEDS_TI_LMU_COMMON is not set
|
||||
|
||||
#
|
||||
# Flash and Torch LED drivers
|
||||
#
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
#
|
||||
|
|
@ -6786,7 +6844,6 @@ CONFIG_RTC_DRV_DS1390=m
|
|||
CONFIG_RTC_DRV_MAX6916=m
|
||||
CONFIG_RTC_DRV_R9701=m
|
||||
CONFIG_RTC_DRV_RX4581=m
|
||||
CONFIG_RTC_DRV_RX6110=m
|
||||
CONFIG_RTC_DRV_RS5C348=m
|
||||
CONFIG_RTC_DRV_MAX6902=m
|
||||
CONFIG_RTC_DRV_PCF2123=m
|
||||
|
|
@ -6801,6 +6858,7 @@ CONFIG_RTC_DRV_DS3232_HWMON=y
|
|||
CONFIG_RTC_DRV_PCF2127=m
|
||||
CONFIG_RTC_DRV_RV3029C2=m
|
||||
CONFIG_RTC_DRV_RV3029_HWMON=y
|
||||
CONFIG_RTC_DRV_RX6110=m
|
||||
|
||||
#
|
||||
# Platform RTC drivers
|
||||
|
|
@ -6838,6 +6896,7 @@ CONFIG_RTC_DRV_CADENCE=m
|
|||
# HID Sensor RTC drivers
|
||||
#
|
||||
CONFIG_RTC_DRV_HID_SENSOR_TIME=m
|
||||
CONFIG_RTC_DRV_GOLDFISH=m
|
||||
CONFIG_DMADEVICES=y
|
||||
# CONFIG_DMADEVICES_DEBUG is not set
|
||||
|
||||
|
|
@ -6922,6 +6981,7 @@ CONFIG_VIRTIO_MMIO=y
|
|||
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
|
||||
CONFIG_VDPA=m
|
||||
CONFIG_VDPA_SIM=m
|
||||
CONFIG_VDPA_SIM_NET=m
|
||||
CONFIG_IFCVF=m
|
||||
CONFIG_VHOST_IOTLB=m
|
||||
CONFIG_VHOST_RING=m
|
||||
|
|
@ -7045,7 +7105,6 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m
|
|||
CONFIG_VIDEO_SUNXI=y
|
||||
CONFIG_VIDEO_SUNXI_CEDRUS=m
|
||||
# CONFIG_VIDEO_ZORAN is not set
|
||||
CONFIG_VIDEO_ROCKCHIP_ISP1=m
|
||||
|
||||
#
|
||||
# Android
|
||||
|
|
@ -7107,6 +7166,11 @@ CONFIG_HMS_ANYBUSS_BUS=m
|
|||
# CONFIG_HMS_PROFINET is not set
|
||||
# CONFIG_KPC2000 is not set
|
||||
# CONFIG_QLGE is not set
|
||||
CONFIG_WIMAX=m
|
||||
CONFIG_WIMAX_DEBUG_LEVEL=8
|
||||
CONFIG_WIMAX_I2400M=m
|
||||
CONFIG_WIMAX_I2400M_USB=m
|
||||
CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8
|
||||
CONFIG_WFX=m
|
||||
# CONFIG_SPMI_HISI3670 is not set
|
||||
# CONFIG_MFD_HI6421_SPMI is not set
|
||||
|
|
@ -7142,7 +7206,6 @@ CONFIG_COMMON_CLK_SI544=m
|
|||
# CONFIG_COMMON_CLK_CDCE925 is not set
|
||||
CONFIG_COMMON_CLK_CS2000_CP=y
|
||||
CONFIG_COMMON_CLK_S2MPS11=y
|
||||
CONFIG_CLK_QORIQ=y
|
||||
CONFIG_COMMON_CLK_XGENE=y
|
||||
CONFIG_COMMON_CLK_PWM=y
|
||||
# CONFIG_COMMON_CLK_VC5 is not set
|
||||
|
|
@ -7170,11 +7233,6 @@ CONFIG_COMMON_CLK_G12A=y
|
|||
|
||||
CONFIG_COMMON_CLK_ROCKCHIP=y
|
||||
CONFIG_CLK_PX30=y
|
||||
CONFIG_CLK_RV110X=y
|
||||
CONFIG_CLK_RK3036=y
|
||||
CONFIG_CLK_RK312X=y
|
||||
CONFIG_CLK_RK3188=y
|
||||
CONFIG_CLK_RK322X=y
|
||||
CONFIG_CLK_RK3308=y
|
||||
CONFIG_CLK_RK3328=y
|
||||
CONFIG_CLK_RK3368=y
|
||||
|
|
@ -7215,6 +7273,7 @@ CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
|
|||
|
||||
CONFIG_MAILBOX=y
|
||||
CONFIG_ARM_MHU=y
|
||||
CONFIG_ARM_MHU_V2=m
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
# CONFIG_PL320_MBOX is not set
|
||||
CONFIG_ROCKCHIP_MBOX=y
|
||||
|
|
@ -7275,14 +7334,8 @@ CONFIG_MESON_GX_SOCINFO=y
|
|||
CONFIG_MESON_GX_PM_DOMAINS=y
|
||||
CONFIG_MESON_EE_PM_DOMAINS=y
|
||||
CONFIG_MESON_SECURE_PM_DOMAINS=y
|
||||
CONFIG_MESON_MX_SOCINFO=y
|
||||
# end of Amlogic SoC drivers
|
||||
|
||||
#
|
||||
# Aspeed SoC drivers
|
||||
#
|
||||
# end of Aspeed SoC drivers
|
||||
|
||||
#
|
||||
# Broadcom SoC drivers
|
||||
#
|
||||
|
|
@ -7301,6 +7354,13 @@ CONFIG_SOC_BRCMSTB=y
|
|||
#
|
||||
# end of i.MX SoC drivers
|
||||
|
||||
#
|
||||
# Enable LiteX SoC Builder specific drivers
|
||||
#
|
||||
CONFIG_LITEX=y
|
||||
CONFIG_LITEX_SOC_CONTROLLER=m
|
||||
# end of Enable LiteX SoC Builder specific drivers
|
||||
|
||||
#
|
||||
# Qualcomm SoC drivers
|
||||
#
|
||||
|
|
@ -7310,6 +7370,7 @@ CONFIG_ROCKCHIP_GRF=y
|
|||
CONFIG_ROCKCHIP_IODOMAIN=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
# CONFIG_ROCKCHIP_SUSPEND_MODE is not set
|
||||
CONFIG_SUNXI_MBUS=y
|
||||
CONFIG_SUNXI_SRAM=y
|
||||
# CONFIG_SOC_TI is not set
|
||||
|
||||
|
|
@ -7354,6 +7415,7 @@ CONFIG_EXTCON_PTN5150=m
|
|||
# CONFIG_EXTCON_SM5502 is not set
|
||||
CONFIG_EXTCON_USB_GPIO=y
|
||||
# CONFIG_EXTCON_USBC_CROS_EC is not set
|
||||
CONFIG_EXTCON_USBC_TUSB320=m
|
||||
# CONFIG_MEMORY is not set
|
||||
CONFIG_IIO=y
|
||||
CONFIG_IIO_BUFFER=y
|
||||
|
|
@ -7885,7 +7947,9 @@ CONFIG_MAX31856=m
|
|||
CONFIG_PWM=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_PWM_DEBUG is not set
|
||||
CONFIG_PWM_ATMEL_TCB=m
|
||||
CONFIG_PWM_CROS_EC=m
|
||||
CONFIG_PWM_DWC=m
|
||||
# CONFIG_PWM_FSL_FTM is not set
|
||||
# CONFIG_PWM_IQS620A is not set
|
||||
CONFIG_PWM_MESON=m
|
||||
|
|
@ -7936,6 +8000,7 @@ CONFIG_PHY_MESON_G12A_USB2=m
|
|||
CONFIG_PHY_MESON_G12A_USB3_PCIE=m
|
||||
CONFIG_PHY_MESON_AXG_PCIE=y
|
||||
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
|
||||
CONFIG_PHY_MESON_AXG_MIPI_DPHY=m
|
||||
# CONFIG_BCM_KONA_USB2_PHY is not set
|
||||
CONFIG_PHY_CADENCE_TORRENT=m
|
||||
CONFIG_PHY_CADENCE_DPHY=m
|
||||
|
|
@ -8259,6 +8324,7 @@ CONFIG_ROMFS_BACKED_BY_BLOCK=y
|
|||
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
|
||||
CONFIG_ROMFS_ON_BLOCK=y
|
||||
CONFIG_PSTORE=y
|
||||
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
|
||||
CONFIG_PSTORE_DEFLATE_COMPRESS=y
|
||||
# CONFIG_PSTORE_LZO_COMPRESS is not set
|
||||
# CONFIG_PSTORE_LZ4_COMPRESS is not set
|
||||
|
|
@ -8342,6 +8408,7 @@ CONFIG_CIFS_DEBUG=y
|
|||
# CONFIG_CIFS_DEBUG2 is not set
|
||||
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
|
||||
CONFIG_CIFS_DFS_UPCALL=y
|
||||
# CONFIG_CIFS_SWN_UPCALL is not set
|
||||
CONFIG_CIFS_FSCACHE=y
|
||||
CONFIG_CODA_FS=m
|
||||
CONFIG_AFS_FS=m
|
||||
|
|
@ -8471,6 +8538,7 @@ CONFIG_LOAD_UEFI_KEYS=y
|
|||
CONFIG_INTEGRITY_AUDIT=y
|
||||
# CONFIG_IMA is not set
|
||||
# CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY is not set
|
||||
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
|
||||
# CONFIG_EVM is not set
|
||||
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
|
||||
# CONFIG_DEFAULT_SECURITY_SMACK is not set
|
||||
|
|
@ -8487,6 +8555,10 @@ CONFIG_LSM="lockdown,yama,integrity,apparmor"
|
|||
# Memory initialization
|
||||
#
|
||||
CONFIG_INIT_STACK_NONE=y
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
|
||||
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
|
||||
CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
|
||||
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
|
||||
# end of Memory initialization
|
||||
|
|
@ -8845,6 +8917,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y
|
|||
# CONFIG_CMA_SIZE_SEL_MAX is not set
|
||||
CONFIG_CMA_ALIGNMENT=8
|
||||
# CONFIG_DMA_API_DEBUG is not set
|
||||
# CONFIG_DMA_MAP_BENCHMARK is not set
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_DQL=y
|
||||
|
|
@ -8885,6 +8958,8 @@ CONFIG_SBITMAP=y
|
|||
# CONFIG_STRING_SELFTEST is not set
|
||||
# end of Library routines
|
||||
|
||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
|
|
@ -8908,7 +8983,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
|
|||
# Compile-time checks and compiler options
|
||||
#
|
||||
# CONFIG_DEBUG_INFO is not set
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_FRAME_WARN=2048
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_READABLE_ASM is not set
|
||||
|
|
@ -9092,9 +9166,9 @@ CONFIG_PROBE_EVENTS=y
|
|||
# CONFIG_RING_BUFFER_BENCHMARK is not set
|
||||
# CONFIG_TRACE_EVAL_MAP_FILE is not set
|
||||
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
|
||||
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
|
||||
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
|
||||
CONFIG_STRICT_DEVMEM=y
|
||||
# CONFIG_IO_STRICT_DEVMEM is not set
|
||||
|
||||
|
|
@ -9153,9 +9227,11 @@ CONFIG_TEST_BLACKHOLE_DEV=m
|
|||
# CONFIG_TEST_FIRMWARE is not set
|
||||
# CONFIG_TEST_SYSCTL is not set
|
||||
# CONFIG_BITFIELD_KUNIT is not set
|
||||
CONFIG_RESOURCE_KUNIT_TEST=m
|
||||
# CONFIG_SYSCTL_KUNIT_TEST is not set
|
||||
# CONFIG_LIST_KUNIT_TEST is not set
|
||||
# CONFIG_LINEAR_RANGES_TEST is not set
|
||||
CONFIG_CMDLINE_KUNIT_TEST=m
|
||||
# CONFIG_BITS_TEST is not set
|
||||
# CONFIG_TEST_UDELAY is not set
|
||||
# CONFIG_TEST_STATIC_KEYS is not set
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 5.10.13 Kernel Configuration
|
||||
# Linux/arm 5.11.0-rc6 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
|
|
@ -269,7 +269,6 @@ CONFIG_MMU=y
|
|||
CONFIG_ARCH_MMAP_RND_BITS_MIN=8
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=16
|
||||
CONFIG_ARCH_MULTIPLATFORM=y
|
||||
# CONFIG_ARCH_EBSA110 is not set
|
||||
# CONFIG_ARCH_EP93XX is not set
|
||||
# CONFIG_ARCH_FOOTBRIDGE is not set
|
||||
# CONFIG_ARCH_IOP32X is not set
|
||||
|
|
@ -475,6 +474,7 @@ CONFIG_ALIGNMENT_TRAP=y
|
|||
# CONFIG_PARAVIRT is not set
|
||||
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
|
||||
# CONFIG_XEN is not set
|
||||
# CONFIG_STACKPROTECTOR_PER_TASK is not set
|
||||
# end of Kernel Features
|
||||
|
||||
#
|
||||
|
|
@ -653,6 +653,7 @@ CONFIG_HAVE_ARCH_SECCOMP=y
|
|||
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
||||
CONFIG_SECCOMP=y
|
||||
CONFIG_SECCOMP_FILTER=y
|
||||
# CONFIG_SECCOMP_CACHE_DEBUG is not set
|
||||
CONFIG_HAVE_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
|
|
@ -679,6 +680,7 @@ CONFIG_STRICT_MODULE_RWX=y
|
|||
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
|
||||
# CONFIG_LOCK_EVENT_COUNTS is not set
|
||||
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
|
||||
#
|
||||
# GCOV-based kernel profiling
|
||||
|
|
@ -688,6 +690,10 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
|
|||
# end of GCOV-based kernel profiling
|
||||
|
||||
CONFIG_HAVE_GCC_PLUGINS=y
|
||||
CONFIG_GCC_PLUGINS=y
|
||||
# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
|
||||
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
|
||||
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
|
||||
# end of General architecture-dependent options
|
||||
|
||||
CONFIG_RT_MUTEXES=y
|
||||
|
|
@ -793,6 +799,7 @@ CONFIG_SELECT_MEMORY_MODEL=y
|
|||
CONFIG_SPARSEMEM_MANUAL=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_STATIC=y
|
||||
CONFIG_ARCH_KEEP_MEMBLOCK=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
CONFIG_MEMORY_BALLOON=y
|
||||
|
|
@ -832,7 +839,8 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
|
|||
CONFIG_IDLE_PAGE_TRACKING=y
|
||||
CONFIG_FRAME_VECTOR=y
|
||||
# CONFIG_PERCPU_STATS is not set
|
||||
# CONFIG_GUP_BENCHMARK is not set
|
||||
# CONFIG_GUP_TEST is not set
|
||||
CONFIG_KMAP_LOCAL=y
|
||||
# end of Memory Management options
|
||||
|
||||
CONFIG_NET=y
|
||||
|
|
@ -1050,6 +1058,7 @@ CONFIG_NF_DUP_NETDEV=m
|
|||
CONFIG_NFT_DUP_NETDEV=m
|
||||
CONFIG_NFT_FWD_NETDEV=m
|
||||
CONFIG_NFT_FIB_NETDEV=m
|
||||
CONFIG_NFT_REJECT_NETDEV=m
|
||||
CONFIG_NF_FLOW_TABLE_INET=m
|
||||
CONFIG_NF_FLOW_TABLE=m
|
||||
CONFIG_NETFILTER_XTABLES=m
|
||||
|
|
@ -1367,6 +1376,7 @@ CONFIG_BRIDGE=y
|
|||
CONFIG_BRIDGE_IGMP_SNOOPING=y
|
||||
CONFIG_BRIDGE_VLAN_FILTERING=y
|
||||
CONFIG_BRIDGE_MRP=y
|
||||
# CONFIG_BRIDGE_CFM is not set
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
CONFIG_NET_DSA=m
|
||||
CONFIG_NET_DSA_TAG_8021Q=m
|
||||
|
|
@ -1374,7 +1384,9 @@ CONFIG_NET_DSA_TAG_AR9331=m
|
|||
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
|
||||
CONFIG_NET_DSA_TAG_BRCM=m
|
||||
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
|
||||
CONFIG_NET_DSA_TAG_HELLCREEK=m
|
||||
CONFIG_NET_DSA_TAG_GSWIP=m
|
||||
CONFIG_NET_DSA_TAG_DSA_COMMON=m
|
||||
CONFIG_NET_DSA_TAG_DSA=m
|
||||
CONFIG_NET_DSA_TAG_EDSA=m
|
||||
CONFIG_NET_DSA_TAG_MTK=m
|
||||
|
|
@ -1512,9 +1524,7 @@ CONFIG_BATMAN_ADV_BLA=y
|
|||
CONFIG_BATMAN_ADV_DAT=y
|
||||
CONFIG_BATMAN_ADV_NC=y
|
||||
CONFIG_BATMAN_ADV_MCAST=y
|
||||
# CONFIG_BATMAN_ADV_DEBUGFS is not set
|
||||
# CONFIG_BATMAN_ADV_DEBUG is not set
|
||||
CONFIG_BATMAN_ADV_SYSFS=y
|
||||
# CONFIG_BATMAN_ADV_TRACING is not set
|
||||
CONFIG_OPENVSWITCH=m
|
||||
CONFIG_OPENVSWITCH_GRE=m
|
||||
|
|
@ -1719,8 +1729,6 @@ CONFIG_MAC80211_LEDS=y
|
|||
# CONFIG_MAC80211_MESSAGE_TRACING is not set
|
||||
# CONFIG_MAC80211_DEBUG_MENU is not set
|
||||
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
|
||||
CONFIG_WIMAX=m
|
||||
CONFIG_WIMAX_DEBUG_LEVEL=8
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_RFKILL_LEDS=y
|
||||
CONFIG_RFKILL_INPUT=y
|
||||
|
|
@ -1768,6 +1776,7 @@ CONFIG_NFC_NXP_NCI=m
|
|||
CONFIG_NFC_NXP_NCI_I2C=m
|
||||
CONFIG_NFC_S3FWRN5=m
|
||||
CONFIG_NFC_S3FWRN5_I2C=m
|
||||
CONFIG_NFC_S3FWRN82_UART=m
|
||||
CONFIG_NFC_ST95HF=m
|
||||
# end of Near Field Communication (NFC) devices
|
||||
|
||||
|
|
@ -1926,12 +1935,9 @@ CONFIG_MTD_BLOCK2MTD=m
|
|||
#
|
||||
# NAND
|
||||
#
|
||||
CONFIG_MTD_NAND_CORE=m
|
||||
CONFIG_MTD_NAND_CORE=y
|
||||
# CONFIG_MTD_ONENAND is not set
|
||||
CONFIG_MTD_NAND_ECC_SW_HAMMING=m
|
||||
# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
|
||||
CONFIG_MTD_RAW_NAND=m
|
||||
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
|
||||
|
||||
#
|
||||
# Raw/parallel NAND flash controllers
|
||||
|
|
@ -1944,6 +1950,7 @@ CONFIG_MTD_NAND_GPIO=m
|
|||
CONFIG_MTD_NAND_PLATFORM=m
|
||||
CONFIG_MTD_NAND_CADENCE=m
|
||||
# CONFIG_MTD_NAND_ARASAN is not set
|
||||
CONFIG_MTD_NAND_INTEL_LGM=m
|
||||
|
||||
#
|
||||
# Misc
|
||||
|
|
@ -1956,6 +1963,9 @@ CONFIG_MTD_SPI_NAND=m
|
|||
# ECC engine support
|
||||
#
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
|
||||
# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
|
||||
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
|
||||
# end of ECC engine support
|
||||
# end of NAND
|
||||
|
||||
|
|
@ -1968,6 +1978,9 @@ CONFIG_MTD_NAND_ECC=y
|
|||
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
|
||||
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
|
||||
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
|
|
@ -1999,6 +2012,13 @@ CONFIG_BLK_DEV=y
|
|||
# CONFIG_BLK_DEV_NULL_BLK is not set
|
||||
CONFIG_CDROM=m
|
||||
CONFIG_ZRAM=m
|
||||
CONFIG_ZRAM_DEF_COMP_LZORLE=y
|
||||
# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZO is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_842 is not set
|
||||
CONFIG_ZRAM_DEF_COMP="lzo-rle"
|
||||
CONFIG_ZRAM_WRITEBACK=y
|
||||
# CONFIG_ZRAM_MEMORY_TRACKING is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
|
|
@ -2198,12 +2218,14 @@ CONFIG_DM_MULTIPATH=m
|
|||
CONFIG_DM_MULTIPATH_QL=m
|
||||
CONFIG_DM_MULTIPATH_ST=m
|
||||
CONFIG_DM_MULTIPATH_HST=m
|
||||
CONFIG_DM_MULTIPATH_IOA=m
|
||||
CONFIG_DM_DELAY=m
|
||||
CONFIG_DM_DUST=m
|
||||
CONFIG_DM_UEVENT=y
|
||||
CONFIG_DM_FLAKEY=m
|
||||
CONFIG_DM_VERITY=m
|
||||
CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
|
||||
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING is not set
|
||||
CONFIG_DM_VERITY_FEC=y
|
||||
CONFIG_DM_SWITCH=m
|
||||
CONFIG_DM_LOG_WRITES=m
|
||||
|
|
@ -2243,6 +2265,7 @@ CONFIG_VETH=m
|
|||
CONFIG_VIRTIO_NET=m
|
||||
# CONFIG_NLMON is not set
|
||||
CONFIG_NET_VRF=m
|
||||
CONFIG_MHI_NET=m
|
||||
CONFIG_ATM_DRIVERS=y
|
||||
# CONFIG_ATM_DUMMY is not set
|
||||
# CONFIG_ATM_TCP is not set
|
||||
|
|
@ -2258,6 +2281,7 @@ CONFIG_B53_SRAB_DRIVER=m
|
|||
CONFIG_B53_SERDES=m
|
||||
CONFIG_NET_DSA_BCM_SF2=m
|
||||
CONFIG_NET_DSA_LOOP=m
|
||||
CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
|
||||
CONFIG_NET_DSA_LANTIQ_GSWIP=m
|
||||
CONFIG_NET_DSA_MT7530=m
|
||||
CONFIG_NET_DSA_MV88E6060=m
|
||||
|
|
@ -2501,8 +2525,8 @@ CONFIG_USB_SIERRA_NET=m
|
|||
CONFIG_USB_VL600=m
|
||||
CONFIG_USB_NET_CH9200=m
|
||||
CONFIG_USB_NET_AQC111=m
|
||||
# CONFIG_USB_RTL8153_ECM is not set
|
||||
CONFIG_WLAN=y
|
||||
# CONFIG_WIRELESS_WDS is not set
|
||||
CONFIG_WLAN_VENDOR_ADMTEK=y
|
||||
CONFIG_ATH_COMMON=m
|
||||
CONFIG_WLAN_VENDOR_ATH=y
|
||||
|
|
@ -2640,6 +2664,7 @@ CONFIG_WLAN_VENDOR_TI=y
|
|||
CONFIG_RTL8723DU=m
|
||||
CONFIG_RTL8723DS=m
|
||||
CONFIG_RTL8822BU=m
|
||||
CONFIG_RTL8188EU=m
|
||||
CONFIG_RTL8821CU=m
|
||||
CONFIG_WLAN_VENDOR_XRADIO=m
|
||||
CONFIG_XRADIO_NON_POWER_OF_TWO_BLOCKSIZES=y
|
||||
|
|
@ -2657,13 +2682,6 @@ CONFIG_WLAN_VENDOR_QUANTENNA=y
|
|||
CONFIG_MAC80211_HWSIM=m
|
||||
CONFIG_USB_NET_RNDIS_WLAN=m
|
||||
# CONFIG_VIRT_WIFI is not set
|
||||
|
||||
#
|
||||
# WiMAX Wireless Broadband devices
|
||||
#
|
||||
# CONFIG_WIMAX_I2400M_USB is not set
|
||||
# end of WiMAX Wireless Broadband devices
|
||||
|
||||
# CONFIG_WAN is not set
|
||||
CONFIG_NETDEVSIM=m
|
||||
CONFIG_NET_FAILOVER=m
|
||||
|
|
@ -2676,7 +2694,6 @@ CONFIG_NET_FAILOVER=m
|
|||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_LEDS=m
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
CONFIG_INPUT_POLLDEV=m
|
||||
# CONFIG_INPUT_SPARSEKMAP is not set
|
||||
CONFIG_INPUT_MATRIXKMAP=m
|
||||
|
||||
|
|
@ -2875,6 +2892,7 @@ CONFIG_INPUT_UINPUT=m
|
|||
# CONFIG_INPUT_PWM_BEEPER is not set
|
||||
# CONFIG_INPUT_PWM_VIBRA is not set
|
||||
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
|
||||
CONFIG_INPUT_DA7280_HAPTICS=m
|
||||
# CONFIG_INPUT_ADXL34X is not set
|
||||
# CONFIG_INPUT_IMS_PCU is not set
|
||||
# CONFIG_INPUT_IQS269A is not set
|
||||
|
|
@ -2979,6 +2997,7 @@ CONFIG_SERIAL_SC16IS7XX_SPI=y
|
|||
CONFIG_SERIAL_CONEXANT_DIGICOLOR=m
|
||||
# CONFIG_SERIAL_ST_ASC is not set
|
||||
CONFIG_SERIAL_SPRD=m
|
||||
# CONFIG_SERIAL_LITEUART is not set
|
||||
# end of Serial drivers
|
||||
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
|
|
@ -3085,6 +3104,7 @@ CONFIG_I2C_SLAVE_EEPROM=m
|
|||
CONFIG_I3C=m
|
||||
# CONFIG_CDNS_I3C_MASTER is not set
|
||||
CONFIG_DW_I3C_MASTER=m
|
||||
CONFIG_MIPI_I3C_HCI=m
|
||||
CONFIG_SPI=y
|
||||
# CONFIG_SPI_DEBUG is not set
|
||||
CONFIG_SPI_MASTER=y
|
||||
|
|
@ -3168,6 +3188,7 @@ CONFIG_PINCTRL_AXP209=m
|
|||
# CONFIG_PINCTRL_SX150X is not set
|
||||
CONFIG_PINCTRL_STMFX=m
|
||||
# CONFIG_PINCTRL_OCELOT is not set
|
||||
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
|
||||
|
||||
#
|
||||
# Renesas pinctrl drivers
|
||||
|
|
@ -3271,8 +3292,13 @@ CONFIG_GPIO_MAX77650=m
|
|||
#
|
||||
# end of USB GPIO expanders
|
||||
|
||||
#
|
||||
# Virtual GPIO drivers
|
||||
#
|
||||
CONFIG_GPIO_AGGREGATOR=m
|
||||
# CONFIG_GPIO_MOCKUP is not set
|
||||
# end of Virtual GPIO drivers
|
||||
|
||||
CONFIG_W1=m
|
||||
CONFIG_W1_CON=y
|
||||
|
||||
|
|
@ -3316,6 +3342,7 @@ CONFIG_POWER_RESET=y
|
|||
# CONFIG_POWER_RESET_GPIO is not set
|
||||
# CONFIG_POWER_RESET_GPIO_RESTART is not set
|
||||
# CONFIG_POWER_RESET_LTC2952 is not set
|
||||
# CONFIG_POWER_RESET_REGULATOR is not set
|
||||
# CONFIG_POWER_RESET_RESTART is not set
|
||||
CONFIG_POWER_RESET_VERSATILE=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
|
|
@ -3397,6 +3424,7 @@ CONFIG_SENSORS_AXI_FAN_CONTROL=m
|
|||
# CONFIG_SENSORS_ASPEED is not set
|
||||
CONFIG_SENSORS_ATXP1=m
|
||||
# CONFIG_SENSORS_CORSAIR_CPRO is not set
|
||||
CONFIG_SENSORS_CORSAIR_PSU=m
|
||||
CONFIG_SENSORS_DRIVETEMP=m
|
||||
CONFIG_SENSORS_DS620=m
|
||||
CONFIG_SENSORS_DS1621=m
|
||||
|
|
@ -3420,6 +3448,7 @@ CONFIG_SENSORS_LTC2947=m
|
|||
CONFIG_SENSORS_LTC2947_I2C=m
|
||||
CONFIG_SENSORS_LTC2947_SPI=m
|
||||
CONFIG_SENSORS_LTC2990=m
|
||||
CONFIG_SENSORS_LTC2992=m
|
||||
CONFIG_SENSORS_LTC4151=m
|
||||
CONFIG_SENSORS_LTC4215=m
|
||||
CONFIG_SENSORS_LTC4222=m
|
||||
|
|
@ -3427,6 +3456,7 @@ CONFIG_SENSORS_LTC4245=m
|
|||
CONFIG_SENSORS_LTC4260=m
|
||||
CONFIG_SENSORS_LTC4261=m
|
||||
CONFIG_SENSORS_MAX1111=m
|
||||
CONFIG_SENSORS_MAX127=m
|
||||
CONFIG_SENSORS_MAX16065=m
|
||||
CONFIG_SENSORS_MAX1619=m
|
||||
CONFIG_SENSORS_MAX1668=m
|
||||
|
|
@ -3472,6 +3502,7 @@ CONFIG_SENSORS_OCC=m
|
|||
CONFIG_SENSORS_PCF8591=m
|
||||
# CONFIG_PMBUS is not set
|
||||
CONFIG_SENSORS_PWM_FAN=m
|
||||
CONFIG_SENSORS_SBTSI=m
|
||||
CONFIG_SENSORS_SHT15=m
|
||||
CONFIG_SENSORS_SHT21=m
|
||||
CONFIG_SENSORS_SHT3x=m
|
||||
|
|
@ -3722,6 +3753,7 @@ CONFIG_REGULATOR_AXP20X=y
|
|||
CONFIG_REGULATOR_BD71828=m
|
||||
CONFIG_REGULATOR_BD718XX=m
|
||||
CONFIG_REGULATOR_CPCAP=m
|
||||
CONFIG_REGULATOR_DA9121=m
|
||||
# CONFIG_REGULATOR_DA9210 is not set
|
||||
# CONFIG_REGULATOR_DA9211 is not set
|
||||
# CONFIG_REGULATOR_FAN53555 is not set
|
||||
|
|
@ -3749,6 +3781,7 @@ CONFIG_REGULATOR_MP886X=m
|
|||
CONFIG_REGULATOR_MPQ7920=m
|
||||
# CONFIG_REGULATOR_MT6311 is not set
|
||||
# CONFIG_REGULATOR_PCA9450 is not set
|
||||
# CONFIG_REGULATOR_PF8X00 is not set
|
||||
# CONFIG_REGULATOR_PFUZE100 is not set
|
||||
# CONFIG_REGULATOR_PV88060 is not set
|
||||
# CONFIG_REGULATOR_PV88080 is not set
|
||||
|
|
@ -4209,6 +4242,7 @@ CONFIG_VIDEO_ST_MIPID02=m
|
|||
#
|
||||
# Camera sensor devices
|
||||
#
|
||||
CONFIG_VIDEO_CCS_PLL=m
|
||||
CONFIG_VIDEO_HI556=m
|
||||
CONFIG_VIDEO_IMX214=m
|
||||
CONFIG_VIDEO_IMX219=m
|
||||
|
|
@ -4217,6 +4251,7 @@ CONFIG_VIDEO_IMX219=m
|
|||
CONFIG_VIDEO_IMX290=m
|
||||
CONFIG_VIDEO_IMX319=m
|
||||
CONFIG_VIDEO_IMX355=m
|
||||
CONFIG_VIDEO_OV02A10=m
|
||||
# CONFIG_VIDEO_OV2640 is not set
|
||||
# CONFIG_VIDEO_OV2659 is not set
|
||||
CONFIG_VIDEO_OV2680=m
|
||||
|
|
@ -4256,7 +4291,7 @@ CONFIG_VIDEO_RJ54N1=m
|
|||
# CONFIG_VIDEO_S5K6A3 is not set
|
||||
# CONFIG_VIDEO_S5K4ECGX is not set
|
||||
# CONFIG_VIDEO_S5K5BAF is not set
|
||||
# CONFIG_VIDEO_SMIAPP is not set
|
||||
CONFIG_VIDEO_CCS=m
|
||||
CONFIG_VIDEO_ET8EK8=m
|
||||
# CONFIG_VIDEO_S5C73M3 is not set
|
||||
CONFIG_VIDEO_HM5065=m
|
||||
|
|
@ -4570,6 +4605,7 @@ CONFIG_DRM_PANEL=y
|
|||
#
|
||||
# Display Panels
|
||||
#
|
||||
CONFIG_DRM_PANEL_ABT_Y030XX067A=m
|
||||
CONFIG_DRM_PANEL_ARM_VERSATILE=m
|
||||
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
|
||||
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
|
||||
|
|
@ -4591,6 +4627,7 @@ CONFIG_DRM_PANEL_LG_LB035Q02=m
|
|||
# CONFIG_DRM_PANEL_LG_LG4573 is not set
|
||||
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
|
||||
# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
|
||||
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
|
||||
|
|
@ -4607,6 +4644,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
|
|||
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
|
||||
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
|
||||
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
|
||||
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
|
||||
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
||||
|
|
@ -4616,6 +4654,7 @@ CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
|||
CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
|
||||
CONFIG_DRM_PANEL_SONY_ACX424AKP=m
|
||||
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
|
||||
CONFIG_DRM_PANEL_TDO_TL070WSH30=m
|
||||
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
|
||||
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
|
||||
CONFIG_DRM_PANEL_TPO_TPG110=m
|
||||
|
|
@ -4634,6 +4673,7 @@ CONFIG_DRM_PANEL_BRIDGE=y
|
|||
# CONFIG_DRM_CHRONTEL_CH7033 is not set
|
||||
CONFIG_DRM_DISPLAY_CONNECTOR=m
|
||||
# CONFIG_DRM_LONTIUM_LT9611 is not set
|
||||
CONFIG_DRM_LONTIUM_LT9611UXC=m
|
||||
CONFIG_DRM_LVDS_CODEC=m
|
||||
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
|
||||
# CONFIG_DRM_NWL_MIPI_DSI is not set
|
||||
|
|
@ -4656,6 +4696,7 @@ CONFIG_DRM_TI_TPD12S015=m
|
|||
CONFIG_DRM_ANALOGIX_ANX6345=m
|
||||
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
|
||||
CONFIG_DRM_ANALOGIX_DP=m
|
||||
CONFIG_DRM_ANALOGIX_ANX7625=m
|
||||
# CONFIG_DRM_I2C_ADV7511 is not set
|
||||
# CONFIG_DRM_CDNS_MHDP8546 is not set
|
||||
CONFIG_DRM_DW_HDMI=y
|
||||
|
|
@ -4852,6 +4893,9 @@ CONFIG_SND_SOC_AC97_BUS=y
|
|||
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
|
||||
CONFIG_SND_SOC_COMPRESS=y
|
||||
CONFIG_SND_SOC_TOPOLOGY=y
|
||||
CONFIG_SND_SOC_ADI=m
|
||||
CONFIG_SND_SOC_ADI_AXI_I2S=m
|
||||
CONFIG_SND_SOC_ADI_AXI_SPDIF=m
|
||||
CONFIG_SND_SOC_AMD_ACP=m
|
||||
CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
|
||||
CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
|
||||
|
|
@ -4877,6 +4921,7 @@ CONFIG_SND_SOC_FSL_SPDIF=m
|
|||
CONFIG_SND_SOC_FSL_ESAI=m
|
||||
CONFIG_SND_SOC_FSL_MICFIL=m
|
||||
# CONFIG_SND_SOC_FSL_EASRC is not set
|
||||
CONFIG_SND_SOC_FSL_XCVR=m
|
||||
CONFIG_SND_SOC_IMX_AUDMUX=m
|
||||
# end of SoC Audio for Freescale CPUs
|
||||
|
||||
|
|
@ -4936,6 +4981,9 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
|
|||
#
|
||||
CONFIG_SND_SOC_AC97_CODEC=m
|
||||
CONFIG_SND_SOC_ADAU_UTILS=m
|
||||
CONFIG_SND_SOC_ADAU1372=m
|
||||
CONFIG_SND_SOC_ADAU1372_I2C=m
|
||||
CONFIG_SND_SOC_ADAU1372_SPI=m
|
||||
CONFIG_SND_SOC_ADAU1701=m
|
||||
CONFIG_SND_SOC_ADAU17X1=m
|
||||
CONFIG_SND_SOC_ADAU1761=m
|
||||
|
|
@ -5032,6 +5080,7 @@ CONFIG_SND_SOC_SIGMADSP=m
|
|||
CONFIG_SND_SOC_SIGMADSP_I2C=m
|
||||
CONFIG_SND_SOC_SIGMADSP_REGMAP=m
|
||||
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
|
||||
CONFIG_SND_SOC_SIMPLE_MUX=m
|
||||
# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set
|
||||
CONFIG_SND_SOC_SPDIF=m
|
||||
CONFIG_SND_SOC_SSM2305=m
|
||||
|
|
@ -5095,11 +5144,14 @@ CONFIG_SND_SOC_MAX9759=m
|
|||
CONFIG_SND_SOC_MT6351=m
|
||||
CONFIG_SND_SOC_MT6358=m
|
||||
CONFIG_SND_SOC_MT6660=m
|
||||
CONFIG_SND_SOC_NAU8315=m
|
||||
CONFIG_SND_SOC_NAU8540=m
|
||||
CONFIG_SND_SOC_NAU8810=m
|
||||
CONFIG_SND_SOC_NAU8822=m
|
||||
CONFIG_SND_SOC_NAU8824=m
|
||||
CONFIG_SND_SOC_TPA6130A2=m
|
||||
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
|
||||
CONFIG_SND_SOC_LPASS_VA_MACRO=m
|
||||
# end of CODEC drivers
|
||||
|
||||
CONFIG_SND_SIMPLE_CARD_UTILS=y
|
||||
|
|
@ -5428,7 +5480,6 @@ CONFIG_USB_SERIAL_SIERRAWIRELESS=m
|
|||
CONFIG_USB_SERIAL_SYMBOL=m
|
||||
CONFIG_USB_SERIAL_TI=m
|
||||
CONFIG_USB_SERIAL_CYBERJACK=m
|
||||
CONFIG_USB_SERIAL_XIRCOM=m
|
||||
CONFIG_USB_SERIAL_WWAN=m
|
||||
CONFIG_USB_SERIAL_OPTION=m
|
||||
CONFIG_USB_SERIAL_OMNINET=m
|
||||
|
|
@ -5705,6 +5756,11 @@ CONFIG_LEDS_LM3697=m
|
|||
# CONFIG_LEDS_SGM3140 is not set
|
||||
CONFIG_LEDS_AXP20X=m
|
||||
|
||||
#
|
||||
# Flash and Torch LED drivers
|
||||
#
|
||||
CONFIG_LEDS_RT8515=m
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
#
|
||||
|
|
@ -5803,7 +5859,6 @@ CONFIG_RTC_DRV_DS1390=m
|
|||
CONFIG_RTC_DRV_MAX6916=m
|
||||
CONFIG_RTC_DRV_R9701=m
|
||||
CONFIG_RTC_DRV_RX4581=m
|
||||
CONFIG_RTC_DRV_RX6110=m
|
||||
CONFIG_RTC_DRV_RS5C348=m
|
||||
CONFIG_RTC_DRV_MAX6902=m
|
||||
CONFIG_RTC_DRV_PCF2123=m
|
||||
|
|
@ -5818,6 +5873,7 @@ CONFIG_RTC_DRV_DS3232_HWMON=y
|
|||
CONFIG_RTC_DRV_PCF2127=m
|
||||
CONFIG_RTC_DRV_RV3029C2=m
|
||||
CONFIG_RTC_DRV_RV3029_HWMON=y
|
||||
CONFIG_RTC_DRV_RX6110=m
|
||||
|
||||
#
|
||||
# Platform RTC drivers
|
||||
|
|
@ -5858,6 +5914,7 @@ CONFIG_RTC_DRV_CPCAP=m
|
|||
# HID Sensor RTC drivers
|
||||
#
|
||||
CONFIG_RTC_DRV_HID_SENSOR_TIME=m
|
||||
CONFIG_RTC_DRV_GOLDFISH=m
|
||||
CONFIG_DMADEVICES=y
|
||||
# CONFIG_DMADEVICES_DEBUG is not set
|
||||
|
||||
|
|
@ -6057,6 +6114,9 @@ CONFIG_FIELDBUS_DEV=m
|
|||
CONFIG_HMS_ANYBUSS_BUS=m
|
||||
CONFIG_ARCX_ANYBUS_CONTROLLER=m
|
||||
CONFIG_HMS_PROFINET=m
|
||||
CONFIG_WIMAX=m
|
||||
CONFIG_WIMAX_DEBUG_LEVEL=8
|
||||
# CONFIG_WIMAX_I2400M_USB is not set
|
||||
CONFIG_WFX=m
|
||||
# CONFIG_GOLDFISH is not set
|
||||
# CONFIG_CHROME_PLATFORMS is not set
|
||||
|
|
@ -6074,7 +6134,6 @@ CONFIG_COMMON_CLK_MAX9485=m
|
|||
# CONFIG_COMMON_CLK_CDCE706 is not set
|
||||
# CONFIG_COMMON_CLK_CDCE925 is not set
|
||||
# CONFIG_COMMON_CLK_CS2000_CP is not set
|
||||
CONFIG_CLK_QORIQ=y
|
||||
CONFIG_COMMON_CLK_PWM=m
|
||||
CONFIG_COMMON_CLK_VC5=m
|
||||
CONFIG_COMMON_CLK_BD718XX=m
|
||||
|
|
@ -6157,11 +6216,6 @@ CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
|
|||
#
|
||||
# end of Amlogic SoC drivers
|
||||
|
||||
#
|
||||
# Aspeed SoC drivers
|
||||
#
|
||||
# end of Aspeed SoC drivers
|
||||
|
||||
#
|
||||
# Broadcom SoC drivers
|
||||
#
|
||||
|
|
@ -6180,11 +6234,19 @@ CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
|
|||
#
|
||||
# end of i.MX SoC drivers
|
||||
|
||||
#
|
||||
# Enable LiteX SoC Builder specific drivers
|
||||
#
|
||||
CONFIG_LITEX=y
|
||||
CONFIG_LITEX_SOC_CONTROLLER=m
|
||||
# end of Enable LiteX SoC Builder specific drivers
|
||||
|
||||
#
|
||||
# Qualcomm SoC drivers
|
||||
#
|
||||
# end of Qualcomm SoC drivers
|
||||
|
||||
CONFIG_SUNXI_MBUS=y
|
||||
CONFIG_SUNXI_SRAM=y
|
||||
# CONFIG_SOC_TI is not set
|
||||
|
||||
|
|
@ -6223,6 +6285,7 @@ CONFIG_EXTCON_PTN5150=m
|
|||
# CONFIG_EXTCON_RT8973A is not set
|
||||
# CONFIG_EXTCON_SM5502 is not set
|
||||
CONFIG_EXTCON_USB_GPIO=m
|
||||
CONFIG_EXTCON_USBC_TUSB320=m
|
||||
# CONFIG_MEMORY is not set
|
||||
CONFIG_IIO=m
|
||||
CONFIG_IIO_BUFFER=y
|
||||
|
|
@ -6714,6 +6777,7 @@ CONFIG_MAX31856=m
|
|||
CONFIG_PWM=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_PWM_DEBUG is not set
|
||||
CONFIG_PWM_ATMEL_TCB=m
|
||||
# CONFIG_PWM_FSL_FTM is not set
|
||||
# CONFIG_PWM_IQS620A is not set
|
||||
# CONFIG_PWM_PCA9685 is not set
|
||||
|
|
@ -7065,6 +7129,7 @@ CONFIG_ROMFS_BACKED_BY_BLOCK=y
|
|||
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
|
||||
CONFIG_ROMFS_ON_BLOCK=y
|
||||
CONFIG_PSTORE=y
|
||||
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
|
||||
CONFIG_PSTORE_DEFLATE_COMPRESS=y
|
||||
# CONFIG_PSTORE_LZO_COMPRESS is not set
|
||||
# CONFIG_PSTORE_LZ4_COMPRESS is not set
|
||||
|
|
@ -7089,24 +7154,6 @@ CONFIG_EROFS_FS_XATTR=y
|
|||
CONFIG_EROFS_FS_POSIX_ACL=y
|
||||
CONFIG_EROFS_FS_SECURITY=y
|
||||
# CONFIG_EROFS_FS_ZIP is not set
|
||||
CONFIG_AUFS_FS=m
|
||||
CONFIG_AUFS_BRANCH_MAX_127=y
|
||||
# CONFIG_AUFS_BRANCH_MAX_511 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_1023 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_32767 is not set
|
||||
CONFIG_AUFS_SBILIST=y
|
||||
# CONFIG_AUFS_HNOTIFY is not set
|
||||
# CONFIG_AUFS_EXPORT is not set
|
||||
# CONFIG_AUFS_XATTR is not set
|
||||
# CONFIG_AUFS_FHSM is not set
|
||||
# CONFIG_AUFS_RDU is not set
|
||||
# CONFIG_AUFS_DIRREN is not set
|
||||
# CONFIG_AUFS_SHWH is not set
|
||||
# CONFIG_AUFS_BR_RAMFS is not set
|
||||
# CONFIG_AUFS_BR_FUSE is not set
|
||||
CONFIG_AUFS_BR_HFSPLUS=y
|
||||
CONFIG_AUFS_BDEV_LOOP=y
|
||||
# CONFIG_AUFS_DEBUG is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=m
|
||||
CONFIG_NFS_V2=m
|
||||
|
|
@ -7166,6 +7213,7 @@ CONFIG_CIFS_DEBUG=y
|
|||
# CONFIG_CIFS_DEBUG2 is not set
|
||||
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
|
||||
CONFIG_CIFS_DFS_UPCALL=y
|
||||
# CONFIG_CIFS_SWN_UPCALL is not set
|
||||
CONFIG_CIFS_FSCACHE=y
|
||||
CONFIG_CODA_FS=m
|
||||
CONFIG_AFS_FS=m
|
||||
|
|
@ -7306,6 +7354,9 @@ CONFIG_LSM="lockdown,yama,integrity,apparmor"
|
|||
# Memory initialization
|
||||
#
|
||||
CONFIG_INIT_STACK_NONE=y
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
|
||||
CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
|
||||
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
|
||||
# end of Memory initialization
|
||||
|
|
@ -7641,6 +7692,7 @@ CONFIG_CMA_SIZE_SEL_MIN=y
|
|||
# CONFIG_CMA_SIZE_SEL_MAX is not set
|
||||
CONFIG_CMA_ALIGNMENT=8
|
||||
# CONFIG_DMA_API_DEBUG is not set
|
||||
# CONFIG_DMA_MAP_BENCHMARK is not set
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_DQL=y
|
||||
|
|
@ -7677,6 +7729,8 @@ CONFIG_SBITMAP=y
|
|||
# CONFIG_STRING_SELFTEST is not set
|
||||
# end of Library routines
|
||||
|
||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
|
|
@ -7700,7 +7754,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
|
|||
# Compile-time checks and compiler options
|
||||
#
|
||||
# CONFIG_DEBUG_INFO is not set
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_FRAME_WARN=1024
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_READABLE_ASM is not set
|
||||
|
|
@ -7752,9 +7805,12 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
|
|||
# CONFIG_DEBUG_VIRTUAL is not set
|
||||
# CONFIG_DEBUG_MEMORY_INIT is not set
|
||||
# CONFIG_DEBUG_PER_CPU_MAPS is not set
|
||||
# CONFIG_DEBUG_KMAP_LOCAL is not set
|
||||
# CONFIG_DEBUG_HIGHMEM is not set
|
||||
CONFIG_HAVE_ARCH_KASAN=y
|
||||
CONFIG_CC_HAS_KASAN_GENERIC=y
|
||||
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
|
||||
# CONFIG_KASAN is not set
|
||||
# end of Memory Debugging
|
||||
|
||||
# CONFIG_DEBUG_SHIRQ is not set
|
||||
|
|
@ -7867,11 +7923,12 @@ CONFIG_FTRACE_MCOUNT_RECORD=y
|
|||
# CONFIG_TRACEPOINT_BENCHMARK is not set
|
||||
# CONFIG_RING_BUFFER_BENCHMARK is not set
|
||||
# CONFIG_TRACE_EVAL_MAP_FILE is not set
|
||||
# CONFIG_FTRACE_RECORD_RECURSION is not set
|
||||
# CONFIG_FTRACE_STARTUP_TEST is not set
|
||||
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
|
||||
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
|
||||
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
|
||||
# CONFIG_STRICT_DEVMEM is not set
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm64 5.10.13 Kernel Configuration
|
||||
# Linux/arm64 5.11.0-rc6 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
|
|
@ -280,6 +280,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y
|
|||
CONFIG_ARCH_SUNXI=y
|
||||
# CONFIG_ARCH_ALPINE is not set
|
||||
# CONFIG_ARCH_BCM2835 is not set
|
||||
# CONFIG_ARCH_BCM4908 is not set
|
||||
# CONFIG_ARCH_BCM_IPROC is not set
|
||||
# CONFIG_ARCH_BERLIN is not set
|
||||
# CONFIG_ARCH_BITMAIN is not set
|
||||
|
|
@ -382,11 +383,9 @@ CONFIG_HZ_250=y
|
|||
# CONFIG_HZ_1000 is not set
|
||||
CONFIG_HZ=250
|
||||
CONFIG_SCHED_HRTICK=y
|
||||
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
|
||||
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
CONFIG_HW_PERF_EVENTS=y
|
||||
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
|
||||
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
|
||||
|
|
@ -415,6 +414,7 @@ CONFIG_SETEND_EMULATION=y
|
|||
#
|
||||
CONFIG_ARM64_HW_AFDBM=y
|
||||
CONFIG_ARM64_PAN=y
|
||||
CONFIG_AS_HAS_LDAPR=y
|
||||
CONFIG_ARM64_LSE_ATOMICS=y
|
||||
CONFIG_ARM64_USE_LSE_ATOMICS=y
|
||||
CONFIG_ARM64_VHE=y
|
||||
|
|
@ -423,7 +423,6 @@ CONFIG_ARM64_VHE=y
|
|||
#
|
||||
# ARMv8.2 architectural features
|
||||
#
|
||||
CONFIG_ARM64_UAO=y
|
||||
# CONFIG_ARM64_PMEM is not set
|
||||
CONFIG_ARM64_RAS_EXTN=y
|
||||
CONFIG_ARM64_CNP=y
|
||||
|
|
@ -448,6 +447,7 @@ CONFIG_ARM64_TLB_RANGE=y
|
|||
#
|
||||
# ARMv8.5 architectural features
|
||||
#
|
||||
CONFIG_AS_HAS_ARMV8_5=y
|
||||
CONFIG_ARM64_BTI=y
|
||||
CONFIG_ARM64_E0PD=y
|
||||
CONFIG_ARCH_RANDOM=y
|
||||
|
|
@ -595,7 +595,6 @@ CONFIG_CRYPTO_AES_ARM64_BS=y
|
|||
# General architecture-dependent options
|
||||
#
|
||||
CONFIG_CRASH_CORE=y
|
||||
CONFIG_SET_FS=y
|
||||
# CONFIG_KPROBES is not set
|
||||
CONFIG_JUMP_LABEL=y
|
||||
# CONFIG_STATIC_KEYS_SELFTEST is not set
|
||||
|
|
@ -633,6 +632,7 @@ CONFIG_HAVE_ARCH_SECCOMP=y
|
|||
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
||||
CONFIG_SECCOMP=y
|
||||
CONFIG_SECCOMP_FILTER=y
|
||||
# CONFIG_SECCOMP_CACHE_DEBUG is not set
|
||||
CONFIG_HAVE_ARCH_STACKLEAK=y
|
||||
CONFIG_HAVE_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
|
|
@ -640,6 +640,7 @@ CONFIG_STACKPROTECTOR_STRONG=y
|
|||
CONFIG_HAVE_CONTEXT_TRACKING=y
|
||||
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
|
||||
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_HAVE_MOVE_PUD=y
|
||||
CONFIG_HAVE_MOVE_PMD=y
|
||||
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_HAVE_ARCH_HUGE_VMAP=y
|
||||
|
|
@ -666,6 +667,8 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
|
|||
# CONFIG_LOCK_EVENT_COUNTS is not set
|
||||
CONFIG_ARCH_HAS_RELR=y
|
||||
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
|
||||
|
||||
#
|
||||
# GCOV-based kernel profiling
|
||||
|
|
@ -675,6 +678,9 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
|
|||
# end of GCOV-based kernel profiling
|
||||
|
||||
CONFIG_HAVE_GCC_PLUGINS=y
|
||||
CONFIG_GCC_PLUGINS=y
|
||||
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
|
||||
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
|
||||
# end of General architecture-dependent options
|
||||
|
||||
CONFIG_RT_MUTEXES=y
|
||||
|
|
@ -880,7 +886,7 @@ CONFIG_IDLE_PAGE_TRACKING=y
|
|||
CONFIG_ARCH_HAS_PTE_DEVMAP=y
|
||||
CONFIG_FRAME_VECTOR=y
|
||||
CONFIG_PERCPU_STATS=y
|
||||
# CONFIG_GUP_BENCHMARK is not set
|
||||
# CONFIG_GUP_TEST is not set
|
||||
# CONFIG_READ_ONLY_THP_FOR_FS is not set
|
||||
CONFIG_ARCH_HAS_PTE_SPECIAL=y
|
||||
# end of Memory Management options
|
||||
|
|
@ -1097,6 +1103,7 @@ CONFIG_NF_DUP_NETDEV=m
|
|||
CONFIG_NFT_DUP_NETDEV=m
|
||||
CONFIG_NFT_FWD_NETDEV=m
|
||||
CONFIG_NFT_FIB_NETDEV=m
|
||||
CONFIG_NFT_REJECT_NETDEV=m
|
||||
CONFIG_NF_FLOW_TABLE_INET=m
|
||||
CONFIG_NF_FLOW_TABLE=m
|
||||
CONFIG_NETFILTER_XTABLES=y
|
||||
|
|
@ -1388,6 +1395,7 @@ CONFIG_BRIDGE=m
|
|||
CONFIG_BRIDGE_IGMP_SNOOPING=y
|
||||
CONFIG_BRIDGE_VLAN_FILTERING=y
|
||||
CONFIG_BRIDGE_MRP=y
|
||||
# CONFIG_BRIDGE_CFM is not set
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
CONFIG_NET_DSA=m
|
||||
CONFIG_NET_DSA_TAG_8021Q=m
|
||||
|
|
@ -1395,7 +1403,9 @@ CONFIG_NET_DSA_TAG_AR9331=m
|
|||
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
|
||||
CONFIG_NET_DSA_TAG_BRCM=m
|
||||
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
|
||||
CONFIG_NET_DSA_TAG_HELLCREEK=m
|
||||
CONFIG_NET_DSA_TAG_GSWIP=m
|
||||
CONFIG_NET_DSA_TAG_DSA_COMMON=m
|
||||
CONFIG_NET_DSA_TAG_DSA=m
|
||||
CONFIG_NET_DSA_TAG_EDSA=m
|
||||
CONFIG_NET_DSA_TAG_MTK=m
|
||||
|
|
@ -1545,9 +1555,7 @@ CONFIG_BATMAN_ADV_BLA=y
|
|||
CONFIG_BATMAN_ADV_DAT=y
|
||||
CONFIG_BATMAN_ADV_NC=y
|
||||
CONFIG_BATMAN_ADV_MCAST=y
|
||||
CONFIG_BATMAN_ADV_DEBUGFS=y
|
||||
CONFIG_BATMAN_ADV_DEBUG=y
|
||||
CONFIG_BATMAN_ADV_SYSFS=y
|
||||
CONFIG_OPENVSWITCH=m
|
||||
CONFIG_OPENVSWITCH_GRE=m
|
||||
CONFIG_OPENVSWITCH_VXLAN=m
|
||||
|
|
@ -1742,7 +1750,6 @@ CONFIG_MAC80211_LEDS=y
|
|||
# CONFIG_MAC80211_MESSAGE_TRACING is not set
|
||||
# CONFIG_MAC80211_DEBUG_MENU is not set
|
||||
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
|
||||
# CONFIG_WIMAX is not set
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_RFKILL_LEDS=y
|
||||
CONFIG_RFKILL_INPUT=y
|
||||
|
|
@ -1792,6 +1799,7 @@ CONFIG_NFC_NXP_NCI=m
|
|||
CONFIG_NFC_NXP_NCI_I2C=m
|
||||
CONFIG_NFC_S3FWRN5=m
|
||||
CONFIG_NFC_S3FWRN5_I2C=m
|
||||
CONFIG_NFC_S3FWRN82_UART=m
|
||||
CONFIG_NFC_ST95HF=m
|
||||
# end of Near Field Communication (NFC) devices
|
||||
|
||||
|
|
@ -1953,12 +1961,9 @@ CONFIG_MTD_CFI_UTIL=y
|
|||
#
|
||||
# NAND
|
||||
#
|
||||
CONFIG_MTD_NAND_CORE=m
|
||||
CONFIG_MTD_NAND_CORE=y
|
||||
# CONFIG_MTD_ONENAND is not set
|
||||
CONFIG_MTD_NAND_ECC_SW_HAMMING=m
|
||||
# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
|
||||
CONFIG_MTD_RAW_NAND=m
|
||||
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
|
||||
|
||||
#
|
||||
# Raw/parallel NAND flash controllers
|
||||
|
|
@ -1972,6 +1977,7 @@ CONFIG_MTD_NAND_GPIO=m
|
|||
CONFIG_MTD_NAND_PLATFORM=m
|
||||
CONFIG_MTD_NAND_CADENCE=m
|
||||
# CONFIG_MTD_NAND_ARASAN is not set
|
||||
CONFIG_MTD_NAND_INTEL_LGM=m
|
||||
|
||||
#
|
||||
# Misc
|
||||
|
|
@ -1987,6 +1993,9 @@ CONFIG_MTD_SPI_NAND=m
|
|||
# ECC engine support
|
||||
#
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
|
||||
# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
|
||||
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
|
||||
# end of ECC engine support
|
||||
# end of NAND
|
||||
|
||||
|
|
@ -1998,6 +2007,9 @@ CONFIG_MTD_NAND_ECC=y
|
|||
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
|
||||
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
|
||||
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
|
||||
# CONFIG_MTD_UBI is not set
|
||||
# CONFIG_MTD_HYPERBUS is not set
|
||||
CONFIG_DTC=y
|
||||
|
|
@ -2020,6 +2032,13 @@ CONFIG_BLK_DEV=y
|
|||
# CONFIG_BLK_DEV_NULL_BLK is not set
|
||||
CONFIG_CDROM=m
|
||||
CONFIG_ZRAM=m
|
||||
CONFIG_ZRAM_DEF_COMP_LZORLE=y
|
||||
# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZO is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
|
||||
# CONFIG_ZRAM_DEF_COMP_842 is not set
|
||||
CONFIG_ZRAM_DEF_COMP="lzo-rle"
|
||||
CONFIG_ZRAM_WRITEBACK=y
|
||||
# CONFIG_ZRAM_MEMORY_TRACKING is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
|
|
@ -2190,6 +2209,7 @@ CONFIG_DM_MULTIPATH=m
|
|||
# CONFIG_DM_MULTIPATH_QL is not set
|
||||
# CONFIG_DM_MULTIPATH_ST is not set
|
||||
# CONFIG_DM_MULTIPATH_HST is not set
|
||||
CONFIG_DM_MULTIPATH_IOA=m
|
||||
CONFIG_DM_DELAY=m
|
||||
CONFIG_DM_DUST=m
|
||||
# CONFIG_DM_UEVENT is not set
|
||||
|
|
@ -2241,6 +2261,7 @@ CONFIG_VETH=m
|
|||
CONFIG_VIRTIO_NET=m
|
||||
CONFIG_NLMON=m
|
||||
# CONFIG_NET_VRF is not set
|
||||
CONFIG_MHI_NET=m
|
||||
|
||||
#
|
||||
# Distributed Switch Architecture drivers
|
||||
|
|
@ -2248,6 +2269,7 @@ CONFIG_NLMON=m
|
|||
# CONFIG_B53 is not set
|
||||
# CONFIG_NET_DSA_BCM_SF2 is not set
|
||||
# CONFIG_NET_DSA_LOOP is not set
|
||||
CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
|
||||
CONFIG_NET_DSA_LANTIQ_GSWIP=m
|
||||
# CONFIG_NET_DSA_MT7530 is not set
|
||||
# CONFIG_NET_DSA_MV88E6060 is not set
|
||||
|
|
@ -2486,6 +2508,7 @@ CONFIG_USB_SIERRA_NET=m
|
|||
CONFIG_USB_VL600=m
|
||||
CONFIG_USB_NET_CH9200=m
|
||||
# CONFIG_USB_NET_AQC111 is not set
|
||||
# CONFIG_USB_RTL8153_ECM is not set
|
||||
CONFIG_WLAN=y
|
||||
CONFIG_WLAN_VENDOR_ADMTEK=y
|
||||
CONFIG_ATH_COMMON=m
|
||||
|
|
@ -2613,6 +2636,7 @@ CONFIG_RTW88=m
|
|||
CONFIG_RTL8723DU=m
|
||||
CONFIG_RTL8723DS=m
|
||||
CONFIG_RTL8822BU=m
|
||||
CONFIG_RTL8188EU=m
|
||||
CONFIG_RTL8821CU=m
|
||||
# CONFIG_WLAN_VENDOR_XRADIO is not set
|
||||
CONFIG_88XXAU=m
|
||||
|
|
@ -2624,10 +2648,6 @@ CONFIG_WLAN_VENDOR_QUANTENNA=y
|
|||
# CONFIG_MAC80211_HWSIM is not set
|
||||
CONFIG_USB_NET_RNDIS_WLAN=m
|
||||
CONFIG_VIRT_WIFI=m
|
||||
|
||||
#
|
||||
# Enable WiMAX (Networking options) to see the WiMAX drivers
|
||||
#
|
||||
# CONFIG_WAN is not set
|
||||
CONFIG_IEEE802154_DRIVERS=m
|
||||
CONFIG_NETDEVSIM=m
|
||||
|
|
@ -2641,7 +2661,6 @@ CONFIG_NET_FAILOVER=m
|
|||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_LEDS=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
CONFIG_INPUT_POLLDEV=m
|
||||
# CONFIG_INPUT_SPARSEKMAP is not set
|
||||
# CONFIG_INPUT_MATRIXKMAP is not set
|
||||
|
||||
|
|
@ -2858,6 +2877,7 @@ CONFIG_INPUT_PCF8574=m
|
|||
# CONFIG_INPUT_PWM_BEEPER is not set
|
||||
CONFIG_INPUT_PWM_VIBRA=m
|
||||
CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
|
||||
CONFIG_INPUT_DA7280_HAPTICS=m
|
||||
# CONFIG_INPUT_ADXL34X is not set
|
||||
# CONFIG_INPUT_IMS_PCU is not set
|
||||
# CONFIG_INPUT_IQS269A is not set
|
||||
|
|
@ -2952,6 +2972,7 @@ CONFIG_SERIAL_SC16IS7XX_CORE=m
|
|||
CONFIG_SERIAL_SC16IS7XX=m
|
||||
CONFIG_SERIAL_SC16IS7XX_I2C=y
|
||||
# CONFIG_SERIAL_SC16IS7XX_SPI is not set
|
||||
CONFIG_SERIAL_BCM63XX=m
|
||||
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
|
||||
# CONFIG_SERIAL_ALTERA_UART is not set
|
||||
# CONFIG_SERIAL_IFX6X60 is not set
|
||||
|
|
@ -2962,6 +2983,8 @@ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
|
|||
CONFIG_SERIAL_FSL_LINFLEXUART=m
|
||||
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
|
||||
CONFIG_SERIAL_SPRD=m
|
||||
CONFIG_SERIAL_LITEUART=m
|
||||
CONFIG_SERIAL_LITEUART_MAX_PORTS=1
|
||||
# end of Serial drivers
|
||||
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
|
|
@ -3080,6 +3103,7 @@ CONFIG_I2C_SLAVE_EEPROM=m
|
|||
CONFIG_I3C=m
|
||||
CONFIG_CDNS_I3C_MASTER=m
|
||||
CONFIG_DW_I3C_MASTER=m
|
||||
CONFIG_MIPI_I3C_HCI=m
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
|
|
@ -3165,6 +3189,7 @@ CONFIG_PINCTRL_SINGLE=y
|
|||
# CONFIG_PINCTRL_SX150X is not set
|
||||
CONFIG_PINCTRL_STMFX=m
|
||||
# CONFIG_PINCTRL_OCELOT is not set
|
||||
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
|
||||
|
||||
#
|
||||
# Renesas pinctrl drivers
|
||||
|
|
@ -3200,7 +3225,6 @@ CONFIG_GPIOLIB=y
|
|||
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_CDEV=y
|
||||
CONFIG_GPIO_CDEV_V1=y
|
||||
CONFIG_GPIO_GENERIC=y
|
||||
|
|
@ -3269,8 +3293,13 @@ CONFIG_GPIO_XRA1403=m
|
|||
#
|
||||
# end of USB GPIO expanders
|
||||
|
||||
#
|
||||
# Virtual GPIO drivers
|
||||
#
|
||||
CONFIG_GPIO_AGGREGATOR=m
|
||||
CONFIG_GPIO_MOCKUP=m
|
||||
# end of Virtual GPIO drivers
|
||||
|
||||
CONFIG_W1=m
|
||||
CONFIG_W1_CON=y
|
||||
|
||||
|
|
@ -3313,6 +3342,7 @@ CONFIG_POWER_RESET=y
|
|||
# CONFIG_POWER_RESET_GPIO is not set
|
||||
# CONFIG_POWER_RESET_GPIO_RESTART is not set
|
||||
# CONFIG_POWER_RESET_LTC2952 is not set
|
||||
# CONFIG_POWER_RESET_REGULATOR is not set
|
||||
# CONFIG_POWER_RESET_RESTART is not set
|
||||
# CONFIG_POWER_RESET_XGENE is not set
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
|
|
@ -3397,6 +3427,7 @@ CONFIG_SENSORS_ARM_SCPI=m
|
|||
CONFIG_SENSORS_ASPEED=m
|
||||
CONFIG_SENSORS_ATXP1=m
|
||||
# CONFIG_SENSORS_CORSAIR_CPRO is not set
|
||||
CONFIG_SENSORS_CORSAIR_PSU=m
|
||||
CONFIG_SENSORS_DRIVETEMP=m
|
||||
CONFIG_SENSORS_DS620=m
|
||||
CONFIG_SENSORS_DS1621=m
|
||||
|
|
@ -3420,6 +3451,7 @@ CONFIG_SENSORS_LTC2947=m
|
|||
CONFIG_SENSORS_LTC2947_I2C=m
|
||||
# CONFIG_SENSORS_LTC2947_SPI is not set
|
||||
CONFIG_SENSORS_LTC2990=m
|
||||
CONFIG_SENSORS_LTC2992=m
|
||||
CONFIG_SENSORS_LTC4151=m
|
||||
CONFIG_SENSORS_LTC4215=m
|
||||
CONFIG_SENSORS_LTC4222=m
|
||||
|
|
@ -3427,6 +3459,7 @@ CONFIG_SENSORS_LTC4245=m
|
|||
CONFIG_SENSORS_LTC4260=m
|
||||
CONFIG_SENSORS_LTC4261=m
|
||||
CONFIG_SENSORS_MAX1111=m
|
||||
CONFIG_SENSORS_MAX127=m
|
||||
CONFIG_SENSORS_MAX16065=m
|
||||
CONFIG_SENSORS_MAX1619=m
|
||||
CONFIG_SENSORS_MAX1668=m
|
||||
|
|
@ -3492,7 +3525,9 @@ CONFIG_SENSORS_MAX31785=m
|
|||
CONFIG_SENSORS_MAX34440=m
|
||||
CONFIG_SENSORS_MAX8688=m
|
||||
# CONFIG_SENSORS_MP2975 is not set
|
||||
CONFIG_SENSORS_PM6764TR=m
|
||||
# CONFIG_SENSORS_PXE1610 is not set
|
||||
CONFIG_SENSORS_Q54SJ108A2=m
|
||||
CONFIG_SENSORS_TPS40422=m
|
||||
CONFIG_SENSORS_TPS53679=m
|
||||
CONFIG_SENSORS_UCD9000=m
|
||||
|
|
@ -3500,6 +3535,7 @@ CONFIG_SENSORS_UCD9200=m
|
|||
CONFIG_SENSORS_XDPE122=m
|
||||
CONFIG_SENSORS_ZL6100=m
|
||||
CONFIG_SENSORS_PWM_FAN=m
|
||||
CONFIG_SENSORS_SBTSI=m
|
||||
CONFIG_SENSORS_SHT15=m
|
||||
CONFIG_SENSORS_SHT21=m
|
||||
CONFIG_SENSORS_SHT3x=m
|
||||
|
|
@ -3741,10 +3777,12 @@ CONFIG_REGULATOR_88PG86X=m
|
|||
# CONFIG_REGULATOR_AD5398 is not set
|
||||
# CONFIG_REGULATOR_ARIZONA_LDO1 is not set
|
||||
# CONFIG_REGULATOR_ARIZONA_MICSUPP is not set
|
||||
CONFIG_REGULATOR_ARM_SCMI=m
|
||||
CONFIG_REGULATOR_AXP20X=y
|
||||
CONFIG_REGULATOR_BD71828=m
|
||||
CONFIG_REGULATOR_BD718XX=m
|
||||
CONFIG_REGULATOR_BD9571MWV=m
|
||||
CONFIG_REGULATOR_DA9121=m
|
||||
# CONFIG_REGULATOR_DA9210 is not set
|
||||
# CONFIG_REGULATOR_DA9211 is not set
|
||||
# CONFIG_REGULATOR_FAN53555 is not set
|
||||
|
|
@ -3772,6 +3810,7 @@ CONFIG_REGULATOR_MP886X=m
|
|||
CONFIG_REGULATOR_MPQ7920=m
|
||||
# CONFIG_REGULATOR_MT6311 is not set
|
||||
# CONFIG_REGULATOR_PCA9450 is not set
|
||||
CONFIG_REGULATOR_PF8X00=m
|
||||
# CONFIG_REGULATOR_PFUZE100 is not set
|
||||
# CONFIG_REGULATOR_PV88060 is not set
|
||||
# CONFIG_REGULATOR_PV88080 is not set
|
||||
|
|
@ -4125,7 +4164,7 @@ CONFIG_VIDEO_CX25840=m
|
|||
# Camera sensor devices
|
||||
#
|
||||
CONFIG_VIDEO_APTINA_PLL=m
|
||||
CONFIG_VIDEO_SMIAPP_PLL=m
|
||||
CONFIG_VIDEO_CCS_PLL=m
|
||||
CONFIG_VIDEO_HI556=m
|
||||
CONFIG_VIDEO_IMX214=m
|
||||
CONFIG_VIDEO_IMX219=m
|
||||
|
|
@ -4134,6 +4173,7 @@ CONFIG_VIDEO_IMX274=m
|
|||
CONFIG_VIDEO_IMX290=m
|
||||
CONFIG_VIDEO_IMX319=m
|
||||
CONFIG_VIDEO_IMX355=m
|
||||
CONFIG_VIDEO_OV02A10=m
|
||||
CONFIG_VIDEO_OV2640=m
|
||||
CONFIG_VIDEO_OV2659=m
|
||||
CONFIG_VIDEO_OV2680=m
|
||||
|
|
@ -4173,7 +4213,7 @@ CONFIG_VIDEO_S5K6AA=m
|
|||
CONFIG_VIDEO_S5K6A3=m
|
||||
CONFIG_VIDEO_S5K4ECGX=m
|
||||
CONFIG_VIDEO_S5K5BAF=m
|
||||
CONFIG_VIDEO_SMIAPP=m
|
||||
CONFIG_VIDEO_CCS=m
|
||||
CONFIG_VIDEO_ET8EK8=m
|
||||
CONFIG_VIDEO_S5C73M3=m
|
||||
CONFIG_VIDEO_HM5065=m
|
||||
|
|
@ -4435,6 +4475,7 @@ CONFIG_DRM_PANEL=y
|
|||
#
|
||||
# Display Panels
|
||||
#
|
||||
CONFIG_DRM_PANEL_ABT_Y030XX067A=m
|
||||
CONFIG_DRM_PANEL_ARM_VERSATILE=m
|
||||
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
|
||||
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
|
||||
|
|
@ -4456,6 +4497,7 @@ CONFIG_DRM_PANEL_LG_LB035Q02=m
|
|||
# CONFIG_DRM_PANEL_LG_LG4573 is not set
|
||||
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
|
||||
# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
|
||||
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
|
||||
|
|
@ -4472,6 +4514,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
|
|||
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
|
||||
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
|
||||
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
|
||||
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
||||
|
|
@ -4481,6 +4524,7 @@ CONFIG_DRM_PANEL_SITRONIX_ST7701=m
|
|||
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
|
||||
CONFIG_DRM_PANEL_SONY_ACX424AKP=m
|
||||
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
|
||||
CONFIG_DRM_PANEL_TDO_TL070WSH30=m
|
||||
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
|
||||
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
|
||||
CONFIG_DRM_PANEL_TPO_TPG110=m
|
||||
|
|
@ -4499,6 +4543,7 @@ CONFIG_DRM_CDNS_DSI=m
|
|||
# CONFIG_DRM_CHRONTEL_CH7033 is not set
|
||||
CONFIG_DRM_DISPLAY_CONNECTOR=m
|
||||
# CONFIG_DRM_LONTIUM_LT9611 is not set
|
||||
CONFIG_DRM_LONTIUM_LT9611UXC=m
|
||||
CONFIG_DRM_LVDS_CODEC=m
|
||||
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
|
||||
# CONFIG_DRM_NWL_MIPI_DSI is not set
|
||||
|
|
@ -4521,6 +4566,7 @@ CONFIG_DRM_TI_TPD12S015=m
|
|||
CONFIG_DRM_ANALOGIX_ANX6345=m
|
||||
CONFIG_DRM_ANALOGIX_ANX78XX=m
|
||||
CONFIG_DRM_ANALOGIX_DP=m
|
||||
CONFIG_DRM_ANALOGIX_ANX7625=m
|
||||
# CONFIG_DRM_I2C_ADV7511 is not set
|
||||
# CONFIG_DRM_CDNS_MHDP8546 is not set
|
||||
CONFIG_DRM_DW_HDMI=y
|
||||
|
|
@ -4698,6 +4744,9 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
|
|||
# CONFIG_SND_USB_VARIAX is not set
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
|
||||
CONFIG_SND_SOC_ADI=m
|
||||
CONFIG_SND_SOC_ADI_AXI_I2S=m
|
||||
CONFIG_SND_SOC_ADI_AXI_SPDIF=m
|
||||
# CONFIG_SND_SOC_AMD_ACP is not set
|
||||
# CONFIG_SND_ATMEL_SOC is not set
|
||||
CONFIG_SND_BCM63XX_I2S_WHISTLER=m
|
||||
|
|
@ -4717,6 +4766,7 @@ CONFIG_SND_SOC_FSL_AUDMIX=m
|
|||
# CONFIG_SND_SOC_FSL_SPDIF is not set
|
||||
# CONFIG_SND_SOC_FSL_ESAI is not set
|
||||
CONFIG_SND_SOC_FSL_MICFIL=m
|
||||
CONFIG_SND_SOC_FSL_XCVR=m
|
||||
# CONFIG_SND_SOC_IMX_AUDMUX is not set
|
||||
# end of SoC Audio for Freescale CPUs
|
||||
|
||||
|
|
@ -4753,6 +4803,10 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
|
|||
# CODEC drivers
|
||||
#
|
||||
# CONFIG_SND_SOC_AC97_CODEC is not set
|
||||
CONFIG_SND_SOC_ADAU_UTILS=m
|
||||
CONFIG_SND_SOC_ADAU1372=m
|
||||
CONFIG_SND_SOC_ADAU1372_I2C=m
|
||||
CONFIG_SND_SOC_ADAU1372_SPI=m
|
||||
# CONFIG_SND_SOC_ADAU1701 is not set
|
||||
# CONFIG_SND_SOC_ADAU1761_I2C is not set
|
||||
# CONFIG_SND_SOC_ADAU1761_SPI is not set
|
||||
|
|
@ -4834,6 +4888,7 @@ CONFIG_SND_SOC_RK3328=m
|
|||
# CONFIG_SND_SOC_RT5631 is not set
|
||||
# CONFIG_SND_SOC_SGTL5000 is not set
|
||||
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
|
||||
CONFIG_SND_SOC_SIMPLE_MUX=m
|
||||
# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set
|
||||
CONFIG_SND_SOC_SPDIF=m
|
||||
CONFIG_SND_SOC_SSM2305=m
|
||||
|
|
@ -4894,11 +4949,14 @@ CONFIG_SND_SOC_MAX9759=m
|
|||
CONFIG_SND_SOC_MT6351=m
|
||||
CONFIG_SND_SOC_MT6358=m
|
||||
CONFIG_SND_SOC_MT6660=m
|
||||
CONFIG_SND_SOC_NAU8315=m
|
||||
# CONFIG_SND_SOC_NAU8540 is not set
|
||||
# CONFIG_SND_SOC_NAU8810 is not set
|
||||
CONFIG_SND_SOC_NAU8822=m
|
||||
# CONFIG_SND_SOC_NAU8824 is not set
|
||||
# CONFIG_SND_SOC_TPA6130A2 is not set
|
||||
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
|
||||
CONFIG_SND_SOC_LPASS_VA_MACRO=m
|
||||
# end of CODEC drivers
|
||||
|
||||
CONFIG_SND_SIMPLE_CARD_UTILS=m
|
||||
|
|
@ -5223,7 +5281,6 @@ CONFIG_USB_SERIAL_SIERRAWIRELESS=m
|
|||
CONFIG_USB_SERIAL_SYMBOL=m
|
||||
CONFIG_USB_SERIAL_TI=m
|
||||
CONFIG_USB_SERIAL_CYBERJACK=m
|
||||
CONFIG_USB_SERIAL_XIRCOM=m
|
||||
CONFIG_USB_SERIAL_WWAN=m
|
||||
CONFIG_USB_SERIAL_OPTION=m
|
||||
CONFIG_USB_SERIAL_OMNINET=m
|
||||
|
|
@ -5491,6 +5548,10 @@ CONFIG_LEDS_USER=y
|
|||
# CONFIG_LEDS_TI_LMU_COMMON is not set
|
||||
# CONFIG_LEDS_AXP20X is not set
|
||||
|
||||
#
|
||||
# Flash and Torch LED drivers
|
||||
#
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
#
|
||||
|
|
@ -5593,7 +5654,6 @@ CONFIG_RTC_DRV_DS1390=m
|
|||
CONFIG_RTC_DRV_MAX6916=m
|
||||
CONFIG_RTC_DRV_R9701=m
|
||||
CONFIG_RTC_DRV_RX4581=m
|
||||
CONFIG_RTC_DRV_RX6110=m
|
||||
CONFIG_RTC_DRV_RS5C348=m
|
||||
CONFIG_RTC_DRV_MAX6902=m
|
||||
CONFIG_RTC_DRV_PCF2123=m
|
||||
|
|
@ -5608,6 +5668,7 @@ CONFIG_RTC_DRV_DS3232_HWMON=y
|
|||
CONFIG_RTC_DRV_PCF2127=m
|
||||
CONFIG_RTC_DRV_RV3029C2=m
|
||||
CONFIG_RTC_DRV_RV3029_HWMON=y
|
||||
CONFIG_RTC_DRV_RX6110=m
|
||||
|
||||
#
|
||||
# Platform RTC drivers
|
||||
|
|
@ -5642,6 +5703,7 @@ CONFIG_RTC_DRV_CADENCE=m
|
|||
# HID Sensor RTC drivers
|
||||
#
|
||||
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
|
||||
CONFIG_RTC_DRV_GOLDFISH=m
|
||||
CONFIG_DMADEVICES=y
|
||||
# CONFIG_DMADEVICES_DEBUG is not set
|
||||
|
||||
|
|
@ -5841,6 +5903,7 @@ CONFIG_MOST_COMPONENTS=m
|
|||
|
||||
CONFIG_XIL_AXIS_FIFO=m
|
||||
# CONFIG_FIELDBUS_DEV is not set
|
||||
# CONFIG_WIMAX is not set
|
||||
CONFIG_WFX=m
|
||||
# CONFIG_SPMI_HISI3670 is not set
|
||||
# CONFIG_MFD_HI6421_SPMI is not set
|
||||
|
|
@ -5863,7 +5926,6 @@ CONFIG_COMMON_CLK_SI544=m
|
|||
# CONFIG_COMMON_CLK_CDCE925 is not set
|
||||
# CONFIG_COMMON_CLK_CS2000_CP is not set
|
||||
# CONFIG_COMMON_CLK_S2MPS11 is not set
|
||||
# CONFIG_CLK_QORIQ is not set
|
||||
# CONFIG_COMMON_CLK_XGENE is not set
|
||||
# CONFIG_COMMON_CLK_PWM is not set
|
||||
# CONFIG_COMMON_CLK_VC5 is not set
|
||||
|
|
@ -5904,6 +5966,7 @@ CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
|
|||
|
||||
CONFIG_MAILBOX=y
|
||||
CONFIG_ARM_MHU=y
|
||||
CONFIG_ARM_MHU_V2=m
|
||||
# CONFIG_PLATFORM_MHU is not set
|
||||
# CONFIG_PL320_MBOX is not set
|
||||
# CONFIG_ALTERA_MBOX is not set
|
||||
|
|
@ -5957,11 +6020,6 @@ CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
|
|||
#
|
||||
# end of Amlogic SoC drivers
|
||||
|
||||
#
|
||||
# Aspeed SoC drivers
|
||||
#
|
||||
# end of Aspeed SoC drivers
|
||||
|
||||
#
|
||||
# Broadcom SoC drivers
|
||||
#
|
||||
|
|
@ -5980,11 +6038,19 @@ CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
|
|||
#
|
||||
# end of i.MX SoC drivers
|
||||
|
||||
#
|
||||
# Enable LiteX SoC Builder specific drivers
|
||||
#
|
||||
CONFIG_LITEX=y
|
||||
CONFIG_LITEX_SOC_CONTROLLER=m
|
||||
# end of Enable LiteX SoC Builder specific drivers
|
||||
|
||||
#
|
||||
# Qualcomm SoC drivers
|
||||
#
|
||||
# end of Qualcomm SoC drivers
|
||||
|
||||
CONFIG_SUNXI_MBUS=y
|
||||
CONFIG_SUNXI_SRAM=y
|
||||
# CONFIG_SOC_TI is not set
|
||||
|
||||
|
|
@ -6023,6 +6089,7 @@ CONFIG_EXTCON_PTN5150=m
|
|||
# CONFIG_EXTCON_RT8973A is not set
|
||||
# CONFIG_EXTCON_SM5502 is not set
|
||||
CONFIG_EXTCON_USB_GPIO=y
|
||||
CONFIG_EXTCON_USBC_TUSB320=m
|
||||
# CONFIG_MEMORY is not set
|
||||
CONFIG_IIO=m
|
||||
CONFIG_IIO_BUFFER=y
|
||||
|
|
@ -6546,6 +6613,7 @@ CONFIG_MAX31856=m
|
|||
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
CONFIG_PWM_ATMEL_TCB=m
|
||||
# CONFIG_PWM_FSL_FTM is not set
|
||||
# CONFIG_PWM_IQS620A is not set
|
||||
CONFIG_PWM_PCA9685=m
|
||||
|
|
@ -6872,6 +6940,7 @@ CONFIG_ROMFS_BACKED_BY_BLOCK=y
|
|||
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
|
||||
CONFIG_ROMFS_ON_BLOCK=y
|
||||
CONFIG_PSTORE=y
|
||||
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
|
||||
CONFIG_PSTORE_DEFLATE_COMPRESS=y
|
||||
# CONFIG_PSTORE_LZO_COMPRESS is not set
|
||||
# CONFIG_PSTORE_LZ4_COMPRESS is not set
|
||||
|
|
@ -6895,24 +6964,6 @@ CONFIG_EROFS_FS_XATTR=y
|
|||
CONFIG_EROFS_FS_POSIX_ACL=y
|
||||
CONFIG_EROFS_FS_SECURITY=y
|
||||
# CONFIG_EROFS_FS_ZIP is not set
|
||||
CONFIG_AUFS_FS=m
|
||||
CONFIG_AUFS_BRANCH_MAX_127=y
|
||||
# CONFIG_AUFS_BRANCH_MAX_511 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_1023 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_32767 is not set
|
||||
CONFIG_AUFS_SBILIST=y
|
||||
# CONFIG_AUFS_HNOTIFY is not set
|
||||
# CONFIG_AUFS_EXPORT is not set
|
||||
# CONFIG_AUFS_XATTR is not set
|
||||
# CONFIG_AUFS_FHSM is not set
|
||||
# CONFIG_AUFS_RDU is not set
|
||||
# CONFIG_AUFS_DIRREN is not set
|
||||
# CONFIG_AUFS_SHWH is not set
|
||||
# CONFIG_AUFS_BR_RAMFS is not set
|
||||
# CONFIG_AUFS_BR_FUSE is not set
|
||||
CONFIG_AUFS_BR_HFSPLUS=y
|
||||
CONFIG_AUFS_BDEV_LOOP=y
|
||||
# CONFIG_AUFS_DEBUG is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=m
|
||||
CONFIG_NFS_V2=m
|
||||
|
|
@ -6972,6 +7023,7 @@ CONFIG_CIFS_DEBUG=y
|
|||
# CONFIG_CIFS_DEBUG2 is not set
|
||||
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
|
||||
CONFIG_CIFS_DFS_UPCALL=y
|
||||
# CONFIG_CIFS_SWN_UPCALL is not set
|
||||
CONFIG_CIFS_FSCACHE=y
|
||||
CONFIG_CODA_FS=m
|
||||
CONFIG_AFS_FS=m
|
||||
|
|
@ -7142,6 +7194,10 @@ CONFIG_LSM="lockdown,yama,integrity,apparmor"
|
|||
# Memory initialization
|
||||
#
|
||||
CONFIG_INIT_STACK_NONE=y
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
|
||||
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
|
||||
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
|
||||
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
|
||||
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
|
||||
# end of Memory initialization
|
||||
|
|
@ -7490,6 +7546,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y
|
|||
# CONFIG_CMA_SIZE_SEL_MAX is not set
|
||||
CONFIG_CMA_ALIGNMENT=8
|
||||
# CONFIG_DMA_API_DEBUG is not set
|
||||
# CONFIG_DMA_MAP_BENCHMARK is not set
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_DQL=y
|
||||
|
|
@ -7527,6 +7584,8 @@ CONFIG_SBITMAP=y
|
|||
# CONFIG_STRING_SELFTEST is not set
|
||||
# end of Library routines
|
||||
|
||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
|
|
@ -7548,7 +7607,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
|
|||
#
|
||||
# Compile-time checks and compiler options
|
||||
#
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_FRAME_WARN=2048
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_HEADERS_INSTALL is not set
|
||||
|
|
@ -7649,7 +7707,6 @@ CONFIG_HAVE_C_RECORDMCOUNT=y
|
|||
CONFIG_TRACING_SUPPORT=y
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
|
||||
# CONFIG_STRICT_DEVMEM is not set
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -29,8 +29,8 @@ case $BRANCH in
|
|||
;;
|
||||
dev)
|
||||
|
||||
KERNELSOURCE="https://github.com/xdarklight/linux"
|
||||
KERNELBRANCH="commit:15faa34a0d22dcd15a6f6984a865895110c2f81b"
|
||||
KERNELBRANCH="branch:linux-5.11.y"
|
||||
KERNELPATCHDIR='meson-current'
|
||||
|
||||
;;
|
||||
esac
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ case $BRANCH in
|
|||
dev)
|
||||
|
||||
KERNELPATCHDIR='rockchip64-'$BRANCH
|
||||
KERNELBRANCH="branch:linux-5.10.y"
|
||||
KERNELBRANCH="branch:linux-5.11.y"
|
||||
LINUXFAMILY=rockchip64
|
||||
LINUXCONFIG='linux-rockchip64-'$BRANCH
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ case $BRANCH in
|
|||
dev)
|
||||
|
||||
KERNELSOURCE="https://github.com/megous/linux"
|
||||
KERNELBRANCH="branch:orange-pi-5.10"
|
||||
KERNELBRANCH="branch:orange-pi-5.11"
|
||||
KERNELPATCHDIR='sunxi-'$BRANCH
|
||||
|
||||
;;
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ case $BRANCH in
|
|||
dev)
|
||||
|
||||
KERNELSOURCE="https://github.com/megous/linux"
|
||||
KERNELBRANCH="branch:orange-pi-5.10"
|
||||
KERNELBRANCH="branch:orange-pi-5.11"
|
||||
KERNELPATCHDIR='sunxi-'$BRANCH
|
||||
|
||||
;;
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ case $BRANCH in
|
|||
|
||||
dev)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.10.y'
|
||||
KERNELBRANCH='branch:linux-5.11.y'
|
||||
LINUXCONFIG='linux-mvebu-dev'
|
||||
KERNELPATCHDIR="mvebu-dev"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
ARCH=arm64
|
||||
BOOTSOURCE='https://github.com/u-boot/u-boot'
|
||||
BOOTBRANCH='branch:v2021.01'
|
||||
BOOTENV_FILE='mvebu64.txt'
|
||||
ATFSOURCE='https://github.com/MarvellEmbeddedProcessors/atf-marvell'
|
||||
|
|
@ -41,7 +40,7 @@ case $BRANCH in
|
|||
;;
|
||||
|
||||
dev)
|
||||
KERNELBRANCH='branch:linux-5.10.y'
|
||||
KERNELBRANCH='branch:linux-5.11.y'
|
||||
;;
|
||||
|
||||
esac
|
||||
|
|
|
|||
|
|
@ -23,8 +23,9 @@ case $BRANCH in
|
|||
;;
|
||||
|
||||
dev)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.10.y'
|
||||
KERNELSOURCE='https://github.com/tobetter/linux'
|
||||
KERNELBRANCH='branch:odroid-5.11.y'
|
||||
KERNELDIR='linux-odroidxu4'
|
||||
|
||||
;;
|
||||
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ case $BRANCH in
|
|||
|
||||
dev)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.10.y'
|
||||
KERNELBRANCH='branch:linux-5.11.y'
|
||||
|
||||
;;
|
||||
|
||||
|
|
|
|||
|
|
@ -544,6 +544,9 @@ compilation_prepare()
|
|||
sed -i '/source "drivers\/net\/wireless\/ti\/Kconfig"/a source "drivers\/net\/wireless\/rtl8723ds\/Kconfig"' \
|
||||
"$kerneldir/drivers/net/wireless/Kconfig"
|
||||
|
||||
# add support for K5.11+
|
||||
process_patch_file "${SRC}/patch/misc/wireless-rtl8723ds.patch" "applying"
|
||||
|
||||
fi
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
mvebu-current
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
From 0ef9299ef1afce1dbf847e75cdd16e2343d89bf9 Mon Sep 17 00:00:00 2001
|
||||
From: Igor Pecovnik <igor.pecovnik@gmail.com>
|
||||
Date: Sat, 30 Jan 2021 19:06:41 +0100
|
||||
Subject: [PATCH] Revert "gpio: mvebu: fix pwm .get_state period calculation"
|
||||
|
||||
This reverts commit 43f2e6077f441d681f0337ab91f7c4c2d4c62761.
|
||||
---
|
||||
drivers/gpio/gpio-mvebu.c | 25 +++++++++++++++----------
|
||||
1 file changed, 15 insertions(+), 10 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
|
||||
index ed7c5fc47f52..2f245594a90a 100644
|
||||
--- a/drivers/gpio/gpio-mvebu.c
|
||||
+++ b/drivers/gpio/gpio-mvebu.c
|
||||
@@ -660,8 +660,9 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
|
||||
|
||||
spin_lock_irqsave(&mvpwm->lock, flags);
|
||||
|
||||
- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
|
||||
- val = (unsigned long long) u * NSEC_PER_SEC;
|
||||
+ val = (unsigned long long)
|
||||
+ readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
|
||||
+ val *= NSEC_PER_SEC;
|
||||
do_div(val, mvpwm->clk_rate);
|
||||
if (val > UINT_MAX)
|
||||
state->duty_cycle = UINT_MAX;
|
||||
@@ -670,17 +671,21 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
|
||||
else
|
||||
state->duty_cycle = 1;
|
||||
|
||||
- val = (unsigned long long) u; /* on duration */
|
||||
- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
|
||||
- val += (unsigned long long) u; /* period = on + off duration */
|
||||
+ val = (unsigned long long)
|
||||
+ readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
|
||||
val *= NSEC_PER_SEC;
|
||||
do_div(val, mvpwm->clk_rate);
|
||||
- if (val > UINT_MAX)
|
||||
- state->period = UINT_MAX;
|
||||
- else if (val)
|
||||
- state->period = val;
|
||||
- else
|
||||
+ if (val < state->duty_cycle) {
|
||||
state->period = 1;
|
||||
+ } else {
|
||||
+ val -= state->duty_cycle;
|
||||
+ if (val > UINT_MAX)
|
||||
+ state->period = UINT_MAX;
|
||||
+ else if (val)
|
||||
+ state->period = val;
|
||||
+ else
|
||||
+ state->period = 1;
|
||||
+ }
|
||||
|
||||
regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
|
||||
if (u)
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Subject: [PATCH 01/30] cpuidle: mvebu: indicate failure to enter deeper sleep
|
||||
states
|
||||
MIME-Version: 1.0
|
||||
Content-Disposition: inline
|
||||
Content-Transfer-Encoding: 8bit
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
|
||||
The cpuidle ->enter method expects the return value to be the sleep
|
||||
state we entered. Returning negative numbers or other codes is not
|
||||
permissible since coupled CPU idle was merged.
|
||||
|
||||
At least some of the mvebu_v7_cpu_suspend() implementations return the
|
||||
value from cpu_suspend(), which returns zero if the CPU vectors back
|
||||
into the kernel via cpu_resume() (the success case), or the non-zero
|
||||
return value of the suspend actor, or one (failure cases).
|
||||
|
||||
We do not want to be returning the failure case value back to CPU idle
|
||||
as that indicates that we successfully entered one of the deeper idle
|
||||
states. Always return zero instead, indicating that we slept for the
|
||||
shortest amount of time.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
---
|
||||
drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-
|
||||
1 file changed, 5 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/cpuidle/cpuidle-mvebu-v7.c
|
||||
+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
|
||||
@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp
|
||||
ret = mvebu_v7_cpu_suspend(deepidle);
|
||||
cpu_pm_exit();
|
||||
|
||||
+ /*
|
||||
+ * If we failed to enter the desired state, indicate that we
|
||||
+ * slept lightly.
|
||||
+ */
|
||||
if (ret)
|
||||
- return ret;
|
||||
+ return 0;
|
||||
|
||||
return index;
|
||||
}
|
||||
398
patch/kernel/mvebu-dev/10-mvebu-clearfog-pcie-updates.patch
Normal file
398
patch/kernel/mvebu-dev/10-mvebu-clearfog-pcie-updates.patch
Normal file
|
|
@ -0,0 +1,398 @@
|
|||
From 527312a74d9d85ba9520c8cb2979004f6d23c4da Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Date: Tue, 29 Nov 2016 10:13:46 +0000
|
||||
Subject: [PATCH] mvebu/clearfog pcie updates
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
---
|
||||
drivers/pci/controller/pci-mvebu.c | 112 ++++++++++++++++++++++++++++-
|
||||
drivers/pci/pci-bridge-emul.c | 83 ++++++++++++---------
|
||||
drivers/pci/pci-bridge-emul.h | 15 ++++
|
||||
drivers/pci/pcie/aspm.c | 6 ++
|
||||
drivers/pci/pcie/portdrv_core.c | 2 +
|
||||
5 files changed, 184 insertions(+), 34 deletions(-)
|
||||
|
||||
--- a/drivers/pci/controller/pci-mvebu.c
|
||||
+++ b/drivers/pci/controller/pci-mvebu.c
|
||||
@@ -52,7 +52,14 @@
|
||||
PCIE_CONF_ADDR_EN)
|
||||
#define PCIE_CONF_DATA_OFF 0x18fc
|
||||
#define PCIE_MASK_OFF 0x1910
|
||||
+#define PCIE_MASK_PM_PME BIT(28)
|
||||
#define PCIE_MASK_ENABLE_INTS 0x0f000000
|
||||
+#define PCIE_MASK_ERR_COR BIT(18)
|
||||
+#define PCIE_MASK_ERR_NONFATAL BIT(17)
|
||||
+#define PCIE_MASK_ERR_FATAL BIT(16)
|
||||
+#define PCIE_MASK_FERR_DET BIT(10)
|
||||
+#define PCIE_MASK_NFERR_DET BIT(9)
|
||||
+#define PCIE_MASK_CORERR_DET BIT(8)
|
||||
#define PCIE_CTRL_OFF 0x1a00
|
||||
#define PCIE_CTRL_X1_MODE 0x0001
|
||||
#define PCIE_STAT_OFF 0x1a04
|
||||
@@ -430,6 +437,54 @@ static void mvebu_pcie_handle_membase_ch
|
||||
&port->memwin);
|
||||
}
|
||||
|
||||
+static void mvebu_pcie_handle_irq_change(struct mvebu_pcie_port *port)
|
||||
+{
|
||||
+ u32 reg, old;
|
||||
+ u16 devctl, rtctl;
|
||||
+
|
||||
+ /*
|
||||
+ * Errors from downstream devices:
|
||||
+ * bridge control register SERR: enables reception of errors
|
||||
+ * Errors from this device, or received errors:
|
||||
+ * command SERR: enables ERR_NONFATAL and ERR_FATAL messages
|
||||
+ * => when enabled, these conditions also flag SERR in status register
|
||||
+ * devctl CERE: enables ERR_CORR messages
|
||||
+ * devctl NFERE: enables ERR_NONFATAL messages
|
||||
+ * devctl FERE: enables ERR_FATAL messages
|
||||
+ * Enabled messages then have three paths:
|
||||
+ * 1. rtctl: enables system error indication
|
||||
+ * 2. root error status register updated
|
||||
+ * 3. root error command register: forwarding via MSI
|
||||
+ */
|
||||
+ old = mvebu_readl(port, PCIE_MASK_OFF);
|
||||
+ reg = old & ~(PCIE_MASK_PM_PME | PCIE_MASK_FERR_DET |
|
||||
+ PCIE_MASK_NFERR_DET | PCIE_MASK_CORERR_DET |
|
||||
+ PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
|
||||
+ PCIE_MASK_ERR_FATAL);
|
||||
+
|
||||
+ devctl = port->bridge.pcie_conf.devctl;
|
||||
+ if (devctl & PCI_EXP_DEVCTL_FERE)
|
||||
+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_ERR_FATAL;
|
||||
+ if (devctl & PCI_EXP_DEVCTL_NFERE)
|
||||
+ reg |= PCIE_MASK_NFERR_DET | PCIE_MASK_ERR_NONFATAL;
|
||||
+ if (devctl & PCI_EXP_DEVCTL_CERE)
|
||||
+ reg |= PCIE_MASK_CORERR_DET | PCIE_MASK_ERR_COR;
|
||||
+ if (port->bridge.conf.command & PCI_COMMAND_SERR)
|
||||
+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_NFERR_DET |
|
||||
+ PCIE_MASK_ERR_FATAL | PCIE_MASK_ERR_NONFATAL;
|
||||
+
|
||||
+ if (!(port->bridge.conf.bridgectrl & PCI_BRIDGE_CTL_SERR))
|
||||
+ reg &= ~(PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
|
||||
+ PCIE_MASK_ERR_FATAL);
|
||||
+
|
||||
+ rtctl = port->bridge.pcie_conf.rootctl;
|
||||
+ if (rtctl & PCI_EXP_RTCTL_PMEIE)
|
||||
+ reg |= PCIE_MASK_PM_PME;
|
||||
+
|
||||
+ if (old != reg)
|
||||
+ mvebu_writel(port, reg, PCIE_MASK_OFF);
|
||||
+}
|
||||
+
|
||||
static pci_bridge_emul_read_status_t
|
||||
mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
|
||||
int reg, u32 *value)
|
||||
@@ -475,6 +530,30 @@ mvebu_pci_bridge_emul_pcie_conf_read(str
|
||||
return PCI_BRIDGE_EMUL_HANDLED;
|
||||
}
|
||||
|
||||
+static pci_bridge_emul_read_status_t
|
||||
+mvebu_pci_bridge_emul_pcie_ext_read(struct pci_bridge_emul *bridge,
|
||||
+ int reg, u32 *value)
|
||||
+{
|
||||
+ struct mvebu_pcie_port *port = bridge->data;
|
||||
+
|
||||
+ switch (reg) {
|
||||
+ case 0x00 ... 0x28:
|
||||
+ *value = mvebu_readl(port, 0x100 + (reg & ~3));
|
||||
+ break;
|
||||
+
|
||||
+ case PCI_ERR_ROOT_COMMAND:
|
||||
+ case PCI_ERR_ROOT_STATUS:
|
||||
+ case PCI_ERR_ROOT_ERR_SRC:
|
||||
+ *value = 0;
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ return PCI_BRIDGE_EMUL_NOT_HANDLED;
|
||||
+ }
|
||||
+
|
||||
+ return PCI_BRIDGE_EMUL_HANDLED;
|
||||
+}
|
||||
+
|
||||
static void
|
||||
mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
|
||||
int reg, u32 old, u32 new, u32 mask)
|
||||
@@ -492,7 +571,8 @@ mvebu_pci_bridge_emul_base_conf_write(st
|
||||
mvebu_pcie_handle_iobase_change(port);
|
||||
if ((old ^ new) & PCI_COMMAND_MEMORY)
|
||||
mvebu_pcie_handle_membase_change(port);
|
||||
-
|
||||
+ if ((old ^ new) & PCI_COMMAND_SERR)
|
||||
+ mvebu_pcie_handle_irq_change(port);
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -515,6 +595,11 @@ mvebu_pci_bridge_emul_base_conf_write(st
|
||||
mvebu_pcie_handle_iobase_change(port);
|
||||
break;
|
||||
|
||||
+ case PCI_INTERRUPT_LINE:
|
||||
+ if (((old ^ new) >> 16) & PCI_BRIDGE_CTL_SERR)
|
||||
+ mvebu_pcie_handle_irq_change(port);
|
||||
+ break;
|
||||
+
|
||||
case PCI_PRIMARY_BUS:
|
||||
mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
|
||||
break;
|
||||
@@ -532,6 +617,10 @@ mvebu_pci_bridge_emul_pcie_conf_write(st
|
||||
|
||||
switch (reg) {
|
||||
case PCI_EXP_DEVCTL:
|
||||
+ if ((new ^ old) & (PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_NFERE |
|
||||
+ PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_URRE))
|
||||
+ mvebu_pcie_handle_irq_change(port);
|
||||
+
|
||||
/*
|
||||
* Armada370 data says these bits must always
|
||||
* be zero when in root complex mode.
|
||||
@@ -557,6 +646,25 @@ mvebu_pci_bridge_emul_pcie_conf_write(st
|
||||
case PCI_EXP_RTSTA:
|
||||
mvebu_writel(port, new, PCIE_RC_RTSTA);
|
||||
break;
|
||||
+
|
||||
+ case PCI_EXP_RTCTL:
|
||||
+ if ((new ^ old) & (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
|
||||
+ PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE))
|
||||
+ mvebu_pcie_handle_irq_change(port);
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mvebu_pci_bridge_emul_pcie_ext_write(struct pci_bridge_emul *bridge,
|
||||
+ int reg, u32 old, u32 new, u32 mask)
|
||||
+{
|
||||
+ struct mvebu_pcie_port *port = bridge->data;
|
||||
+
|
||||
+ switch (reg) {
|
||||
+ case 0x00 ... 0x28:
|
||||
+ mvebu_writel(port, new, 0x100 + (reg & ~3));
|
||||
+ break;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -564,6 +672,8 @@ static struct pci_bridge_emul_ops mvebu_
|
||||
.write_base = mvebu_pci_bridge_emul_base_conf_write,
|
||||
.read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
|
||||
.write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
|
||||
+ .read_ext = mvebu_pci_bridge_emul_pcie_ext_read,
|
||||
+ .write_ext = mvebu_pci_bridge_emul_pcie_ext_write,
|
||||
};
|
||||
|
||||
/*
|
||||
--- a/drivers/pci/pci-bridge-emul.c
|
||||
+++ b/drivers/pci/pci-bridge-emul.c
|
||||
@@ -151,6 +151,7 @@ static const struct pci_bridge_reg_behav
|
||||
.rw = (GENMASK(7, 0) |
|
||||
((PCI_BRIDGE_CTL_PARITY |
|
||||
PCI_BRIDGE_CTL_SERR |
|
||||
+ /* NOTE: PCIe does not allow ISA, VGA, MASTER_ABORT */
|
||||
PCI_BRIDGE_CTL_ISA |
|
||||
PCI_BRIDGE_CTL_VGA |
|
||||
PCI_BRIDGE_CTL_MASTER_ABORT |
|
||||
@@ -264,6 +265,7 @@ int pci_bridge_emul_init(struct pci_brid
|
||||
bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
|
||||
bridge->conf.cache_line_size = 0x10;
|
||||
bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
|
||||
+ bridge->conf.bridgectrl = cpu_to_le16(PCI_BRIDGE_CTL_SERR);
|
||||
bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
|
||||
sizeof(pci_regs_behavior),
|
||||
GFP_KERNEL);
|
||||
@@ -323,25 +325,26 @@ int pci_bridge_emul_conf_read(struct pci
|
||||
__le32 *cfgspace;
|
||||
const struct pci_bridge_reg_behavior *behavior;
|
||||
|
||||
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
|
||||
- *value = 0;
|
||||
- return PCIBIOS_SUCCESSFUL;
|
||||
- }
|
||||
-
|
||||
- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
|
||||
+ if (reg < PCI_CAP_PCIE_START) {
|
||||
+ read_op = bridge->ops->read_base;
|
||||
+ cfgspace = (__le32 *) &bridge->conf;
|
||||
+ behavior = bridge->pci_regs_behavior;
|
||||
+ } else if (!bridge->has_pcie) {
|
||||
*value = 0;
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
- }
|
||||
-
|
||||
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
|
||||
+ } else if (reg < PCI_CAP_PCIE_END) {
|
||||
reg -= PCI_CAP_PCIE_START;
|
||||
read_op = bridge->ops->read_pcie;
|
||||
cfgspace = (__le32 *) &bridge->pcie_conf;
|
||||
behavior = bridge->pcie_cap_regs_behavior;
|
||||
+ } else if (reg < 0x100) {
|
||||
+ *value = 0;
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
} else {
|
||||
- read_op = bridge->ops->read_base;
|
||||
- cfgspace = (__le32 *) &bridge->conf;
|
||||
- behavior = bridge->pci_regs_behavior;
|
||||
+ reg -= 0x100;
|
||||
+ read_op = bridge->ops->read_ext;
|
||||
+ cfgspace = NULL;
|
||||
+ behavior = NULL;
|
||||
}
|
||||
|
||||
if (read_op)
|
||||
@@ -349,15 +352,20 @@ int pci_bridge_emul_conf_read(struct pci
|
||||
else
|
||||
ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
|
||||
|
||||
- if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
|
||||
- *value = le32_to_cpu(cfgspace[reg / 4]);
|
||||
+ if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) {
|
||||
+ if (cfgspace)
|
||||
+ *value = le32_to_cpu(cfgspace[reg / 4]);
|
||||
+ else
|
||||
+ *value = 0;
|
||||
+ }
|
||||
|
||||
/*
|
||||
* Make sure we never return any reserved bit with a value
|
||||
* different from 0.
|
||||
*/
|
||||
- *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
|
||||
- behavior[reg / 4].w1c;
|
||||
+ if (behavior)
|
||||
+ *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
|
||||
+ behavior[reg / 4].w1c;
|
||||
|
||||
if (size == 1)
|
||||
*value = (*value >> (8 * (where & 3))) & 0xff;
|
||||
@@ -385,12 +393,6 @@ int pci_bridge_emul_conf_write(struct pc
|
||||
__le32 *cfgspace;
|
||||
const struct pci_bridge_reg_behavior *behavior;
|
||||
|
||||
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
|
||||
- return PCIBIOS_SUCCESSFUL;
|
||||
-
|
||||
- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
|
||||
- return PCIBIOS_SUCCESSFUL;
|
||||
-
|
||||
shift = (where & 0x3) * 8;
|
||||
|
||||
if (size == 4)
|
||||
@@ -406,27 +408,42 @@ int pci_bridge_emul_conf_write(struct pc
|
||||
if (ret != PCIBIOS_SUCCESSFUL)
|
||||
return ret;
|
||||
|
||||
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
|
||||
+ if (reg < PCI_CAP_PCIE_START) {
|
||||
+ write_op = bridge->ops->write_base;
|
||||
+ cfgspace = (__le32 *) &bridge->conf;
|
||||
+ behavior = bridge->pci_regs_behavior;
|
||||
+ } else if (!bridge->has_pcie) {
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+ } else if (reg < PCI_CAP_PCIE_END) {
|
||||
reg -= PCI_CAP_PCIE_START;
|
||||
write_op = bridge->ops->write_pcie;
|
||||
cfgspace = (__le32 *) &bridge->pcie_conf;
|
||||
behavior = bridge->pcie_cap_regs_behavior;
|
||||
+ } else if (reg < 0x100) {
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
} else {
|
||||
- write_op = bridge->ops->write_base;
|
||||
- cfgspace = (__le32 *) &bridge->conf;
|
||||
- behavior = bridge->pci_regs_behavior;
|
||||
+ reg -= 0x100;
|
||||
+ write_op = bridge->ops->write_ext;
|
||||
+ cfgspace = NULL;
|
||||
+ behavior = NULL;
|
||||
}
|
||||
|
||||
- /* Keep all bits, except the RW bits */
|
||||
- new = old & (~mask | ~behavior[reg / 4].rw);
|
||||
+ if (behavior) {
|
||||
+ /* Keep all bits, except the RW bits */
|
||||
+ new = old & (~mask | ~behavior[reg / 4].rw);
|
||||
|
||||
- /* Update the value of the RW bits */
|
||||
- new |= (value << shift) & (behavior[reg / 4].rw & mask);
|
||||
+ /* Update the value of the RW bits */
|
||||
+ new |= (value << shift) & (behavior[reg / 4].rw & mask);
|
||||
|
||||
- /* Clear the W1C bits */
|
||||
- new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
|
||||
+ /* Clear the W1C bits */
|
||||
+ new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
|
||||
+ } else {
|
||||
+ new = old & ~mask;
|
||||
+ new |= (value << shift) & mask;
|
||||
+ }
|
||||
|
||||
- cfgspace[reg / 4] = cpu_to_le32(new);
|
||||
+ if (cfgspace)
|
||||
+ cfgspace[reg / 4] = cpu_to_le32(new);
|
||||
|
||||
if (write_op)
|
||||
write_op(bridge, reg, old, new, mask);
|
||||
--- a/drivers/pci/pci-bridge-emul.h
|
||||
+++ b/drivers/pci/pci-bridge-emul.h
|
||||
@@ -90,6 +90,14 @@ struct pci_bridge_emul_ops {
|
||||
*/
|
||||
pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
|
||||
int reg, u32 *value);
|
||||
+
|
||||
+ /*
|
||||
+ * Same as ->read_base(), except it is for reading from the
|
||||
+ * PCIe extended capability configuration space.
|
||||
+ */
|
||||
+ pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge,
|
||||
+ int reg, u32 *value);
|
||||
+
|
||||
/*
|
||||
* Called when writing to the regular PCI bridge configuration
|
||||
* space. old is the current value, new is the new value being
|
||||
@@ -105,6 +113,13 @@ struct pci_bridge_emul_ops {
|
||||
*/
|
||||
void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
|
||||
u32 old, u32 new, u32 mask);
|
||||
+
|
||||
+ /*
|
||||
+ * Same as ->write_base(), except it is for writing from the
|
||||
+ * PCIe extended capability configuration space.
|
||||
+ */
|
||||
+ void (*write_ext)(struct pci_bridge_emul *bridge, int reg,
|
||||
+ u32 old, u32 new, u32 mask);
|
||||
};
|
||||
|
||||
struct pci_bridge_reg_behavior;
|
||||
--- a/drivers/pci/pcie/aspm.c
|
||||
+++ b/drivers/pci/pcie/aspm.c
|
||||
@@ -578,6 +578,12 @@ static void pcie_aspm_cap_init(struct pc
|
||||
pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
|
||||
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
|
||||
pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
|
||||
+dev_info(&parent->dev, "up support %x enabled %x\n",
|
||||
+ (parent_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10,
|
||||
+ !!(parent_lnkctl & PCI_EXP_LNKCTL_ASPMC));
|
||||
+dev_info(&parent->dev, "dn support %x enabled %x\n",
|
||||
+ (child_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10,
|
||||
+ !!(child_lnkctl & PCI_EXP_LNKCTL_ASPMC));
|
||||
|
||||
/*
|
||||
* Setup L0s state
|
||||
--- a/drivers/pci/pcie/portdrv_core.c
|
||||
+++ b/drivers/pci/pcie/portdrv_core.c
|
||||
@@ -325,6 +325,7 @@ int pcie_port_device_register(struct pci
|
||||
|
||||
/* Get and check PCI Express port services */
|
||||
capabilities = get_port_device_capability(dev);
|
||||
+dev_info(&dev->dev, "PCIe capabilities: 0x%x\n", capabilities);
|
||||
if (!capabilities)
|
||||
return 0;
|
||||
|
||||
@@ -337,6 +338,7 @@ int pcie_port_device_register(struct pci
|
||||
* if that is to be used.
|
||||
*/
|
||||
status = pcie_init_service_irqs(dev, irqs, capabilities);
|
||||
+dev_info(&dev->dev, "init_service_irqs: %d\n", status);
|
||||
if (status) {
|
||||
capabilities &= PCIE_PORT_SERVICE_HP;
|
||||
if (!capabilities)
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
From 2298f59cecc69b0fc6471c5fd3f7629af2d274b2 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Date: Tue, 29 Nov 2016 10:13:48 +0000
|
||||
Subject: [PATCH] implement slot capabilities (SSPL)
|
||||
|
||||
---
|
||||
drivers/pci/controller/pci-mvebu.c | 23 +++++++++++++++++++++++
|
||||
1 file changed, 23 insertions(+)
|
||||
|
||||
--- a/drivers/pci/controller/pci-mvebu.c
|
||||
+++ b/drivers/pci/controller/pci-mvebu.c
|
||||
@@ -66,6 +66,12 @@
|
||||
#define PCIE_STAT_BUS 0xff00
|
||||
#define PCIE_STAT_DEV 0x1f0000
|
||||
#define PCIE_STAT_LINK_DOWN BIT(0)
|
||||
+#define PCIE_SSPL 0x1a0c
|
||||
+#define PCIE_SSPL_MSGEN BIT(14)
|
||||
+#define PCIE_SSPL_SPLS(x) (((x) & 3) << 8)
|
||||
+#define PCIE_SSPL_SPLS_VAL(x) (((x) >> 8) & 3)
|
||||
+#define PCIE_SSPL_SPLV(x) ((x) & 0xff)
|
||||
+#define PCIE_SSPL_SPLV_VAL(x) ((x) & 0xff)
|
||||
#define PCIE_RC_RTSTA 0x1a14
|
||||
#define PCIE_DEBUG_CTRL 0x1a60
|
||||
#define PCIE_DEBUG_SOFT_RESET BIT(20)
|
||||
@@ -515,6 +521,14 @@ mvebu_pci_bridge_emul_pcie_conf_read(str
|
||||
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
|
||||
break;
|
||||
|
||||
+ case PCI_EXP_SLTCAP:
|
||||
+ {
|
||||
+ u32 tmp = mvebu_readl(port, PCIE_SSPL);
|
||||
+ *value = PCIE_SSPL_SPLS_VAL(tmp) << 15 |
|
||||
+ PCIE_SSPL_SPLV_VAL(tmp) << 7;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
case PCI_EXP_SLTCTL:
|
||||
*value = PCI_EXP_SLTSTA_PDS << 16;
|
||||
break;
|
||||
@@ -643,6 +657,15 @@ mvebu_pci_bridge_emul_pcie_conf_write(st
|
||||
mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
|
||||
break;
|
||||
|
||||
+ case PCI_EXP_SLTCAP:
|
||||
+ {
|
||||
+ u32 sspl = PCIE_SSPL_SPLV((new & PCI_EXP_SLTCAP_SPLV) >> 7) |
|
||||
+ PCIE_SSPL_SPLS((new & PCI_EXP_SLTCAP_SPLS) >> 15) |
|
||||
+ PCIE_SSPL_MSGEN;
|
||||
+ mvebu_writel(port, sspl, PCIE_SSPL);
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
case PCI_EXP_RTSTA:
|
||||
mvebu_writel(port, new, PCIE_RC_RTSTA);
|
||||
break;
|
||||
|
|
@ -0,0 +1,432 @@
|
|||
From 88e942a0b703fe54dad925f27f033869e4f10fba Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Date: Sun, 13 Sep 2015 01:06:31 +0100
|
||||
Subject: [PATCH] net: sfp: display SFP module information [*not for
|
||||
mainline*]
|
||||
|
||||
Display SFP module information verbosely, splitting the generic parts
|
||||
into a separate file.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
---
|
||||
drivers/net/phy/Makefile | 2 +-
|
||||
drivers/net/phy/sff.c | 114 ++++++++++++++++++++
|
||||
drivers/net/phy/sff.h | 16 +++
|
||||
drivers/net/phy/sfp.c | 228 +++++++++++++++++++++++++++++++++++++--
|
||||
4 files changed, 349 insertions(+), 11 deletions(-)
|
||||
create mode 100644 drivers/net/phy/sff.c
|
||||
create mode 100644 drivers/net/phy/sff.h
|
||||
|
||||
--- a/drivers/net/phy/Makefile
|
||||
+++ b/drivers/net/phy/Makefile
|
||||
@@ -26,7 +26,7 @@ obj-$(CONFIG_PHYLIB) += libphy.o
|
||||
|
||||
obj-$(CONFIG_NETWORK_PHY_TIMESTAMPING) += mii_timestamper.o
|
||||
|
||||
-obj-$(CONFIG_SFP) += sfp.o
|
||||
+obj-$(CONFIG_SFP) += sff.o sfp.o
|
||||
sfp-obj-$(CONFIG_SFP) += sfp-bus.o
|
||||
obj-y += $(sfp-obj-y) $(sfp-obj-m)
|
||||
|
||||
--- /dev/null
|
||||
+++ b/drivers/net/phy/sff.c
|
||||
@@ -0,0 +1,114 @@
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/sfp.h>
|
||||
+#include "sff.h"
|
||||
+
|
||||
+const char *sff_link_len(char *buf, size_t size, unsigned int length,
|
||||
+ unsigned int multiplier)
|
||||
+{
|
||||
+ if (length == 0)
|
||||
+ return "unsupported/unspecified";
|
||||
+
|
||||
+ if (length == 255) {
|
||||
+ *buf++ = '>';
|
||||
+ size -= 1;
|
||||
+ length -= 1;
|
||||
+ }
|
||||
+
|
||||
+ length *= multiplier;
|
||||
+
|
||||
+ if (length >= 1000)
|
||||
+ snprintf(buf, size, "%u.%0*ukm",
|
||||
+ length / 1000,
|
||||
+ multiplier > 100 ? 1 :
|
||||
+ multiplier > 10 ? 2 : 3,
|
||||
+ length % 1000);
|
||||
+ else
|
||||
+ snprintf(buf, size, "%um", length);
|
||||
+
|
||||
+ return buf;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(sff_link_len);
|
||||
+
|
||||
+const char *sff_bitfield(char *buf, size_t size,
|
||||
+ const struct sff_bitfield *bits, unsigned int val)
|
||||
+{
|
||||
+ char *p = buf;
|
||||
+ int n;
|
||||
+
|
||||
+ *p = '\0';
|
||||
+ while (bits->mask) {
|
||||
+ if ((val & bits->mask) == bits->val) {
|
||||
+ n = snprintf(p, size, "%s%s",
|
||||
+ buf != p ? ", " : "",
|
||||
+ bits->str);
|
||||
+ if (n == size)
|
||||
+ break;
|
||||
+ p += n;
|
||||
+ size -= n;
|
||||
+ }
|
||||
+ bits++;
|
||||
+ }
|
||||
+
|
||||
+ return buf;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(sff_bitfield);
|
||||
+
|
||||
+const char *sff_connector(unsigned int connector)
|
||||
+{
|
||||
+ switch (connector) {
|
||||
+ case SFF8024_CONNECTOR_UNSPEC:
|
||||
+ return "unknown/unspecified";
|
||||
+ case SFF8024_CONNECTOR_SC:
|
||||
+ return "SC";
|
||||
+ case SFF8024_CONNECTOR_FIBERJACK:
|
||||
+ return "Fiberjack";
|
||||
+ case SFF8024_CONNECTOR_LC:
|
||||
+ return "LC";
|
||||
+ case SFF8024_CONNECTOR_MT_RJ:
|
||||
+ return "MT-RJ";
|
||||
+ case SFF8024_CONNECTOR_MU:
|
||||
+ return "MU";
|
||||
+ case SFF8024_CONNECTOR_SG:
|
||||
+ return "SG";
|
||||
+ case SFF8024_CONNECTOR_OPTICAL_PIGTAIL:
|
||||
+ return "Optical pigtail";
|
||||
+ case SFF8024_CONNECTOR_MPO_1X12:
|
||||
+ return "MPO 1X12";
|
||||
+ case SFF8024_CONNECTOR_MPO_2X16:
|
||||
+ return "MPO 2X16";
|
||||
+ case SFF8024_CONNECTOR_HSSDC_II:
|
||||
+ return "HSSDC II";
|
||||
+ case SFF8024_CONNECTOR_COPPER_PIGTAIL:
|
||||
+ return "Copper pigtail";
|
||||
+ case SFF8024_CONNECTOR_RJ45:
|
||||
+ return "RJ45";
|
||||
+ case SFF8024_CONNECTOR_MXC_2X16:
|
||||
+ return "MXC 2X16";
|
||||
+ default:
|
||||
+ return "unknown";
|
||||
+ }
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(sff_connector);
|
||||
+
|
||||
+const char *sff_encoding(unsigned int encoding)
|
||||
+{
|
||||
+ switch (encoding) {
|
||||
+ case SFF8024_ENCODING_UNSPEC:
|
||||
+ return "unspecified";
|
||||
+ case SFF8024_ENCODING_8472_64B66B:
|
||||
+ return "64b66b";
|
||||
+ case SFF8024_ENCODING_8B10B:
|
||||
+ return "8b10b";
|
||||
+ case SFF8024_ENCODING_4B5B:
|
||||
+ return "4b5b";
|
||||
+ case SFF8024_ENCODING_NRZ:
|
||||
+ return "NRZ";
|
||||
+ case SFF8024_ENCODING_8472_MANCHESTER:
|
||||
+ return "MANCHESTER";
|
||||
+ default:
|
||||
+ return "unknown";
|
||||
+ }
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(sff_encoding);
|
||||
+
|
||||
+MODULE_LICENSE("GPL");
|
||||
--- /dev/null
|
||||
+++ b/drivers/net/phy/sff.h
|
||||
@@ -0,0 +1,16 @@
|
||||
+#ifndef SFF_H
|
||||
+#define SFF_H
|
||||
+
|
||||
+struct sff_bitfield {
|
||||
+ unsigned int mask;
|
||||
+ unsigned int val;
|
||||
+ const char *str;
|
||||
+};
|
||||
+
|
||||
+const char *sff_link_len(char *buf, size_t size, unsigned int length,
|
||||
+ unsigned int multiplier);
|
||||
+const char *sff_bitfield(char *buf, size_t size,
|
||||
+ const struct sff_bitfield *bits, unsigned int val);
|
||||
+const char *sff_connector(unsigned int connector);
|
||||
+const char *sff_encoding(unsigned int encoding);
|
||||
+#endif
|
||||
--- a/drivers/net/phy/sfp.c
|
||||
+++ b/drivers/net/phy/sfp.c
|
||||
@@ -17,6 +17,7 @@
|
||||
#include <linux/slab.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
+#include "sff.h"
|
||||
#include "sfp.h"
|
||||
#include "swphy.h"
|
||||
|
||||
@@ -1363,6 +1364,114 @@ static void sfp_hwmon_exit(struct sfp *s
|
||||
}
|
||||
#endif
|
||||
|
||||
+static const struct sff_bitfield sfp_options[] = {
|
||||
+ {
|
||||
+ .mask = SFP_OPTIONS_HIGH_POWER_LEVEL,
|
||||
+ .val = SFP_OPTIONS_HIGH_POWER_LEVEL,
|
||||
+ .str = "hpl",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_PAGING_A2,
|
||||
+ .val = SFP_OPTIONS_PAGING_A2,
|
||||
+ .str = "paginga2",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_RETIMER,
|
||||
+ .val = SFP_OPTIONS_RETIMER,
|
||||
+ .str = "retimer",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_COOLED_XCVR,
|
||||
+ .val = SFP_OPTIONS_COOLED_XCVR,
|
||||
+ .str = "cooled",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_POWER_DECL,
|
||||
+ .val = SFP_OPTIONS_POWER_DECL,
|
||||
+ .str = "powerdecl",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_RX_LINEAR_OUT,
|
||||
+ .val = SFP_OPTIONS_RX_LINEAR_OUT,
|
||||
+ .str = "rxlinear",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_RX_DECISION_THRESH,
|
||||
+ .val = SFP_OPTIONS_RX_DECISION_THRESH,
|
||||
+ .str = "rxthresh",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_TUNABLE_TX,
|
||||
+ .val = SFP_OPTIONS_TUNABLE_TX,
|
||||
+ .str = "tunabletx",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_RATE_SELECT,
|
||||
+ .val = SFP_OPTIONS_RATE_SELECT,
|
||||
+ .str = "ratesel",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_TX_DISABLE,
|
||||
+ .val = SFP_OPTIONS_TX_DISABLE,
|
||||
+ .str = "txdisable",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_TX_FAULT,
|
||||
+ .val = SFP_OPTIONS_TX_FAULT,
|
||||
+ .str = "txfault",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_LOS_INVERTED,
|
||||
+ .val = SFP_OPTIONS_LOS_INVERTED,
|
||||
+ .str = "los-",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_LOS_NORMAL,
|
||||
+ .val = SFP_OPTIONS_LOS_NORMAL,
|
||||
+ .str = "los+",
|
||||
+ }, { }
|
||||
+};
|
||||
+
|
||||
+static const struct sff_bitfield diagmon[] = {
|
||||
+ {
|
||||
+ .mask = SFP_DIAGMON_DDM,
|
||||
+ .val = SFP_DIAGMON_DDM,
|
||||
+ .str = "ddm",
|
||||
+ }, {
|
||||
+ .mask = SFP_DIAGMON_INT_CAL,
|
||||
+ .val = SFP_DIAGMON_INT_CAL,
|
||||
+ .str = "intcal",
|
||||
+ }, {
|
||||
+ .mask = SFP_DIAGMON_EXT_CAL,
|
||||
+ .val = SFP_DIAGMON_EXT_CAL,
|
||||
+ .str = "extcal",
|
||||
+ }, {
|
||||
+ .mask = SFP_DIAGMON_RXPWR_AVG,
|
||||
+ .val = SFP_DIAGMON_RXPWR_AVG,
|
||||
+ .str = "rxpwravg",
|
||||
+ }, { }
|
||||
+};
|
||||
+
|
||||
+static const struct sff_bitfield sfp_enhopts[] = {
|
||||
+ {
|
||||
+ .mask = SFP_ENHOPTS_ALARMWARN,
|
||||
+ .val = SFP_ENHOPTS_ALARMWARN,
|
||||
+ .str = "alarmwarn",
|
||||
+ }, {
|
||||
+ .mask = SFP_ENHOPTS_SOFT_TX_DISABLE,
|
||||
+ .val = SFP_ENHOPTS_SOFT_TX_DISABLE,
|
||||
+ .str = "soft_tx_dis",
|
||||
+ }, {
|
||||
+ .mask = SFP_ENHOPTS_SOFT_TX_FAULT,
|
||||
+ .val = SFP_ENHOPTS_SOFT_TX_FAULT,
|
||||
+ .str = "soft_tx_fault",
|
||||
+ }, {
|
||||
+ .mask = SFP_ENHOPTS_SOFT_RX_LOS,
|
||||
+ .val = SFP_ENHOPTS_SOFT_RX_LOS,
|
||||
+ .str = "soft_rx_los",
|
||||
+ }, {
|
||||
+ .mask = SFP_ENHOPTS_SOFT_RATE_SELECT,
|
||||
+ .val = SFP_ENHOPTS_SOFT_RATE_SELECT,
|
||||
+ .str = "soft_rs",
|
||||
+ }, {
|
||||
+ .mask = SFP_ENHOPTS_APP_SELECT_SFF8079,
|
||||
+ .val = SFP_ENHOPTS_APP_SELECT_SFF8079,
|
||||
+ .str = "app_sel",
|
||||
+ }, {
|
||||
+ .mask = SFP_ENHOPTS_SOFT_RATE_SFF8431,
|
||||
+ .val = SFP_ENHOPTS_SOFT_RATE_SFF8431,
|
||||
+ .str = "soft_r8431",
|
||||
+ }, { }
|
||||
+};
|
||||
+
|
||||
/* Helpers */
|
||||
static void sfp_module_tx_disable(struct sfp *sfp)
|
||||
{
|
||||
@@ -1664,6 +1773,110 @@ static int sfp_cotsworks_fixup_check(str
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static void sfp_print_module_info(struct sfp *sfp, const struct sfp_eeprom_id *id, bool cotsworks)
|
||||
+{
|
||||
+ unsigned int br_nom, br_min, br_max;
|
||||
+ char date[9];
|
||||
+ char options[80];
|
||||
+
|
||||
+ /* Cotsworks also gets the date code wrong. */
|
||||
+ date[0] = id->ext.datecode[4 - 2 * cotsworks];
|
||||
+ date[1] = id->ext.datecode[5 - 2 * cotsworks];
|
||||
+ date[2] = '-';
|
||||
+ date[3] = id->ext.datecode[2 + 2 * cotsworks];
|
||||
+ date[4] = id->ext.datecode[3 + 2 * cotsworks];
|
||||
+ date[5] = '-';
|
||||
+ date[6] = id->ext.datecode[0];
|
||||
+ date[7] = id->ext.datecode[1];
|
||||
+ date[8] = '\0';
|
||||
+
|
||||
+ if (id->base.br_nominal == 0) {
|
||||
+ br_min = br_nom = br_max = 0;
|
||||
+ } else if (id->base.br_nominal == 255) {
|
||||
+ br_nom = 250 * id->ext.br_max;
|
||||
+ br_max = br_nom + br_nom * id->ext.br_min / 100;
|
||||
+ br_min = br_nom - br_nom * id->ext.br_min / 100;
|
||||
+ } else {
|
||||
+ br_nom = id->base.br_nominal * 100;
|
||||
+ br_min = br_nom - id->base.br_nominal * id->ext.br_min;
|
||||
+ br_max = br_nom + id->base.br_nominal * id->ext.br_max;
|
||||
+ }
|
||||
+
|
||||
+ dev_info(sfp->dev, "module %.*s %.*s rev %.*s sn %.*s dc %s\n",
|
||||
+ (int)sizeof(id->base.vendor_name), id->base.vendor_name,
|
||||
+ (int)sizeof(id->base.vendor_pn), id->base.vendor_pn,
|
||||
+ (int)sizeof(id->base.vendor_rev), id->base.vendor_rev,
|
||||
+ (int)sizeof(id->ext.vendor_sn), id->ext.vendor_sn, date);
|
||||
+ dev_info(sfp->dev, " %s connector, encoding %s, bitrate %u.%03u (%u.%03u-%u.%03u) Gbps\n",
|
||||
+ sff_connector(id->base.connector),
|
||||
+ sff_encoding(id->base.encoding),
|
||||
+ br_nom / 1000, br_nom % 1000,
|
||||
+ br_min / 1000, br_min % 1000, br_max / 1000, br_max % 1000);
|
||||
+ dev_info(sfp->dev, " 1000BaseSX%c 1000BaseLX%c 1000BaseCX%c 1000BaseT%c 100BaseLX%c 100BaseFX%c BaseBX10%c BasePX%c\n",
|
||||
+ id->base.e1000_base_sx ? '+' : '-',
|
||||
+ id->base.e1000_base_lx ? '+' : '-',
|
||||
+ id->base.e1000_base_cx ? '+' : '-',
|
||||
+ id->base.e1000_base_t ? '+' : '-',
|
||||
+ id->base.e100_base_lx ? '+' : '-',
|
||||
+ id->base.e100_base_fx ? '+' : '-',
|
||||
+ id->base.e_base_bx10 ? '+' : '-',
|
||||
+ id->base.e_base_px ? '+' : '-');
|
||||
+ dev_info(sfp->dev, " 10GBaseSR%c 10GBaseLR%c 10GBaseLRM%c 10GBaseER%c\n",
|
||||
+ id->base.e10g_base_sr ? '+' : '-',
|
||||
+ id->base.e10g_base_lr ? '+' : '-',
|
||||
+ id->base.e10g_base_lrm ? '+' : '-',
|
||||
+ id->base.e10g_base_er ? '+' : '-');
|
||||
+
|
||||
+ if (!id->base.sfp_ct_passive && !id->base.sfp_ct_active &&
|
||||
+ !id->base.e1000_base_t) {
|
||||
+ char len_9um[16], len_om[16];
|
||||
+
|
||||
+ dev_info(sfp->dev, " Wavelength %unm, fiber lengths:\n",
|
||||
+ be16_to_cpup(&id->base.optical_wavelength));
|
||||
+
|
||||
+ if (id->base.link_len[0] == 255)
|
||||
+ strcpy(len_9um, ">254km");
|
||||
+ else if (id->base.link_len[1] && id->base.link_len[1] != 255)
|
||||
+ sprintf(len_9um, "%um",
|
||||
+ id->base.link_len[1] * 100);
|
||||
+ else if (id->base.link_len[0])
|
||||
+ sprintf(len_9um, "%ukm", id->base.link_len[0]);
|
||||
+ else if (id->base.link_len[1] == 255)
|
||||
+ strcpy(len_9um, ">25.4km");
|
||||
+ else
|
||||
+ strcpy(len_9um, "unsupported");
|
||||
+
|
||||
+ dev_info(sfp->dev, " 9µm SM : %s\n", len_9um);
|
||||
+ dev_info(sfp->dev, " 62.5µm MM OM1: %s\n",
|
||||
+ sff_link_len(len_om, sizeof(len_om),
|
||||
+ id->base.link_len[3], 10));
|
||||
+ dev_info(sfp->dev, " 50µm MM OM2: %s\n",
|
||||
+ sff_link_len(len_om, sizeof(len_om),
|
||||
+ id->base.link_len[2], 10));
|
||||
+ dev_info(sfp->dev, " 50µm MM OM3: %s\n",
|
||||
+ sff_link_len(len_om, sizeof(len_om),
|
||||
+ id->base.link_len[5], 10));
|
||||
+ dev_info(sfp->dev, " 50µm MM OM4: %s\n",
|
||||
+ sff_link_len(len_om, sizeof(len_om),
|
||||
+ id->base.link_len[4], 10));
|
||||
+ } else {
|
||||
+ char len[16];
|
||||
+ dev_info(sfp->dev, " Copper length: %s\n",
|
||||
+ sff_link_len(len, sizeof(len),
|
||||
+ id->base.link_len[4], 1));
|
||||
+ }
|
||||
+
|
||||
+ dev_info(sfp->dev, " Options: %s\n",
|
||||
+ sff_bitfield(options, sizeof(options), sfp_options,
|
||||
+ be16_to_cpu(id->ext.options)));
|
||||
+ dev_info(sfp->dev, " Diagnostics: %s\n",
|
||||
+ sff_bitfield(options, sizeof(options), diagmon,
|
||||
+ id->ext.diagmon));
|
||||
+ dev_info(sfp->dev, " EnhOpts: %s\n",
|
||||
+ sff_bitfield(options, sizeof(options), sfp_enhopts,
|
||||
+ id->ext.enhopts));
|
||||
+}
|
||||
+
|
||||
static int sfp_sm_mod_probe(struct sfp *sfp, bool report)
|
||||
{
|
||||
/* SFP module inserted - read I2C data */
|
||||
@@ -1685,9 +1898,9 @@ static int sfp_sm_mod_probe(struct sfp *
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
- /* Cotsworks do not seem to update the checksums when they
|
||||
- * do the final programming with the final module part number,
|
||||
- * serial number and date code.
|
||||
+ /* Cotsworks do not seem to update the checksums when they update the
|
||||
+ * module part number, serial number and date code. They also format
|
||||
+ * the date code incorrectly.
|
||||
*/
|
||||
cotsworks = !memcmp(id.base.vendor_name, "COTSWORKS ", 16);
|
||||
cotsworks_sfbg = !memcmp(id.base.vendor_pn, "SFBG", 4);
|
||||
@@ -1735,14 +1948,9 @@ static int sfp_sm_mod_probe(struct sfp *
|
||||
}
|
||||
}
|
||||
|
||||
- sfp->id = id;
|
||||
+ sfp_print_module_info(sfp, &id, cotsworks);
|
||||
|
||||
- dev_info(sfp->dev, "module %.*s %.*s rev %.*s sn %.*s dc %.*s\n",
|
||||
- (int)sizeof(id.base.vendor_name), id.base.vendor_name,
|
||||
- (int)sizeof(id.base.vendor_pn), id.base.vendor_pn,
|
||||
- (int)sizeof(id.base.vendor_rev), id.base.vendor_rev,
|
||||
- (int)sizeof(id.ext.vendor_sn), id.ext.vendor_sn,
|
||||
- (int)sizeof(id.ext.datecode), id.ext.datecode);
|
||||
+ sfp->id = id;
|
||||
|
||||
/* Check whether we support this module */
|
||||
if (!sfp->type->module_supported(&id)) {
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Tue, 29 Nov 2016 10:15:45 +0000
|
||||
Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 +
|
||||
.../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++
|
||||
2 files changed, 63 insertions(+)
|
||||
create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
||||
+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
||||
@@ -7,6 +7,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-388-clearfog.dtsi"
|
||||
+#include "armada-38x-solidrun-microsom-emmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SolidRun Clearfog Base A1";
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
|
||||
@@ -0,0 +1,62 @@
|
||||
+/*
|
||||
+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
|
||||
+ *
|
||||
+ * Copyright (C) 2015 Russell King
|
||||
+ *
|
||||
+ * This board is in development; the contents of this file work with
|
||||
+ * the A1 rev 2.0 of the board, which does not represent final
|
||||
+ * production board. Things will change, don't expect this file to
|
||||
+ * remain compatible info the future.
|
||||
+ *
|
||||
+ * This file is dual-licensed: you can use it either under the terms
|
||||
+ * of the GPL or the X11 license, at your option. Note that this dual
|
||||
+ * licensing only applies to this file, and not this project as a
|
||||
+ * whole.
|
||||
+ *
|
||||
+ * a) This file is free software; you can redistribute it and/or
|
||||
+ * modify it under the terms of the GNU General Public License
|
||||
+ * version 2 as published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This file is distributed in the hope that it will be useful
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ *
|
||||
+ * Or, alternatively
|
||||
+ *
|
||||
+ * b) Permission is hereby granted, free of charge, to any person
|
||||
+ * obtaining a copy of this software and associated documentation
|
||||
+ * files (the "Software"), to deal in the Software without
|
||||
+ * restriction, including without limitation the rights to use
|
||||
+ * copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
+ * sell copies of the Software, and to permit persons to whom the
|
||||
+ * Software is furnished to do so, subject to the following
|
||||
+ * conditions:
|
||||
+ *
|
||||
+ * The above copyright notice and this permission notice shall be
|
||||
+ * included in all copies or substantial portions of the Software.
|
||||
+ *
|
||||
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
+ * OTHER DEALINGS IN THE SOFTWARE.
|
||||
+ */
|
||||
+/ {
|
||||
+ soc {
|
||||
+ internal-regs {
|
||||
+ sdhci@d8000 {
|
||||
+ bus-width = <4>;
|
||||
+ no-1-8-v;
|
||||
+ non-removable;
|
||||
+ pinctrl-0 = <µsom_sdhci_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "okay";
|
||||
+ wp-inverted;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
149
patch/kernel/mvebu-dev/91-01-libata-add-ledtrig-support.patch
Normal file
149
patch/kernel/mvebu-dev/91-01-libata-add-ledtrig-support.patch
Normal file
|
|
@ -0,0 +1,149 @@
|
|||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Subject: libata: add ledtrig support
|
||||
|
||||
This adds a LED trigger for each ATA port indicating disk activity.
|
||||
|
||||
As this is needed only on specific platforms (NAS SoCs and such),
|
||||
these platforms should define ARCH_WANTS_LIBATA_LEDS if there
|
||||
are boards with LED(s) intended to indicate ATA disk activity and
|
||||
need the OS to take care of that.
|
||||
In that way, if not selected, LED trigger support not will be
|
||||
included in libata-core and both, codepaths and structures remain
|
||||
untouched.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/ata/Kconfig | 16 ++++++++++++++++
|
||||
drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++
|
||||
include/linux/libata.h | 9 +++++++++
|
||||
3 files changed, 66 insertions(+)
|
||||
|
||||
--- a/drivers/ata/Kconfig
|
||||
+++ b/drivers/ata/Kconfig
|
||||
@@ -67,6 +67,22 @@ config ATA_FORCE
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
+config ARCH_WANT_LIBATA_LEDS
|
||||
+ bool
|
||||
+
|
||||
+config ATA_LEDS
|
||||
+ bool "support ATA port LED triggers"
|
||||
+ depends on ARCH_WANT_LIBATA_LEDS
|
||||
+ select NEW_LEDS
|
||||
+ select LEDS_CLASS
|
||||
+ select LEDS_TRIGGERS
|
||||
+ default y
|
||||
+ help
|
||||
+ This option adds a LED trigger for each registered ATA port.
|
||||
+ It is used to drive disk activity leds connected via GPIO.
|
||||
+
|
||||
+ If unsure, say N.
|
||||
+
|
||||
config ATA_ACPI
|
||||
bool "ATA ACPI Support"
|
||||
depends on ACPI
|
||||
--- a/drivers/ata/libata-core.c
|
||||
+++ b/drivers/ata/libata-core.c
|
||||
@@ -650,6 +650,19 @@ u64 ata_tf_read_block(const struct ata_t
|
||||
return block;
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+#define LIBATA_BLINK_DELAY 20 /* ms */
|
||||
+static inline void ata_led_act(struct ata_port *ap)
|
||||
+{
|
||||
+ unsigned long led_delay = LIBATA_BLINK_DELAY;
|
||||
+
|
||||
+ if (unlikely(!ap->ledtrig))
|
||||
+ return;
|
||||
+
|
||||
+ led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0);
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
/**
|
||||
* ata_build_rw_tf - Build ATA taskfile for given read/write request
|
||||
* @tf: Target ATA taskfile
|
||||
@@ -4513,6 +4526,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
|
||||
if (tag < 0)
|
||||
return NULL;
|
||||
}
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+ ata_led_act(ap);
|
||||
+#endif
|
||||
|
||||
qc = __ata_qc_from_tag(ap, tag);
|
||||
qc->tag = qc->hw_tag = tag;
|
||||
@@ -5291,6 +5307,9 @@ struct ata_port *ata_port_alloc(struct a
|
||||
ap->stats.unhandled_irq = 1;
|
||||
ap->stats.idle_irq = 1;
|
||||
#endif
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+ ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL);
|
||||
+#endif
|
||||
ata_sff_port_init(ap);
|
||||
|
||||
return ap;
|
||||
@@ -5326,6 +5345,12 @@ static void ata_host_release(struct kref
|
||||
|
||||
kfree(ap->pmp_link);
|
||||
kfree(ap->slave_link);
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+ if (ap->ledtrig) {
|
||||
+ led_trigger_unregister(ap->ledtrig);
|
||||
+ kfree(ap->ledtrig);
|
||||
+ };
|
||||
+#endif
|
||||
kfree(ap);
|
||||
host->ports[i] = NULL;
|
||||
}
|
||||
@@ -5732,7 +5757,23 @@ int ata_host_register(struct ata_host *h
|
||||
host->ports[i]->print_id = atomic_inc_return(&ata_print_id);
|
||||
host->ports[i]->local_port_no = i + 1;
|
||||
}
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+ for (i = 0; i < host->n_ports; i++) {
|
||||
+ if (unlikely(!host->ports[i]->ledtrig))
|
||||
+ continue;
|
||||
|
||||
+ snprintf(host->ports[i]->ledtrig_name,
|
||||
+ sizeof(host->ports[i]->ledtrig_name), "ata%u",
|
||||
+ host->ports[i]->print_id);
|
||||
+
|
||||
+ host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name;
|
||||
+
|
||||
+ if (led_trigger_register(host->ports[i]->ledtrig)) {
|
||||
+ kfree(host->ports[i]->ledtrig);
|
||||
+ host->ports[i]->ledtrig = NULL;
|
||||
+ }
|
||||
+ }
|
||||
+#endif
|
||||
/* Create associated sysfs transport objects */
|
||||
for (i = 0; i < host->n_ports; i++) {
|
||||
rc = ata_tport_add(host->dev,host->ports[i]);
|
||||
--- a/include/linux/libata.h
|
||||
+++ b/include/linux/libata.h
|
||||
@@ -23,6 +23,9 @@
|
||||
#include <linux/cdrom.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/async.h>
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+#include <linux/leds.h>
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* Define if arch has non-standard setup. This is a _PCI_ standard
|
||||
@@ -882,6 +885,12 @@ struct ata_port {
|
||||
#ifdef CONFIG_ATA_ACPI
|
||||
struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */
|
||||
#endif
|
||||
+
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+ struct led_trigger *ledtrig;
|
||||
+ char ledtrig_name[8];
|
||||
+#endif
|
||||
+
|
||||
/* owned by EH */
|
||||
u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned;
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
From 9ee6345ef82f7af5f98e17a40e667f8ad6b2fa1b Mon Sep 17 00:00:00 2001
|
||||
From: aprayoga <adit.prayoga@gmail.com>
|
||||
Date: Sun, 3 Sep 2017 18:10:12 +0800
|
||||
Subject: Enable ATA port LED trigger
|
||||
|
||||
---
|
||||
arch/arm/configs/mvebu_v7_defconfig | 1 +
|
||||
arch/arm/mach-mvebu/Kconfig | 1 +
|
||||
2 files changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm/configs/mvebu_v7_defconfig
|
||||
+++ b/arch/arm/configs/mvebu_v7_defconfig
|
||||
@@ -58,6 +58,7 @@ CONFIG_MTD_UBI=y
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_ATA=y
|
||||
+CONFIG_ATA_LEDS=y
|
||||
CONFIG_SATA_AHCI=y
|
||||
CONFIG_AHCI_MVEBU=y
|
||||
CONFIG_SATA_MV=y
|
||||
--- a/arch/arm/mach-mvebu/Kconfig
|
||||
+++ b/arch/arm/mach-mvebu/Kconfig
|
||||
@@ -56,6 +56,7 @@ config MACH_ARMADA_375
|
||||
config MACH_ARMADA_38X
|
||||
bool "Marvell Armada 380/385 boards"
|
||||
depends on ARCH_MULTI_V7
|
||||
+ select ARCH_WANT_LIBATA_LEDS
|
||||
select ARM_ERRATA_720789
|
||||
select PL310_ERRATA_753970
|
||||
select ARM_GIC
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
--- a/drivers/gpio/gpio-mvebu.c
|
||||
+++ b/drivers/gpio/gpio-mvebu.c
|
||||
@@ -40,6 +40,7 @@
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/gpio/machine.h>
|
||||
#include <linux/init.h>
|
||||
+#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
@@ -111,7 +112,7 @@ struct mvebu_gpio_chip {
|
||||
struct regmap *regs;
|
||||
u32 offset;
|
||||
struct regmap *percpu_regs;
|
||||
- int irqbase;
|
||||
+ int bank_irq[4];
|
||||
struct irq_domain *domain;
|
||||
int soc_variant;
|
||||
|
||||
@@ -601,6 +602,33 @@ static void mvebu_gpio_irq_handler(struc
|
||||
}
|
||||
|
||||
/*
|
||||
+ * Set interrupt number "irq" in the GPIO as a wake-up source.
|
||||
+ * While system is running, all registered GPIO interrupts need to have
|
||||
+ * wake-up enabled. When system is suspended, only selected GPIO interrupts
|
||||
+ * need to have wake-up enabled.
|
||||
+ * @param irq interrupt source number
|
||||
+ * @param enable enable as wake-up if equal to non-zero
|
||||
+ * @return This function returns 0 on success.
|
||||
+ */
|
||||
+static int mvebu_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
|
||||
+{
|
||||
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
+ struct mvebu_gpio_chip *mvchip = gc->private;
|
||||
+ int irq;
|
||||
+ int bank;
|
||||
+
|
||||
+ bank = d->hwirq % 8;
|
||||
+ irq = mvchip->bank_irq[bank];
|
||||
+
|
||||
+ if (enable)
|
||||
+ enable_irq_wake(irq);
|
||||
+ else
|
||||
+ disable_irq_wake(irq);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
* Functions implementing the pwm_chip methods
|
||||
*/
|
||||
static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
|
||||
@@ -1219,7 +1247,7 @@ static int mvebu_gpio_probe(struct platf
|
||||
|
||||
err = irq_alloc_domain_generic_chips(
|
||||
mvchip->domain, ngpios, 2, np->name, handle_level_irq,
|
||||
- IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
|
||||
+ IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, IRQ_GC_INIT_NESTED_LOCK);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
|
||||
mvchip->chip.label);
|
||||
@@ -1237,6 +1265,8 @@ static int mvebu_gpio_probe(struct platf
|
||||
ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
|
||||
ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
|
||||
ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
|
||||
+ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
|
||||
+ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
|
||||
ct->chip.name = mvchip->chip.label;
|
||||
|
||||
ct = &gc->chip_types[1];
|
||||
@@ -1245,6 +1275,8 @@ static int mvebu_gpio_probe(struct platf
|
||||
ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
|
||||
ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
|
||||
ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
|
||||
+ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
|
||||
+ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
|
||||
ct->handler = handle_edge_irq;
|
||||
ct->chip.name = mvchip->chip.label;
|
||||
|
||||
@@ -1260,6 +1292,7 @@ static int mvebu_gpio_probe(struct platf
|
||||
continue;
|
||||
irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
|
||||
mvchip);
|
||||
+ mvchip->bank_irq[i] = irq;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
--- a/arch/arm/boot/dts/armada-388-helios4.dts
|
||||
+++ b/arch/arm/boot/dts/armada-388-helios4.dts
|
||||
@@ -84,6 +84,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ gpio-keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ pinctrl-0 = <µsom_phy0_int_pins>;
|
||||
+
|
||||
+ wol {
|
||||
+ label = "Wake-On-LAN";
|
||||
+ linux,code = <KEY_WAKEUP>;
|
||||
+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
|
||||
+ wakeup-source;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
io-leds {
|
||||
compatible = "gpio-leds";
|
||||
sata1-led {
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
--- a/arch/arm/boot/dts/armada-388-helios4.dts
|
||||
+++ b/arch/arm/boot/dts/armada-388-helios4.dts
|
||||
@@ -70,6 +70,9 @@
|
||||
|
||||
system-leds {
|
||||
compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&helios_system_led_pins>;
|
||||
+
|
||||
status-led {
|
||||
label = "helios4:green:status";
|
||||
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
|
||||
@@ -98,6 +101,9 @@
|
||||
|
||||
io-leds {
|
||||
compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&helios_io_led_pins>;
|
||||
+
|
||||
sata1-led {
|
||||
label = "helios4:green:ata1";
|
||||
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
|
||||
@@ -133,11 +139,15 @@
|
||||
fan1: j10-pwm {
|
||||
compatible = "pwm-fan";
|
||||
pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&j10_pins>;
|
||||
};
|
||||
|
||||
fan2: j17-pwm {
|
||||
compatible = "pwm-fan";
|
||||
pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&j17_pins>;
|
||||
};
|
||||
|
||||
usb2_phy: usb2-phy {
|
||||
@@ -298,16 +308,23 @@
|
||||
"mpp39", "mpp40";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
- helios_led_pins: helios-led-pins {
|
||||
- marvell,pins = "mpp24", "mpp25",
|
||||
+ helios_system_led_pins: helios-system-led-pins {
|
||||
+ marvell,pins = "mpp24", "mpp25";
|
||||
+ marvell,function = "gpio";
|
||||
+ };
|
||||
+ helios_io_led_pins: helios-io-led-pins {
|
||||
+ marvell,pins = "mpp49", "mpp50",
|
||||
"mpp49", "mpp50",
|
||||
"mpp52", "mpp53",
|
||||
"mpp54";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
- helios_fan_pins: helios-fan-pins {
|
||||
- marvell,pins = "mpp41", "mpp43",
|
||||
- "mpp48", "mpp55";
|
||||
+ j10_pins: fan-j10-pins {
|
||||
+ marvell,pins = "mpp41", "mpp43";
|
||||
+ marvell,function = "gpio";
|
||||
+ };
|
||||
+ j17_pins: fan-j17-pins {
|
||||
+ marvell,pins = "mpp48", "mpp55";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
microsom_spi1_cs_pins: spi1-cs-pins {
|
||||
12
patch/kernel/mvebu-dev/compile-dtb-with-symbol-support.patch
Normal file
12
patch/kernel/mvebu-dev/compile-dtb-with-symbol-support.patch
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
--- a/scripts/Makefile.lib
|
||||
+++ b/scripts/Makefile.lib
|
||||
@@ -277,6 +277,9 @@ quiet_cmd_gzip = GZIP $@
|
||||
DTC ?= $(objtree)/scripts/dtc/dtc
|
||||
DTC_FLAGS += -Wno-interrupt_provider
|
||||
|
||||
+# Enable overlay support
|
||||
+DTC_FLAGS += -@
|
||||
+
|
||||
# Disable noisy checks by default
|
||||
ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),)
|
||||
DTC_FLAGS += -Wno-unit_address_vs_reg \
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
|
||||
@@ -107,6 +107,7 @@
|
||||
compatible = "w25q32", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <3000000>;
|
||||
+ status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
--- a/arch/arm/mm/dma-mapping.c
|
||||
+++ b/arch/arm/mm/dma-mapping.c
|
||||
@@ -315,7 +315,7 @@ static void *__alloc_remap_buffer(struct
|
||||
pgprot_t prot, struct page **ret_page,
|
||||
const void *caller, bool want_vaddr);
|
||||
|
||||
-#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
|
||||
+#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_2M
|
||||
static struct gen_pool *atomic_pool __ro_after_init;
|
||||
|
||||
static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
--- a/drivers/gpio/gpio-mvebu.c
|
||||
+++ b/drivers/gpio/gpio-mvebu.c
|
||||
@@ -641,39 +641,81 @@ static int mvebu_pwm_request(struct pwm_
|
||||
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
|
||||
struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
|
||||
struct gpio_desc *desc;
|
||||
+ enum mvebu_pwm_ctrl id;
|
||||
unsigned long flags;
|
||||
int ret = 0;
|
||||
+ struct mvebu_pwm_chip_drv *chip_data;
|
||||
|
||||
- spin_lock_irqsave(&mvpwm->lock, flags);
|
||||
+ spin_lock_irqsave(&mvpwm->controller.lock, flags);
|
||||
|
||||
- if (mvpwm->gpiod) {
|
||||
- ret = -EBUSY;
|
||||
- } else {
|
||||
- desc = gpiochip_request_own_desc(&mvchip->chip,
|
||||
+ regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
|
||||
+ &mvchip->blink_en_reg);
|
||||
+
|
||||
+ if (pwm->chip_data || (mvchip->blink_en_reg & BIT(pwm->hwpwm)))
|
||||
+ return -EBUSY;
|
||||
+
|
||||
+ desc = gpiochip_request_own_desc(&mvchip->chip,
|
||||
pwm->hwpwm, "mvebu-pwm",
|
||||
GPIO_ACTIVE_HIGH,
|
||||
GPIOD_OUT_LOW);
|
||||
- if (IS_ERR(desc)) {
|
||||
- ret = PTR_ERR(desc);
|
||||
- goto out;
|
||||
- }
|
||||
+ if (IS_ERR(desc)) {
|
||||
+ ret = PTR_ERR(desc);
|
||||
+ goto out;
|
||||
+ }
|
||||
+
|
||||
+ ret = gpiod_direction_output(desc, 0);
|
||||
+ if (ret) {
|
||||
+ gpiochip_free_own_desc(desc);
|
||||
+ goto out;
|
||||
+ }
|
||||
|
||||
- mvpwm->gpiod = desc;
|
||||
+ chip_data = kzalloc(sizeof(struct mvebu_pwm_chip_drv), GFP_KERNEL);
|
||||
+ if (!chip_data) {
|
||||
+ gpiochip_free_own_desc(desc);
|
||||
+ ret = -ENOMEM;
|
||||
+ goto out;
|
||||
}
|
||||
+
|
||||
+ for (id = MVEBU_PWM_CTRL_SET_A;id < MVEBU_PWM_CTRL_MAX; id++) {
|
||||
+ if (!mvebu_pwm_list[id]->in_use) {
|
||||
+ chip_data->ctrl = id;
|
||||
+ chip_data->master = true;
|
||||
+ mvebu_pwm_list[id]->in_use = true;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (!chip_data->master)
|
||||
+ chip_data->ctrl = mvpwm->default_counter;
|
||||
+
|
||||
+ regmap_update_bits(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
|
||||
+ BIT(pwm->hwpwm), chip_data->ctrl ? BIT(pwm->hwpwm) : 0);
|
||||
+
|
||||
+ chip_data->gpiod = desc;
|
||||
+ pwm->chip_data = chip_data;
|
||||
+
|
||||
+ regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
|
||||
+ &mvpwm->blink_select);
|
||||
+
|
||||
out:
|
||||
- spin_unlock_irqrestore(&mvpwm->lock, flags);
|
||||
+ spin_unlock_irqrestore(&mvpwm->controller.lock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
|
||||
+ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data;
|
||||
unsigned long flags;
|
||||
|
||||
- spin_lock_irqsave(&mvpwm->lock, flags);
|
||||
- gpiochip_free_own_desc(mvpwm->gpiod);
|
||||
- mvpwm->gpiod = NULL;
|
||||
- spin_unlock_irqrestore(&mvpwm->lock, flags);
|
||||
+ spin_lock_irqsave(&mvpwm->controller.lock, flags);
|
||||
+ if (chip_data->master)
|
||||
+ mvebu_pwm_list[chip_data->ctrl]->in_use = false;
|
||||
+
|
||||
+ gpiochip_free_own_desc(chip_data->gpiod);
|
||||
+ kfree(chip_data);
|
||||
+ pwm->chip_data = NULL;
|
||||
+ spin_unlock_irqrestore(&mvpwm->controller.lock, flags);
|
||||
}
|
||||
|
||||
static void mvebu_pwm_get_state(struct pwm_chip *chip,
|
||||
@@ -721,19 +763,21 @@ static void mvebu_pwm_get_state(struct p
|
||||
else
|
||||
state->enabled = false;
|
||||
|
||||
- spin_unlock_irqrestore(&mvpwm->lock, flags);
|
||||
+ spin_unlock_irqrestore(&controller->lock, flags);
|
||||
}
|
||||
|
||||
static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||
const struct pwm_state *state)
|
||||
{
|
||||
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
|
||||
+ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data;
|
||||
+ struct mvebu_pwmchip *controller = mvebu_pwm_list[chip_data->ctrl];
|
||||
struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
|
||||
unsigned long long val;
|
||||
unsigned long flags;
|
||||
unsigned int on, off;
|
||||
|
||||
- val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
|
||||
+ val = (unsigned long long) controller->clk_rate * state->duty_cycle;
|
||||
do_div(val, NSEC_PER_SEC);
|
||||
if (val > UINT_MAX)
|
||||
return -EINVAL;
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
--- a/drivers/gpio/gpio-mvebu.c
|
||||
+++ b/drivers/gpio/gpio-mvebu.c
|
||||
@@ -93,20 +93,41 @@
|
||||
|
||||
#define MVEBU_MAX_GPIO_PER_BANK 32
|
||||
|
||||
-struct mvebu_pwm {
|
||||
+enum mvebu_pwm_ctrl {
|
||||
+ MVEBU_PWM_CTRL_SET_A = 0,
|
||||
+ MVEBU_PWM_CTRL_SET_B,
|
||||
+ MVEBU_PWM_CTRL_MAX
|
||||
+};
|
||||
+
|
||||
+struct mvebu_pwmchip {
|
||||
void __iomem *membase;
|
||||
unsigned long clk_rate;
|
||||
+ spinlock_t lock;
|
||||
+ bool in_use;
|
||||
+
|
||||
+ /* Used to preserve GPIO/PWM registers across suspend/resume */
|
||||
+ u32 blink_on_duration;
|
||||
+ u32 blink_off_duration;
|
||||
+};
|
||||
+
|
||||
+struct mvebu_pwm_chip_drv {
|
||||
+ enum mvebu_pwm_ctrl ctrl;
|
||||
struct gpio_desc *gpiod;
|
||||
+ bool master;
|
||||
+};
|
||||
+
|
||||
+struct mvebu_pwm {
|
||||
struct pwm_chip chip;
|
||||
- spinlock_t lock;
|
||||
struct mvebu_gpio_chip *mvchip;
|
||||
+ struct mvebu_pwmchip controller;
|
||||
+ enum mvebu_pwm_ctrl default_counter;
|
||||
|
||||
/* Used to preserve GPIO/PWM registers across suspend/resume */
|
||||
u32 blink_select;
|
||||
- u32 blink_on_duration;
|
||||
- u32 blink_off_duration;
|
||||
};
|
||||
|
||||
+static struct mvebu_pwmchip *mvebu_pwm_list[MVEBU_PWM_CTRL_MAX];
|
||||
+
|
||||
struct mvebu_gpio_chip {
|
||||
struct gpio_chip chip;
|
||||
struct regmap *regs;
|
||||
@@ -283,12 +304,12 @@ mvebu_gpio_write_level_mask(struct mvebu
|
||||
* Functions returning addresses of individual registers for a given
|
||||
* PWM controller.
|
||||
*/
|
||||
-static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
|
||||
+static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwmchip *mvpwm)
|
||||
{
|
||||
return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
|
||||
}
|
||||
|
||||
-static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
|
||||
+static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwmchip *mvpwm)
|
||||
{
|
||||
return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
|
||||
}
|
||||
@@ -723,17 +744,24 @@ static void mvebu_pwm_get_state(struct p
|
||||
struct pwm_state *state) {
|
||||
|
||||
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
|
||||
+ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data;
|
||||
+ struct mvebu_pwmchip *controller;
|
||||
struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
|
||||
unsigned long long val;
|
||||
unsigned long flags;
|
||||
u32 u;
|
||||
|
||||
- spin_lock_irqsave(&mvpwm->lock, flags);
|
||||
+ if (chip_data)
|
||||
+ controller = mvebu_pwm_list[chip_data->ctrl];
|
||||
+ else
|
||||
+ controller = &mvpwm->controller;
|
||||
+
|
||||
+ spin_lock_irqsave(&controller->lock, flags);
|
||||
|
||||
val = (unsigned long long)
|
||||
- readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
|
||||
+ readl_relaxed(mvebu_pwmreg_blink_on_duration(controller));
|
||||
val *= NSEC_PER_SEC;
|
||||
- do_div(val, mvpwm->clk_rate);
|
||||
+ do_div(val, controller->clk_rate);
|
||||
if (val > UINT_MAX)
|
||||
state->duty_cycle = UINT_MAX;
|
||||
else if (val)
|
||||
@@ -742,9 +770,9 @@ static void mvebu_pwm_get_state(struct p
|
||||
state->duty_cycle = 1;
|
||||
|
||||
val = (unsigned long long)
|
||||
- readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
|
||||
+ readl_relaxed(mvebu_pwmreg_blink_off_duration(controller));
|
||||
val *= NSEC_PER_SEC;
|
||||
- do_div(val, mvpwm->clk_rate);
|
||||
+ do_div(val, controller->clk_rate);
|
||||
if (val < state->duty_cycle) {
|
||||
state->period = 1;
|
||||
} else {
|
||||
@@ -786,7 +814,7 @@ static int mvebu_pwm_apply(struct pwm_ch
|
||||
else
|
||||
on = 1;
|
||||
|
||||
- val = (unsigned long long) mvpwm->clk_rate *
|
||||
+ val = (unsigned long long) controller->clk_rate *
|
||||
(state->period - state->duty_cycle);
|
||||
do_div(val, NSEC_PER_SEC);
|
||||
if (val > UINT_MAX)
|
||||
@@ -796,16 +824,16 @@ static int mvebu_pwm_apply(struct pwm_ch
|
||||
else
|
||||
off = 1;
|
||||
|
||||
- spin_lock_irqsave(&mvpwm->lock, flags);
|
||||
+ spin_lock_irqsave(&controller->lock, flags);
|
||||
|
||||
- writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
|
||||
- writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
|
||||
+ writel_relaxed(on, mvebu_pwmreg_blink_on_duration(controller));
|
||||
+ writel_relaxed(off, mvebu_pwmreg_blink_off_duration(controller));
|
||||
if (state->enabled)
|
||||
mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
|
||||
else
|
||||
mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
|
||||
|
||||
- spin_unlock_irqrestore(&mvpwm->lock, flags);
|
||||
+ spin_unlock_irqrestore(&controller->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -824,10 +852,10 @@ static void __maybe_unused mvebu_pwm_sus
|
||||
|
||||
regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
|
||||
&mvpwm->blink_select);
|
||||
- mvpwm->blink_on_duration =
|
||||
- readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
|
||||
- mvpwm->blink_off_duration =
|
||||
- readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
|
||||
+ mvpwm->controller.blink_on_duration =
|
||||
+ readl_relaxed(mvebu_pwmreg_blink_on_duration(&mvpwm->controller));
|
||||
+ mvpwm->controller.blink_off_duration =
|
||||
+ readl_relaxed(mvebu_pwmreg_blink_off_duration(&mvpwm->controller));
|
||||
}
|
||||
|
||||
static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
|
||||
@@ -836,10 +864,10 @@ static void __maybe_unused mvebu_pwm_res
|
||||
|
||||
regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
|
||||
mvpwm->blink_select);
|
||||
- writel_relaxed(mvpwm->blink_on_duration,
|
||||
- mvebu_pwmreg_blink_on_duration(mvpwm));
|
||||
- writel_relaxed(mvpwm->blink_off_duration,
|
||||
- mvebu_pwmreg_blink_off_duration(mvpwm));
|
||||
+ writel_relaxed(mvpwm->controller.blink_on_duration,
|
||||
+ mvebu_pwmreg_blink_on_duration(&mvpwm->controller));
|
||||
+ writel_relaxed(mvpwm->controller.blink_off_duration,
|
||||
+ mvebu_pwmreg_blink_off_duration(&mvpwm->controller));
|
||||
}
|
||||
|
||||
static int mvebu_pwm_probe(struct platform_device *pdev,
|
||||
@@ -849,6 +877,7 @@ static int mvebu_pwm_probe(struct platfo
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mvebu_pwm *mvpwm;
|
||||
u32 set;
|
||||
+ enum mvebu_pwm_ctrl ctrl_set;
|
||||
|
||||
if (!of_device_is_compatible(mvchip->chip.of_node,
|
||||
"marvell,armada-370-gpio"))
|
||||
@@ -870,12 +899,15 @@ static int mvebu_pwm_probe(struct platfo
|
||||
* Use set A for lines of GPIO chip with id 0, B for GPIO chip
|
||||
* with id 1. Don't allow further GPIO chips to be used for PWM.
|
||||
*/
|
||||
- if (id == 0)
|
||||
+ if (id == 0) {
|
||||
set = 0;
|
||||
- else if (id == 1)
|
||||
+ ctrl_set = MVEBU_PWM_CTRL_SET_A;
|
||||
+ } else if (id == 1) {
|
||||
set = U32_MAX;
|
||||
- else
|
||||
+ ctrl_set = MVEBU_PWM_CTRL_SET_B;
|
||||
+ } else {
|
||||
return -EINVAL;
|
||||
+ }
|
||||
regmap_write(mvchip->regs,
|
||||
GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
|
||||
|
||||
@@ -885,15 +917,13 @@ static int mvebu_pwm_probe(struct platfo
|
||||
mvchip->mvpwm = mvpwm;
|
||||
mvpwm->mvchip = mvchip;
|
||||
|
||||
- mvpwm->membase = devm_platform_ioremap_resource_byname(pdev, "pwm");
|
||||
- if (IS_ERR(mvpwm->membase))
|
||||
- return PTR_ERR(mvpwm->membase);
|
||||
-
|
||||
- mvpwm->clk_rate = clk_get_rate(mvchip->clk);
|
||||
- if (!mvpwm->clk_rate) {
|
||||
- dev_err(dev, "failed to get clock rate\n");
|
||||
+ mvpwm->controller.membase = devm_platform_ioremap_resource_byname(pdev, "pwm");
|
||||
+ if (IS_ERR(mvpwm->controller.membase))
|
||||
+ return PTR_ERR(mvpwm->controller.membase);
|
||||
+
|
||||
+ mvpwm->controller.clk_rate = clk_get_rate(mvchip->clk);
|
||||
+ if (!mvpwm->controller.clk_rate)
|
||||
return -EINVAL;
|
||||
- }
|
||||
|
||||
mvpwm->chip.dev = dev;
|
||||
mvpwm->chip.ops = &mvebu_pwm_ops;
|
||||
@@ -906,7 +936,9 @@ static int mvebu_pwm_probe(struct platfo
|
||||
*/
|
||||
mvpwm->chip.base = -1;
|
||||
|
||||
- spin_lock_init(&mvpwm->lock);
|
||||
+ spin_lock_init(&mvpwm->controller.lock);
|
||||
+ mvpwm->default_counter = ctrl_set;
|
||||
+ mvebu_pwm_list[ctrl_set] = &mvpwm->controller;
|
||||
|
||||
return pwmchip_add(&mvpwm->chip);
|
||||
}
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
--- a/drivers/net/wireless/ath/regd.c
|
||||
+++ b/drivers/net/wireless/ath/regd.c
|
||||
@@ -50,12 +50,9 @@ static int __ath_regd_init(struct ath_re
|
||||
#define ATH_5GHZ_5725_5850 REG_RULE(5725-10, 5850+10, 80, 0, 30,\
|
||||
NL80211_RRF_NO_IR)
|
||||
|
||||
-#define ATH_2GHZ_ALL ATH_2GHZ_CH01_11, \
|
||||
- ATH_2GHZ_CH12_13, \
|
||||
- ATH_2GHZ_CH14
|
||||
+#define ATH_2GHZ_ALL REG_RULE(2400, 2483, 40, 0, 30, 0)
|
||||
|
||||
-#define ATH_5GHZ_ALL ATH_5GHZ_5150_5350, \
|
||||
- ATH_5GHZ_5470_5850
|
||||
+#define ATH_5GHZ_ALL REG_RULE(5140, 5860, 40, 0, 30, 0)
|
||||
|
||||
/* This one skips what we call "mid band" */
|
||||
#define ATH_5GHZ_NO_MIDBAND ATH_5GHZ_5150_5350, \
|
||||
@@ -77,9 +74,8 @@ static const struct ieee80211_regdomain
|
||||
.n_reg_rules = 4,
|
||||
.alpha2 = "99",
|
||||
.reg_rules = {
|
||||
- ATH_2GHZ_CH01_11,
|
||||
- ATH_2GHZ_CH12_13,
|
||||
- ATH_5GHZ_NO_MIDBAND,
|
||||
+ ATH_2GHZ_ALL,
|
||||
+ ATH_5GHZ_ALL,
|
||||
}
|
||||
};
|
||||
|
||||
@@ -88,8 +84,8 @@ static const struct ieee80211_regdomain
|
||||
.n_reg_rules = 3,
|
||||
.alpha2 = "99",
|
||||
.reg_rules = {
|
||||
- ATH_2GHZ_CH01_11,
|
||||
- ATH_5GHZ_NO_MIDBAND,
|
||||
+ ATH_2GHZ_ALL,
|
||||
+ ATH_5GHZ_ALL,
|
||||
}
|
||||
};
|
||||
|
||||
@@ -98,7 +94,7 @@ static const struct ieee80211_regdomain
|
||||
.n_reg_rules = 3,
|
||||
.alpha2 = "99",
|
||||
.reg_rules = {
|
||||
- ATH_2GHZ_CH01_11,
|
||||
+ ATH_2GHZ_ALL,
|
||||
ATH_5GHZ_ALL,
|
||||
}
|
||||
};
|
||||
@@ -108,8 +104,7 @@ static const struct ieee80211_regdomain
|
||||
.n_reg_rules = 4,
|
||||
.alpha2 = "99",
|
||||
.reg_rules = {
|
||||
- ATH_2GHZ_CH01_11,
|
||||
- ATH_2GHZ_CH12_13,
|
||||
+ ATH_2GHZ_ALL,
|
||||
ATH_5GHZ_ALL,
|
||||
}
|
||||
};
|
||||
@@ -258,9 +253,7 @@ static bool ath_is_radar_freq(u16 center
|
||||
struct ath_regulatory *reg)
|
||||
|
||||
{
|
||||
- if (reg->country_code == CTRY_INDIA)
|
||||
- return (center_freq >= 5500 && center_freq <= 5700);
|
||||
- return (center_freq >= 5260 && center_freq <= 5700);
|
||||
+ return false;
|
||||
}
|
||||
|
||||
static void ath_force_clear_no_ir_chan(struct wiphy *wiphy,
|
||||
39
patch/kernel/mvebu-dev/use-1000BaseX-clearfog-switch.patch
Normal file
39
patch/kernel/mvebu-dev/use-1000BaseX-clearfog-switch.patch
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
From 219f80b5cc03dab87fd05210b95c0b1a5afa8d33 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Thu, 14 Jul 2016 15:31:42 +0100
|
||||
Subject: ARM: dts: armada388-clearfog: use 1000BaseX mode for 88e6176 switch
|
||||
|
||||
Use 1000BaseX mode for the 88e6176 switch, which allows mvneta to
|
||||
negotiate correctly without needing to be forced.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
arch/arm/boot/dts/armada-388-clearfog.dts | 10 ++--------
|
||||
1 file changed, 2 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
|
||||
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
||||
@@ -47,10 +47,8 @@
|
||||
|
||||
ð1 {
|
||||
/* ethernet@30000 */
|
||||
- fixed-link {
|
||||
- speed = <1000>;
|
||||
- full-duplex;
|
||||
- };
|
||||
+ phy-mode = "1000base-x";
|
||||
+ managed = "in-band-status";
|
||||
};
|
||||
|
||||
&expander0 {
|
||||
@@ -131,10 +129,6 @@
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
ethernet = <ð1>;
|
||||
- fixed-link {
|
||||
- speed = <1000>;
|
||||
- full-duplex;
|
||||
- };
|
||||
};
|
||||
|
||||
port@6 {
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
diff --git a/drivers/net/wireless/rtl8811cu/include/rtw_security.h b/drivers/net/wireless/rtl8811cu/include/rtw_security.h
|
||||
index ac8432e..5f74fb7 100755
|
||||
--- a/drivers/net/wireless/rtl8811cu/include/rtw_security.h
|
||||
+++ b/drivers/net/wireless/rtl8811cu/include/rtw_security.h
|
||||
@@ -249,7 +249,7 @@ struct security_priv {
|
||||
#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE
|
||||
#endif
|
||||
|
||||
-struct sha256_state {
|
||||
+struct rtl_sha256_state {
|
||||
u64 length;
|
||||
u32 state[8], curlen;
|
||||
u8 buf[64];
|
||||
diff --git a/drivers/net/wireless/rtl8811cu/core/rtw_security.c b/drivers/net/wireless/rtl8811cu/core/rtw_security.c
|
||||
index b537a26..f8c42f4 100755
|
||||
--- a/drivers/net/wireless/rtl8811cu/core/rtw_security.c
|
||||
+++ b/drivers/net/wireless/rtl8811cu/core/rtw_security.c
|
||||
@@ -2133,7 +2133,7 @@ BIP_exit:
|
||||
#ifndef PLATFORM_FREEBSD
|
||||
#if defined(CONFIG_TDLS)
|
||||
/* compress 512-bits */
|
||||
-static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
+static int sha256_compress(struct rtl_sha256_state *md, unsigned char *buf)
|
||||
{
|
||||
u32 S[8], W[64], t0, t1;
|
||||
u32 t;
|
||||
@@ -2181,7 +2181,7 @@ static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
}
|
||||
|
||||
/* Initialize the hash state */
|
||||
-static void sha256_init(struct sha256_state *md)
|
||||
+static void sha256_init(struct rtl_sha256_state *md)
|
||||
{
|
||||
md->curlen = 0;
|
||||
md->length = 0;
|
||||
@@ -2202,7 +2202,7 @@ static void sha256_init(struct sha256_state *md)
|
||||
@param inlen The length of the data (octets)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
+static int sha256_process(struct rtl_sha256_state *md, unsigned char *in,
|
||||
unsigned long inlen)
|
||||
{
|
||||
unsigned long n;
|
||||
@@ -2243,7 +2243,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
@param out [out] The destination of the hash (32 bytes)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
+static int sha256_done(struct rtl_sha256_state *md, unsigned char *out)
|
||||
{
|
||||
int i;
|
||||
|
||||
@@ -2293,7 +2293,7 @@ static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,
|
||||
u8 *mac)
|
||||
{
|
||||
- struct sha256_state ctx;
|
||||
+ struct rtl_sha256_state ctx;
|
||||
size_t i;
|
||||
|
||||
sha256_init(&ctx);
|
||||
|
|
@ -1 +0,0 @@
|
|||
mvebu64-current
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
From ff4e9b1be3e48ed22f30145fbccfaa49c8e87d10 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
|
||||
Date: Wed, 7 Oct 2020 21:35:20 +0200
|
||||
Subject: [PATCH 01/10] arm64: dts: marvell: armada-37xx: add syscon compatible
|
||||
to NB clk node
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Add "syscon" compatible to the North Bridge clocks node to allow the
|
||||
cpufreq driver to access these registers via syscon API.
|
||||
|
||||
This is needed for a fix of cpufreq driver.
|
||||
|
||||
Signed-off-by: Marek Behún <kabel@kernel.org>
|
||||
Fixes: e8d66e7927b2 ("arm64: dts: marvell: armada-37xx: add nodes...")
|
||||
Cc: stable@vger.kernel.org
|
||||
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
---
|
||||
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
||||
index d5b6c0a1c54a..a89e47d95eef 100644
|
||||
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
||||
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
||||
@@ -156,7 +156,8 @@ uart1: serial@12200 {
|
||||
};
|
||||
|
||||
nb_periph_clk: nb-periph-clk@13000 {
|
||||
- compatible = "marvell,armada-3700-periph-clock-nb";
|
||||
+ compatible = "marvell,armada-3700-periph-clock-nb",
|
||||
+ "syscon";
|
||||
reg = <0x13000 0x100>;
|
||||
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
|
||||
<&tbg 3>, <&xtalclk>;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
From a900d6500bd22863d7fea47a25aefa2c9faab0fe Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
|
||||
Date: Wed, 7 Oct 2020 21:35:21 +0200
|
||||
Subject: [PATCH 02/10] cpufreq: armada-37xx: Fix setting TBG parent for load
|
||||
levels
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
With CPU frequency determining software [1] we have discovered that
|
||||
after this driver does one CPU frequency change, the base frequency of
|
||||
the CPU is set to the frequency of TBG-A-P clock, instead of the TBG
|
||||
that is parent to the CPU.
|
||||
|
||||
This can be reproduced on EspressoBIN and Turris MOX:
|
||||
cd /sys/devices/system/cpu/cpufreq/policy0
|
||||
echo powersave >scaling_governor
|
||||
echo performance >scaling_governor
|
||||
|
||||
Running the mhz tool before this driver is loaded reports 1000 MHz, and
|
||||
after loading the driver and executing commands above the tool reports
|
||||
800 MHz.
|
||||
|
||||
The change of TBG clock selector is supposed to happen in function
|
||||
armada37xx_cpufreq_dvfs_setup. Before the function returns, it does
|
||||
this:
|
||||
parent = clk_get_parent(clk);
|
||||
clk_set_parent(clk, parent);
|
||||
|
||||
The armada-37xx-periph clock driver has the .set_parent method
|
||||
implemented correctly for this, so if the method was actually called,
|
||||
this would work. But since the introduction of the common clock
|
||||
framework in commit b2476490ef11 ("clk: introduce the common clock..."),
|
||||
the clk_set_parent function checks whether the parent is actually
|
||||
changing, and if the requested new parent is same as the old parent
|
||||
(which is obviously the case for the code above), the .set_parent method
|
||||
is not called at all.
|
||||
|
||||
This patch fixes this issue by filling the correct TBG clock selector
|
||||
directly in the armada37xx_cpufreq_dvfs_setup during the filling of
|
||||
other registers at the same address. But the determination of CPU TBG
|
||||
index cannot be done via the common clock framework, therefore we need
|
||||
to access the North Bridge Peripheral Clock registers directly in this
|
||||
driver.
|
||||
|
||||
[1] https://github.com/wtarreau/mhz
|
||||
|
||||
Signed-off-by: Marek Behún <kabel@kernel.org>
|
||||
Fixes: 92ce45fb875d ("cpufreq: Add DVFS support for Armada 37xx")
|
||||
Cc: stable@vger.kernel.org
|
||||
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
|
||||
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
---
|
||||
drivers/cpufreq/armada-37xx-cpufreq.c | 35 ++++++++++++++++++---------
|
||||
1 file changed, 23 insertions(+), 12 deletions(-)
|
||||
|
||||
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
index b4af4094309b..b8dc6c849579 100644
|
||||
--- a/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
@@ -25,6 +25,10 @@
|
||||
|
||||
#include "cpufreq-dt.h"
|
||||
|
||||
+/* Clk register set */
|
||||
+#define ARMADA_37XX_CLK_TBG_SEL 0
|
||||
+#define ARMADA_37XX_CLK_TBG_SEL_CPU_OFF 22
|
||||
+
|
||||
/* Power management in North Bridge register set */
|
||||
#define ARMADA_37XX_NB_L0L1 0x18
|
||||
#define ARMADA_37XX_NB_L2L3 0x1C
|
||||
@@ -120,10 +124,15 @@ static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
|
||||
* will be configured then the DVFS will be enabled.
|
||||
*/
|
||||
static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
|
||||
- struct clk *clk, u8 *divider)
|
||||
+ struct regmap *clk_base, u8 *divider)
|
||||
{
|
||||
+ u32 cpu_tbg_sel;
|
||||
int load_lvl;
|
||||
- struct clk *parent;
|
||||
+
|
||||
+ /* Determine to which TBG clock is CPU connected */
|
||||
+ regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel);
|
||||
+ cpu_tbg_sel >>= ARMADA_37XX_CLK_TBG_SEL_CPU_OFF;
|
||||
+ cpu_tbg_sel &= ARMADA_37XX_NB_TBG_SEL_MASK;
|
||||
|
||||
for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
|
||||
unsigned int reg, mask, val, offset = 0;
|
||||
@@ -142,6 +151,11 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
|
||||
mask = (ARMADA_37XX_NB_CLK_SEL_MASK
|
||||
<< ARMADA_37XX_NB_CLK_SEL_OFF);
|
||||
|
||||
+ /* Set TBG index, for all levels we use the same TBG */
|
||||
+ val = cpu_tbg_sel << ARMADA_37XX_NB_TBG_SEL_OFF;
|
||||
+ mask = (ARMADA_37XX_NB_TBG_SEL_MASK
|
||||
+ << ARMADA_37XX_NB_TBG_SEL_OFF);
|
||||
+
|
||||
/*
|
||||
* Set cpu divider based on the pre-computed array in
|
||||
* order to have balanced step.
|
||||
@@ -160,14 +174,6 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
|
||||
|
||||
regmap_update_bits(base, reg, mask, val);
|
||||
}
|
||||
-
|
||||
- /*
|
||||
- * Set cpu clock source, for all the level we keep the same
|
||||
- * clock source that the one already configured. For this one
|
||||
- * we need to use the clock framework
|
||||
- */
|
||||
- parent = clk_get_parent(clk);
|
||||
- clk_set_parent(clk, parent);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -358,11 +364,16 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
struct platform_device *pdev;
|
||||
unsigned long freq;
|
||||
unsigned int cur_frequency, base_frequency;
|
||||
- struct regmap *nb_pm_base, *avs_base;
|
||||
+ struct regmap *nb_clk_base, *nb_pm_base, *avs_base;
|
||||
struct device *cpu_dev;
|
||||
int load_lvl, ret;
|
||||
struct clk *clk, *parent;
|
||||
|
||||
+ nb_clk_base =
|
||||
+ syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb");
|
||||
+ if (IS_ERR(nb_clk_base))
|
||||
+ return -ENODEV;
|
||||
+
|
||||
nb_pm_base =
|
||||
syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
|
||||
|
||||
@@ -439,7 +450,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
armada37xx_cpufreq_avs_configure(avs_base, dvfs);
|
||||
armada37xx_cpufreq_avs_setup(avs_base, dvfs);
|
||||
|
||||
- armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
|
||||
+ armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider);
|
||||
clk_put(clk);
|
||||
|
||||
for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
From 18304427b4ca4b97c76759553ea64341ea8cd2eb Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
|
||||
Date: Wed, 7 Oct 2020 21:35:22 +0200
|
||||
Subject: [PATCH 03/10] clk: mvebu: armada-37xx-periph: remove .set_parent
|
||||
method for CPU PM clock
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Remove the .set_parent method in clk_pm_cpu_ops.
|
||||
|
||||
This method was supposed to be needed by the armada-37xx-cpufreq driver,
|
||||
but was never actually called due to wrong assumptions in the cpufreq
|
||||
driver. After this was fixed in the cpufreq driver, this method is not
|
||||
needed anymore.
|
||||
|
||||
Signed-off-by: Marek Behún <kabel@kernel.org>
|
||||
Fixes: 2089dc33ea0e ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks")
|
||||
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
|
||||
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
---
|
||||
drivers/clk/mvebu/armada-37xx-periph.c | 28 --------------------------
|
||||
1 file changed, 28 deletions(-)
|
||||
|
||||
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
|
||||
index f5746f9ea929..6507bd2c5f31 100644
|
||||
--- a/drivers/clk/mvebu/armada-37xx-periph.c
|
||||
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
|
||||
@@ -440,33 +440,6 @@ static u8 clk_pm_cpu_get_parent(struct clk_hw *hw)
|
||||
return val;
|
||||
}
|
||||
|
||||
-static int clk_pm_cpu_set_parent(struct clk_hw *hw, u8 index)
|
||||
-{
|
||||
- struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
|
||||
- struct regmap *base = pm_cpu->nb_pm_base;
|
||||
- int load_level;
|
||||
-
|
||||
- /*
|
||||
- * We set the clock parent only if the DVFS is available but
|
||||
- * not enabled.
|
||||
- */
|
||||
- if (IS_ERR(base) || armada_3700_pm_dvfs_is_enabled(base))
|
||||
- return -EINVAL;
|
||||
-
|
||||
- /* Set the parent clock for all the load level */
|
||||
- for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
|
||||
- unsigned int reg, mask, val,
|
||||
- offset = ARMADA_37XX_NB_TBG_SEL_OFF;
|
||||
-
|
||||
- armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
|
||||
-
|
||||
- val = index << offset;
|
||||
- mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset;
|
||||
- regmap_update_bits(base, reg, mask, val);
|
||||
- }
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
@@ -592,7 +565,6 @@ static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
||||
static const struct clk_ops clk_pm_cpu_ops = {
|
||||
.get_parent = clk_pm_cpu_get_parent,
|
||||
- .set_parent = clk_pm_cpu_set_parent,
|
||||
.round_rate = clk_pm_cpu_round_rate,
|
||||
.set_rate = clk_pm_cpu_set_rate,
|
||||
.recalc_rate = clk_pm_cpu_recalc_rate,
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
From edbd075dec02474616bcd83540ac6e90a7822a1c Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
||||
Date: Thu, 8 Oct 2020 18:01:05 +0200
|
||||
Subject: [PATCH 04/10] cpufreq: armada-37xx: Fix the AVS value for loads L0
|
||||
and L1
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
The original CPU voltage value for load L1 is too low for Armada-37xx SoC
|
||||
when base CPU frequency is 1000 or 1200 MHz. It leads to instabilities
|
||||
where CPU gets stuck soon after dynamic voltage scaling from load L1 to L0.
|
||||
|
||||
Update the CPU voltage value for loads L0 and L1 accordingly when base
|
||||
frequency is 1000 or 1200 MHz. The minimal value is updated from the
|
||||
original 1.05V to 1.108V.
|
||||
|
||||
This change fixes instability issues on 1 GHz variant of Espressobin and
|
||||
Turris MOX. It is based on previous work from Victor Gu <xigu@marvell.com>
|
||||
for Espressobin kernel 4.4 [1]. Discussion about this issue is also at
|
||||
armbian forum [2].
|
||||
|
||||
[1] - https://github.com/MarvellEmbeddedProcessors/linux-marvell/commit/dc33b62c90696afb6adc7dbcc4ebbd48bedec269
|
||||
[2] - https://forum.armbian.com/topic/10429-how-to-make-espressobin-v7-stable/
|
||||
|
||||
Signed-off-by: Pali Rohár <pali@kernel.org>
|
||||
Fixes: 1c3528232f4b ("cpufreq: armada-37xx: Add AVS support")
|
||||
Cc: stable@vger.kernel.org
|
||||
---
|
||||
drivers/cpufreq/armada-37xx-cpufreq.c | 26 ++++++++++++++++++++++++++
|
||||
1 file changed, 26 insertions(+)
|
||||
|
||||
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
index b8dc6c849579..92e531f700f4 100644
|
||||
--- a/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
@@ -73,6 +73,7 @@
|
||||
#define LOAD_LEVEL_NR 4
|
||||
|
||||
#define MIN_VOLT_MV 1000
|
||||
+#define MIN_VOLT_MV_FOR_L0_L1_1GHZ 1108
|
||||
|
||||
/* AVS value for the corresponding voltage (in mV) */
|
||||
static int avs_map[] = {
|
||||
@@ -208,6 +209,8 @@ static u32 armada_37xx_avs_val_match(int target_vm)
|
||||
* - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
|
||||
* This function calculates L1 & L2 & L3 AVS values dynamically based
|
||||
* on L0 voltage and fill all AVS values to the AVS value table.
|
||||
+ * When base CPU frequency is 1000 or 1200 MHz then there is additional
|
||||
+ * minimal avs value for load L0 and L1.
|
||||
*/
|
||||
static void __init armada37xx_cpufreq_avs_configure(struct regmap *base,
|
||||
struct armada_37xx_dvfs *dvfs)
|
||||
@@ -239,6 +242,15 @@ static void __init armada37xx_cpufreq_avs_configure(struct regmap *base,
|
||||
for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++)
|
||||
dvfs->avs[load_level] = avs_min;
|
||||
|
||||
+ /*
|
||||
+ * Set the avs value for load L0 and L1 when base CPU frequency is 1000/1200 MHz,
|
||||
+ * otherwise the CPU gets stuck when switching from load L1 to load L0
|
||||
+ */
|
||||
+ if (dvfs->cpu_freq_max >= 1000*1000*1000) {
|
||||
+ avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L0_L1_1GHZ);
|
||||
+ dvfs->avs[0] = dvfs->avs[1] = avs_min;
|
||||
+ }
|
||||
+
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -258,6 +270,20 @@ static void __init armada37xx_cpufreq_avs_configure(struct regmap *base,
|
||||
target_vm = avs_map[l0_vdd_min] - 150;
|
||||
target_vm = target_vm > MIN_VOLT_MV ? target_vm : MIN_VOLT_MV;
|
||||
dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm);
|
||||
+
|
||||
+ /*
|
||||
+ * Fix the avs value for load L0 and L1 when base CPU frequency is 1000/1200 MHz,
|
||||
+ * otherwise the CPU gets stuck when switching from load L1 to load L0
|
||||
+ */
|
||||
+ if (dvfs->cpu_freq_max >= 1000*1000*1000) {
|
||||
+ u32 avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L0_L1_1GHZ);
|
||||
+
|
||||
+ if (dvfs->avs[0] < avs_min)
|
||||
+ dvfs->avs[0] = avs_min;
|
||||
+
|
||||
+ if (dvfs->avs[1] < avs_min)
|
||||
+ dvfs->avs[1] = avs_min;
|
||||
+ }
|
||||
}
|
||||
|
||||
static void __init armada37xx_cpufreq_avs_setup(struct regmap *base,
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
From 9084ec43ddf97da84add774bd3614ebef20c4c9e Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
||||
Date: Tue, 3 Nov 2020 12:10:36 +0100
|
||||
Subject: [PATCH 05/10] clk: mvebu: armada-37xx-periph: Fix switching CPU freq
|
||||
from 250 Mhz to 1 GHz
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
It was observed that the workaround introduced by commit 61c40f35f5cd
|
||||
("clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to
|
||||
1.2GHz") when base CPU frequency is 1.2 GHz is also required when base
|
||||
CPU frequency is 1 GHz. Otherwise switching CPU frequency directly from
|
||||
L2 (250 MHz) to L0 (1 GHz) causes a crash.
|
||||
|
||||
When base CPU frequency is just 800 MHz no crashed were observed during
|
||||
switch from L2 to L0.
|
||||
|
||||
Signed-off-by: Pali Rohár <pali@kernel.org>
|
||||
Fixes: 2089dc33ea0e ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks")
|
||||
Cc: stable@vger.kernel.org # 61c40f35f5cd ("clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHz")
|
||||
---
|
||||
drivers/clk/mvebu/armada-37xx-periph.c | 12 +++++++-----
|
||||
1 file changed, 7 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
|
||||
index 6507bd2c5f31..b15e177bea7e 100644
|
||||
--- a/drivers/clk/mvebu/armada-37xx-periph.c
|
||||
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
|
||||
@@ -487,8 +487,10 @@ static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
}
|
||||
|
||||
/*
|
||||
- * Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
|
||||
- * respectively) to L0 frequency (1.2 Ghz) requires a significant
|
||||
+ * Workaround when base CPU frequnecy is 1000 or 1200 MHz
|
||||
+ *
|
||||
+ * Switching the CPU from the L2 or L3 frequencies (250/300 or 200 MHz
|
||||
+ * respectively) to L0 frequency (1/1.2 GHz) requires a significant
|
||||
* amount of time to let VDD stabilize to the appropriate
|
||||
* voltage. This amount of time is large enough that it cannot be
|
||||
* covered by the hardware countdown register. Due to this, the CPU
|
||||
@@ -498,15 +500,15 @@ static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
* To work around this problem, we prevent switching directly from the
|
||||
* L2/L3 frequencies to the L0 frequency, and instead switch to the L1
|
||||
* frequency in-between. The sequence therefore becomes:
|
||||
- * 1. First switch from L2/L3(200/300MHz) to L1(600MHZ)
|
||||
+ * 1. First switch from L2/L3 (200/250/300 MHz) to L1 (500/600 MHz)
|
||||
* 2. Sleep 20ms for stabling VDD voltage
|
||||
- * 3. Then switch from L1(600MHZ) to L0(1200Mhz).
|
||||
+ * 3. Then switch from L1 (500/600 MHz) to L0 (1000/1200 MHz).
|
||||
*/
|
||||
static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base)
|
||||
{
|
||||
unsigned int cur_level;
|
||||
|
||||
- if (rate != 1200 * 1000 * 1000)
|
||||
+ if (rate < 1000 * 1000 * 1000)
|
||||
return;
|
||||
|
||||
regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level);
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
From 21e93728fff921ff01aceee6c80d265b2fcb2939 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
||||
Date: Wed, 14 Oct 2020 10:35:51 +0200
|
||||
Subject: [PATCH 06/10] clk: mvebu: armada-37xx-periph: Fix workaround for
|
||||
switching from L1 to L0
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
When CPU frequency is at 250 MHz and set_rate() is called with 500 MHz (L1)
|
||||
quickly followed by a call with 1 GHz (L0), the CPU does not necessarily
|
||||
stay in L1 for at least 20ms as is required by Marvell errata.
|
||||
|
||||
This situation happens frequently with the ondemand cpufreq governor and
|
||||
can be also reproduced with userspace governor. In most cases it causes CPU
|
||||
to crash.
|
||||
|
||||
This change fixes the above issue and ensures that the CPU always stays in
|
||||
L1 for at least 20ms when switching from any state to L0.
|
||||
|
||||
Signed-off-by: Marek Behún <kabel@kernel.org>
|
||||
Signed-off-by: Pali Rohár <pali@kernel.org>
|
||||
Fixes: 61c40f35f5cd ("clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHz")
|
||||
Cc: stable@vger.kernel.org
|
||||
---
|
||||
drivers/clk/mvebu/armada-37xx-periph.c | 45 ++++++++++++++++++++++----
|
||||
1 file changed, 39 insertions(+), 6 deletions(-)
|
||||
|
||||
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
|
||||
index b15e177bea7e..32ac6b6b7530 100644
|
||||
--- a/drivers/clk/mvebu/armada-37xx-periph.c
|
||||
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
|
||||
@@ -84,6 +84,7 @@ struct clk_pm_cpu {
|
||||
void __iomem *reg_div;
|
||||
u8 shift_div;
|
||||
struct regmap *nb_pm_base;
|
||||
+ unsigned long l1_expiration;
|
||||
};
|
||||
|
||||
#define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
|
||||
@@ -504,22 +505,52 @@ static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
* 2. Sleep 20ms for stabling VDD voltage
|
||||
* 3. Then switch from L1 (500/600 MHz) to L0 (1000/1200 MHz).
|
||||
*/
|
||||
-static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base)
|
||||
+static void clk_pm_cpu_set_rate_wa(struct clk_pm_cpu *pm_cpu,
|
||||
+ unsigned int new_level, unsigned long rate,
|
||||
+ struct regmap *base)
|
||||
{
|
||||
unsigned int cur_level;
|
||||
|
||||
- if (rate < 1000 * 1000 * 1000)
|
||||
- return;
|
||||
-
|
||||
regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level);
|
||||
cur_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
|
||||
- if (cur_level <= ARMADA_37XX_DVFS_LOAD_1)
|
||||
+
|
||||
+ if (cur_level == new_level)
|
||||
+ return;
|
||||
+
|
||||
+ /*
|
||||
+ * System wants to go to L1 on its own. If we are going from L2/L3,
|
||||
+ * remember when 20ms will expire. If from L0, set the value so that
|
||||
+ * next switch to L0 won't have to wait.
|
||||
+ */
|
||||
+ if (new_level == ARMADA_37XX_DVFS_LOAD_1) {
|
||||
+ if (cur_level == ARMADA_37XX_DVFS_LOAD_0)
|
||||
+ pm_cpu->l1_expiration = jiffies;
|
||||
+ else
|
||||
+ pm_cpu->l1_expiration = jiffies + msecs_to_jiffies(20);
|
||||
return;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * If we are setting to L2/L3, just invalidate L1 expiration time,
|
||||
+ * sleeping is not needed.
|
||||
+ */
|
||||
+ if (rate < 1000*1000*1000)
|
||||
+ goto invalidate_l1_exp;
|
||||
+
|
||||
+ /*
|
||||
+ * We are going to L0 with rate >= 1GHz. Check whether we have been at
|
||||
+ * L1 for long enough time. If not, go to L1 for 20ms.
|
||||
+ */
|
||||
+ if (pm_cpu->l1_expiration && jiffies >= pm_cpu->l1_expiration)
|
||||
+ goto invalidate_l1_exp;
|
||||
|
||||
regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD,
|
||||
ARMADA_37XX_NB_CPU_LOAD_MASK,
|
||||
ARMADA_37XX_DVFS_LOAD_1);
|
||||
msleep(20);
|
||||
+
|
||||
+invalidate_l1_exp:
|
||||
+ pm_cpu->l1_expiration = 0;
|
||||
}
|
||||
|
||||
static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
@@ -553,7 +584,9 @@ static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
reg = ARMADA_37XX_NB_CPU_LOAD;
|
||||
mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
|
||||
|
||||
- clk_pm_cpu_set_rate_wa(rate, base);
|
||||
+ /* Apply workaround when base CPU frequency is 1000 or 1200 MHz */
|
||||
+ if (parent_rate >= 1000*1000*1000)
|
||||
+ clk_pm_cpu_set_rate_wa(pm_cpu, load_level, rate, base);
|
||||
|
||||
regmap_update_bits(base, reg, mask, load_level);
|
||||
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
From 8440f9edeb29c10cc0ec29c55c07d4e5e5b67c5b Mon Sep 17 00:00:00 2001
|
||||
From: Kevin Mihelich <kevin@archlinuxarm.org>
|
||||
Date: Tue, 4 Jul 2017 19:25:28 -0600
|
||||
Subject: [PATCH 07/11] arm64: dts: marvell: armada37xx: Add eth0 alias
|
||||
|
||||
Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
|
||||
---
|
||||
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
||||
index a78195b4ef7a..14248957b2dd 100644
|
||||
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
||||
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
||||
@@ -54,6 +54,7 @@
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
+ ethernet0 = ð0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
--
|
||||
2.13.3
|
||||
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
From 6facb50e286e10c42791512e17e8599f9f514d82 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
||||
Date: Tue, 20 Oct 2020 16:37:45 +0200
|
||||
Subject: [PATCH 07/10] cpufreq: armada-37xx: Fix driver cleanup when
|
||||
registration failed
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Commit 8db82563451f ("cpufreq: armada-37xx: fix frequency calculation for
|
||||
opp") changed calculation of frequency passed to the dev_pm_opp_add()
|
||||
function call. But the code for dev_pm_opp_remove() function call was not
|
||||
updated, so the driver cleanup phase does not work when registration fails.
|
||||
|
||||
This fixes the issue by using the same frequency in both calls.
|
||||
|
||||
Signed-off-by: Pali Rohár <pali@kernel.org>
|
||||
Fixes: 8db82563451f ("cpufreq: armada-37xx: fix frequency calculation for opp")
|
||||
Cc: stable@vger.kernel.org
|
||||
---
|
||||
drivers/cpufreq/armada-37xx-cpufreq.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
index 92e531f700f4..002a71775e08 100644
|
||||
--- a/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
@@ -510,7 +510,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
remove_opp:
|
||||
/* clean-up the already added opp before leaving */
|
||||
while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
|
||||
- freq = cur_frequency / dvfs->divider[load_lvl];
|
||||
+ freq = base_frequency / dvfs->divider[load_lvl];
|
||||
dev_pm_opp_remove(cpu_dev, freq);
|
||||
}
|
||||
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
From b7a63d67c67bfe3e807f634ac35aea6b09f7dc1c Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
||||
Date: Tue, 20 Oct 2020 16:47:52 +0200
|
||||
Subject: [PATCH 08/10] cpufreq: armada-37xx: Fix determining base CPU
|
||||
frequency
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
When current CPU load is not L0 then loading armada-37xx-cpufreq.ko driver
|
||||
fails with following error:
|
||||
|
||||
# modprobe armada-37xx-cpufreq
|
||||
[ 502.702097] Unsupported CPU frequency 250 MHz
|
||||
|
||||
This issue was partially fixed by commit 8db82563451f ("cpufreq:
|
||||
armada-37xx: fix frequency calculation for opp"), but only for calculating
|
||||
CPU frequency for opp.
|
||||
|
||||
Fix this also for determination of base CPU frequency.
|
||||
|
||||
Signed-off-by: Pali Rohár <pali@kernel.org>
|
||||
Fixes: 92ce45fb875d ("cpufreq: Add DVFS support for Armada 37xx")
|
||||
Cc: stable@vger.kernel.org # 8db82563451f ("cpufreq: armada-37xx: fix frequency calculation for opp")
|
||||
---
|
||||
drivers/cpufreq/armada-37xx-cpufreq.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
index 002a71775e08..f08281fc525c 100644
|
||||
--- a/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
@@ -458,7 +458,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- dvfs = armada_37xx_cpu_freq_info_get(cur_frequency);
|
||||
+ dvfs = armada_37xx_cpu_freq_info_get(base_frequency);
|
||||
if (!dvfs) {
|
||||
clk_put(clk);
|
||||
return -EINVAL;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
From f3274c42504e42a28a288c80f64309b4a915f9b3 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
||||
Date: Tue, 20 Oct 2020 16:57:19 +0200
|
||||
Subject: [PATCH 09/10] cpufreq: armada-37xx: Remove cur_frequency variable
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Variable cur_frequency in armada37xx_cpufreq_driver_init() is unused.
|
||||
|
||||
Signed-off-by: Pali Rohár <pali@kernel.org>
|
||||
---
|
||||
drivers/cpufreq/armada-37xx-cpufreq.c | 10 +---------
|
||||
1 file changed, 1 insertion(+), 9 deletions(-)
|
||||
|
||||
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
index f08281fc525c..f13646d143de 100644
|
||||
--- a/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
@@ -389,7 +389,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
struct armada_37xx_dvfs *dvfs;
|
||||
struct platform_device *pdev;
|
||||
unsigned long freq;
|
||||
- unsigned int cur_frequency, base_frequency;
|
||||
+ unsigned int base_frequency;
|
||||
struct regmap *nb_clk_base, *nb_pm_base, *avs_base;
|
||||
struct device *cpu_dev;
|
||||
int load_lvl, ret;
|
||||
@@ -450,14 +450,6 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- /* Get nominal (current) CPU frequency */
|
||||
- cur_frequency = clk_get_rate(clk);
|
||||
- if (!cur_frequency) {
|
||||
- dev_err(cpu_dev, "Failed to get clock rate for CPU\n");
|
||||
- clk_put(clk);
|
||||
- return -EINVAL;
|
||||
- }
|
||||
-
|
||||
dvfs = armada_37xx_cpu_freq_info_get(base_frequency);
|
||||
if (!dvfs) {
|
||||
clk_put(clk);
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
From 1c2f3373daa919d624f6c28d0d3b024aec5bf55c Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
||||
Date: Tue, 20 Oct 2020 17:04:17 +0200
|
||||
Subject: [PATCH 10/10] cpufreq: armada-37xx: Fix module unloading
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
This driver is missing module_exit hook. Add proper driver exit function
|
||||
which unregisters the platform device and cleans up the data.
|
||||
|
||||
Signed-off-by: Pali Rohár <pali@kernel.org>
|
||||
---
|
||||
drivers/cpufreq/armada-37xx-cpufreq.c | 25 +++++++++++++++++++++++++
|
||||
1 file changed, 25 insertions(+)
|
||||
|
||||
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
index f13646d143de..565c40f536ef 100644
|
||||
--- a/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
@@ -85,6 +85,8 @@ static int avs_map[] = {
|
||||
};
|
||||
|
||||
struct armada37xx_cpufreq_state {
|
||||
+ struct platform_device *pdev;
|
||||
+ struct device *cpu_dev;
|
||||
struct regmap *regmap;
|
||||
u32 nb_l0l1;
|
||||
u32 nb_l2l3;
|
||||
@@ -495,6 +497,9 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
if (ret)
|
||||
goto disable_dvfs;
|
||||
|
||||
+ armada37xx_cpufreq_state->cpu_dev = cpu_dev;
|
||||
+ armada37xx_cpufreq_state->pdev = pdev;
|
||||
+ platform_set_drvdata(pdev, dvfs);
|
||||
return 0;
|
||||
|
||||
disable_dvfs:
|
||||
@@ -513,6 +518,26 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
|
||||
late_initcall(armada37xx_cpufreq_driver_init);
|
||||
|
||||
+static void __exit armada37xx_cpufreq_driver_exit(void)
|
||||
+{
|
||||
+ struct platform_device *pdev = armada37xx_cpufreq_state->pdev;
|
||||
+ struct armada_37xx_dvfs *dvfs = platform_get_drvdata(pdev);
|
||||
+ unsigned long freq;
|
||||
+ int load_lvl;
|
||||
+
|
||||
+ platform_device_unregister(pdev);
|
||||
+
|
||||
+ armada37xx_cpufreq_disable_dvfs(armada37xx_cpufreq_state->regmap);
|
||||
+
|
||||
+ for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
|
||||
+ freq = dvfs->cpu_freq_max / dvfs->divider[load_lvl];
|
||||
+ dev_pm_opp_remove(armada37xx_cpufreq_state->cpu_dev, freq);
|
||||
+ }
|
||||
+
|
||||
+ kfree(armada37xx_cpufreq_state);
|
||||
+}
|
||||
+module_exit(armada37xx_cpufreq_driver_exit);
|
||||
+
|
||||
static const struct of_device_id __maybe_unused armada37xx_cpufreq_of_match[] = {
|
||||
{ .compatible = "marvell,armada-3700-nb-pm" },
|
||||
{ },
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
diff --git a/drivers/net/wireless/rtl8811cu/include/rtw_security.h b/drivers/net/wireless/rtl8811cu/include/rtw_security.h
|
||||
index ac8432e..5f74fb7 100755
|
||||
--- a/drivers/net/wireless/rtl8811cu/include/rtw_security.h
|
||||
+++ b/drivers/net/wireless/rtl8811cu/include/rtw_security.h
|
||||
@@ -249,7 +249,7 @@ struct security_priv {
|
||||
#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE
|
||||
#endif
|
||||
|
||||
-struct sha256_state {
|
||||
+struct rtl_sha256_state {
|
||||
u64 length;
|
||||
u32 state[8], curlen;
|
||||
u8 buf[64];
|
||||
diff --git a/drivers/net/wireless/rtl8811cu/core/rtw_security.c b/drivers/net/wireless/rtl8811cu/core/rtw_security.c
|
||||
index b537a26..f8c42f4 100755
|
||||
--- a/drivers/net/wireless/rtl8811cu/core/rtw_security.c
|
||||
+++ b/drivers/net/wireless/rtl8811cu/core/rtw_security.c
|
||||
@@ -2133,7 +2133,7 @@ BIP_exit:
|
||||
#ifndef PLATFORM_FREEBSD
|
||||
#if defined(CONFIG_TDLS)
|
||||
/* compress 512-bits */
|
||||
-static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
+static int sha256_compress(struct rtl_sha256_state *md, unsigned char *buf)
|
||||
{
|
||||
u32 S[8], W[64], t0, t1;
|
||||
u32 t;
|
||||
@@ -2181,7 +2181,7 @@ static int sha256_compress(struct sha256_state *md, unsigned char *buf)
|
||||
}
|
||||
|
||||
/* Initialize the hash state */
|
||||
-static void sha256_init(struct sha256_state *md)
|
||||
+static void sha256_init(struct rtl_sha256_state *md)
|
||||
{
|
||||
md->curlen = 0;
|
||||
md->length = 0;
|
||||
@@ -2202,7 +2202,7 @@ static void sha256_init(struct sha256_state *md)
|
||||
@param inlen The length of the data (octets)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
+static int sha256_process(struct rtl_sha256_state *md, unsigned char *in,
|
||||
unsigned long inlen)
|
||||
{
|
||||
unsigned long n;
|
||||
@@ -2243,7 +2243,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in,
|
||||
@param out [out] The destination of the hash (32 bytes)
|
||||
@return CRYPT_OK if successful
|
||||
*/
|
||||
-static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
+static int sha256_done(struct rtl_sha256_state *md, unsigned char *out)
|
||||
{
|
||||
int i;
|
||||
|
||||
@@ -2293,7 +2293,7 @@ static int sha256_done(struct sha256_state *md, unsigned char *out)
|
||||
static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,
|
||||
u8 *mac)
|
||||
{
|
||||
- struct sha256_state ctx;
|
||||
+ struct rtl_sha256_state ctx;
|
||||
size_t i;
|
||||
|
||||
sha256_init(&ctx);
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
From a254e56473755fc56ec53136e9f217d4863e1cad Mon Sep 17 00:00:00 2001
|
||||
From: memeka <mihailescu2m@gmail.com>
|
||||
Date: Mon, 21 Oct 2019 10:58:47 +1030
|
||||
Subject: [PATCH 01/24] MEMEKA: ARM: dma-mapping: increase DMA coherent pool
|
||||
size to 2M
|
||||
|
||||
---
|
||||
arch/arm/mm/dma-mapping.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
|
||||
index 8a8949174b1c..80d4e66039ff 100644
|
||||
--- a/arch/arm/mm/dma-mapping.c
|
||||
+++ b/arch/arm/mm/dma-mapping.c
|
||||
@@ -314,7 +314,7 @@ static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
|
||||
pgprot_t prot, struct page **ret_page,
|
||||
const void *caller, bool want_vaddr);
|
||||
|
||||
-#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
|
||||
+#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_2M
|
||||
static struct gen_pool *atomic_pool __ro_after_init;
|
||||
|
||||
static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
From 7ed0bff994ecee9bd6306d23ac1dd5d9b98f91bd Mon Sep 17 00:00:00 2001
|
||||
From: OtherCrashOverride <OtherCrashOverride@users.noreply.github.com>
|
||||
Date: Sun, 9 Apr 2017 17:31:25 +0000
|
||||
Subject: [PATCH 02/24] MEMEKA: drm/exynos/mixer: never blend the base layer
|
||||
|
||||
On Exynos there is a solid color plane that is logically below all the other display planes.
|
||||
This causes display artifacts due to alpha. The patch disables blending the base plane with
|
||||
the solid color plane (no alpha).
|
||||
|
||||
Reviewed-by: memeka <mihailescu2m@gmail.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/gpu/drm/exynos/exynos_mixer.c | 33 +++++++++++++++------------
|
||||
1 file changed, 18 insertions(+), 15 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
|
||||
index 21b726baedea..c1a527fa1df8 100644
|
||||
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
|
||||
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
|
||||
@@ -315,23 +315,26 @@ static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
|
||||
u32 val;
|
||||
|
||||
val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
|
||||
- switch (pixel_alpha) {
|
||||
- case DRM_MODE_BLEND_PIXEL_NONE:
|
||||
- break;
|
||||
- case DRM_MODE_BLEND_COVERAGE:
|
||||
- val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
|
||||
- break;
|
||||
- case DRM_MODE_BLEND_PREMULTI:
|
||||
- default:
|
||||
- val |= MXR_GRP_CFG_BLEND_PRE_MUL;
|
||||
- val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
|
||||
- break;
|
||||
- }
|
||||
+ if (win) {
|
||||
+ switch (pixel_alpha) {
|
||||
+ case DRM_MODE_BLEND_PIXEL_NONE:
|
||||
+ break;
|
||||
+ case DRM_MODE_BLEND_COVERAGE:
|
||||
+ val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
|
||||
+ break;
|
||||
+ case DRM_MODE_BLEND_PREMULTI:
|
||||
+ default:
|
||||
+ val |= MXR_GRP_CFG_BLEND_PRE_MUL;
|
||||
+ val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
|
||||
+ break;
|
||||
+ }
|
||||
|
||||
- if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
|
||||
- val |= MXR_GRP_CFG_WIN_BLEND_EN;
|
||||
- val |= win_alpha;
|
||||
+ if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
|
||||
+ val |= MXR_GRP_CFG_WIN_BLEND_EN;
|
||||
+ val |= win_alpha;
|
||||
+ }
|
||||
}
|
||||
+
|
||||
mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win),
|
||||
val, MXR_GRP_CFG_MISC_MASK);
|
||||
}
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
From 3a03fe387971627668b9cafa3db168e3fe0a2206 Mon Sep 17 00:00:00 2001
|
||||
From: memeka <mihailescu2m@gmail.com>
|
||||
Date: Thu, 24 Jan 2019 16:07:24 +1030
|
||||
Subject: [PATCH 03/24] MEMEKA: media: s5p-jpeg: Enable decoding with multiple
|
||||
buffers
|
||||
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/media/platform/s5p-jpeg/jpeg-core.c | 45 ++++++++++++++++-----
|
||||
1 file changed, 35 insertions(+), 10 deletions(-)
|
||||
|
||||
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c b/drivers/media/platform/s5p-jpeg/jpeg-core.c
|
||||
index 86bda3947110..3015a9c350f2 100644
|
||||
--- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
|
||||
+++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
|
||||
@@ -1797,6 +1797,31 @@ static int exynos3250_jpeg_try_crop(struct s5p_jpeg_ctx *ctx,
|
||||
* V4L2 controls
|
||||
*/
|
||||
|
||||
+static int vidioc_decoder_cmd(struct file *file, void *priv,
|
||||
+ struct v4l2_decoder_cmd *cmd)
|
||||
+{
|
||||
+ struct s5p_jpeg_ctx *ctx = fh_to_ctx(priv);
|
||||
+ struct vb2_queue *vq_src = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
|
||||
+ struct vb2_v4l2_buffer *buf;
|
||||
+
|
||||
+ switch (cmd->cmd) {
|
||||
+ case V4L2_DEC_CMD_STOP:
|
||||
+ if (cmd->flags != 0)
|
||||
+ return -EINVAL;
|
||||
+ if (!vb2_is_streaming(vq_src))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ buf = v4l2_m2m_last_src_buf(ctx->fh.m2m_ctx);
|
||||
+ buf->flags |= V4L2_BUF_FLAG_LAST;
|
||||
+
|
||||
+ break;
|
||||
+ default:
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int s5p_jpeg_g_selection(struct file *file, void *priv,
|
||||
struct v4l2_selection *s)
|
||||
{
|
||||
@@ -1831,9 +1856,6 @@ static int s5p_jpeg_g_selection(struct file *file, void *priv,
|
||||
return 0;
|
||||
}
|
||||
|
||||
-/*
|
||||
- * V4L2 controls
|
||||
- */
|
||||
static int s5p_jpeg_s_selection(struct file *file, void *fh,
|
||||
struct v4l2_selection *s)
|
||||
{
|
||||
@@ -2025,6 +2047,8 @@ static const struct v4l2_ioctl_ops s5p_jpeg_ioctl_ops = {
|
||||
.vidioc_streamon = v4l2_m2m_ioctl_streamon,
|
||||
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
|
||||
|
||||
+ .vidioc_decoder_cmd = vidioc_decoder_cmd,
|
||||
+
|
||||
.vidioc_g_selection = s5p_jpeg_g_selection,
|
||||
.vidioc_s_selection = s5p_jpeg_s_selection,
|
||||
|
||||
@@ -2471,13 +2495,6 @@ static int s5p_jpeg_queue_setup(struct vb2_queue *vq,
|
||||
|
||||
size = q_data->size;
|
||||
|
||||
- /*
|
||||
- * header is parsed during decoding and parsed information stored
|
||||
- * in the context so we do not allow another buffer to overwrite it
|
||||
- */
|
||||
- if (ctx->mode == S5P_JPEG_DECODE)
|
||||
- count = 1;
|
||||
-
|
||||
*nbuffers = count;
|
||||
*nplanes = 1;
|
||||
sizes[0] = size;
|
||||
@@ -2588,6 +2605,7 @@ static int s5p_jpeg_start_streaming(struct vb2_queue *q, unsigned int count)
|
||||
static void s5p_jpeg_stop_streaming(struct vb2_queue *q)
|
||||
{
|
||||
struct s5p_jpeg_ctx *ctx = vb2_get_drv_priv(q);
|
||||
+ struct vb2_v4l2_buffer *buf;
|
||||
|
||||
/*
|
||||
* STREAMOFF is an acknowledgment for resolution change event.
|
||||
@@ -2600,6 +2618,11 @@ static void s5p_jpeg_stop_streaming(struct vb2_queue *q)
|
||||
ctx->state = JPEGCTX_RUNNING;
|
||||
}
|
||||
|
||||
+ while ((buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx)))
|
||||
+ v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR);
|
||||
+ while ((buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx)))
|
||||
+ v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR);
|
||||
+
|
||||
pm_runtime_put(ctx->jpeg->dev);
|
||||
}
|
||||
|
||||
@@ -2839,6 +2862,8 @@ static irqreturn_t exynos3250_jpeg_irq(int irq, void *dev_id)
|
||||
v4l2_m2m_buf_done(src_buf, state);
|
||||
if (curr_ctx->mode == S5P_JPEG_ENCODE)
|
||||
vb2_set_plane_payload(&dst_buf->vb2_buf, 0, payload_size);
|
||||
+ if (src_buf->flags & V4L2_BUF_FLAG_LAST)
|
||||
+ dst_buf->flags |= V4L2_BUF_FLAG_LAST;
|
||||
v4l2_m2m_buf_done(dst_buf, state);
|
||||
|
||||
curr_ctx->subsampling =
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
From e833028fc7a38ee2fac724a3bf267131926a62de Mon Sep 17 00:00:00 2001
|
||||
From: memeka <mihailescu2m@gmail.com>
|
||||
Date: Tue, 10 Jul 2018 11:24:56 +0930
|
||||
Subject: [PATCH 04/24] MEMEKA: media: exynos-gsc: fix v4l2 SELECTION api
|
||||
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/media/platform/exynos-gsc/gsc-core.h | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/media/platform/exynos-gsc/gsc-core.h b/drivers/media/platform/exynos-gsc/gsc-core.h
|
||||
index 8e5a9acb78aa..235d687614f0 100644
|
||||
--- a/drivers/media/platform/exynos-gsc/gsc-core.h
|
||||
+++ b/drivers/media/platform/exynos-gsc/gsc-core.h
|
||||
@@ -474,9 +474,9 @@ static inline struct gsc_frame *ctx_get_frame(struct gsc_ctx *ctx,
|
||||
{
|
||||
struct gsc_frame *frame;
|
||||
|
||||
- if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
|
||||
+ if (V4L2_BUF_TYPE_VIDEO_OUTPUT == type || V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
|
||||
frame = &ctx->s_frame;
|
||||
- } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
|
||||
+ } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == type || V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
|
||||
frame = &ctx->d_frame;
|
||||
} else {
|
||||
pr_err("Wrong buffer/video queue type (%d)", type);
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
From 0a554c41738980359eb40c11a754839e7e2686ff Mon Sep 17 00:00:00 2001
|
||||
From: Thierry Escande <thierry.escande@collabora.com>
|
||||
Date: Wed, 26 Oct 2016 10:52:05 +0200
|
||||
Subject: [PATCH 05/24] MEMEKA: videobuf2-dc: Move vb2_dc_get_base_sgt() above
|
||||
mmap callbacks
|
||||
|
||||
This patch moves vb2_dc_get_base_sgt() function above mmap buffers
|
||||
callbacks, particularly vb2_dc_alloc() and vb2_dc_mmap() from where it
|
||||
will be called for cacheable MMAP support introduced in the next patch.
|
||||
|
||||
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
.../common/videobuf2/videobuf2-dma-contig.c | 44 +++++++++----------
|
||||
1 file changed, 22 insertions(+), 22 deletions(-)
|
||||
|
||||
diff --git a/drivers/media/common/videobuf2/videobuf2-dma-contig.c b/drivers/media/common/videobuf2/videobuf2-dma-contig.c
|
||||
index d3a3ee5b597b..1150e83c9c8d 100644
|
||||
--- a/drivers/media/common/videobuf2/videobuf2-dma-contig.c
|
||||
+++ b/drivers/media/common/videobuf2/videobuf2-dma-contig.c
|
||||
@@ -62,6 +62,28 @@ static unsigned long vb2_dc_get_contiguous_size(struct sg_table *sgt)
|
||||
return size;
|
||||
}
|
||||
|
||||
+static struct sg_table *vb2_dc_get_base_sgt(struct vb2_dc_buf *buf)
|
||||
+{
|
||||
+ int ret;
|
||||
+ struct sg_table *sgt;
|
||||
+
|
||||
+ sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
|
||||
+ if (!sgt) {
|
||||
+ dev_err(buf->dev, "failed to alloc sg table\n");
|
||||
+ return NULL;
|
||||
+ }
|
||||
+
|
||||
+ ret = dma_get_sgtable_attrs(buf->dev, sgt, buf->cookie, buf->dma_addr,
|
||||
+ buf->size, buf->attrs);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(buf->dev, "failed to get scatterlist from DMA API\n");
|
||||
+ kfree(sgt);
|
||||
+ return NULL;
|
||||
+ }
|
||||
+
|
||||
+ return sgt;
|
||||
+}
|
||||
+
|
||||
/*********************************************/
|
||||
/* callbacks for all buffers */
|
||||
/*********************************************/
|
||||
@@ -358,28 +380,6 @@ static const struct dma_buf_ops vb2_dc_dmabuf_ops = {
|
||||
.release = vb2_dc_dmabuf_ops_release,
|
||||
};
|
||||
|
||||
-static struct sg_table *vb2_dc_get_base_sgt(struct vb2_dc_buf *buf)
|
||||
-{
|
||||
- int ret;
|
||||
- struct sg_table *sgt;
|
||||
-
|
||||
- sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
|
||||
- if (!sgt) {
|
||||
- dev_err(buf->dev, "failed to alloc sg table\n");
|
||||
- return NULL;
|
||||
- }
|
||||
-
|
||||
- ret = dma_get_sgtable_attrs(buf->dev, sgt, buf->cookie, buf->dma_addr,
|
||||
- buf->size, buf->attrs);
|
||||
- if (ret < 0) {
|
||||
- dev_err(buf->dev, "failed to get scatterlist from DMA API\n");
|
||||
- kfree(sgt);
|
||||
- return NULL;
|
||||
- }
|
||||
-
|
||||
- return sgt;
|
||||
-}
|
||||
-
|
||||
static struct dma_buf *vb2_dc_get_dmabuf(void *buf_priv, unsigned long flags)
|
||||
{
|
||||
struct vb2_dc_buf *buf = buf_priv;
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
From 89640ed25401f53b2d144a5d1bd762e98a4d1fe3 Mon Sep 17 00:00:00 2001
|
||||
From: Heng-Ruey Hsu <henryhsu@chromium.org>
|
||||
Date: Wed, 26 Oct 2016 10:52:06 +0200
|
||||
Subject: [PATCH 06/24] MEMEKA: videobuf2-dc: Support cacheable MMAP
|
||||
|
||||
DMA allocations for MMAP type are uncached by default. But for
|
||||
some cases, CPU has to access the buffers. ie: memcpy for format
|
||||
converter. Supporting cacheable MMAP improves huge performance.
|
||||
|
||||
This patch enables cacheable memory for DMA coherent allocator in mmap
|
||||
buffer allocation if non-consistent DMA attribute is set and kernel
|
||||
mapping is present. Even if userspace doesn't mmap the buffer, sync
|
||||
still should be happening if kernel mapping is present.
|
||||
If not done in allocation, it is enabled when memory is mapped from
|
||||
userspace (if non-consistent DMA attribute is set).
|
||||
|
||||
Signed-off-by: Heng-Ruey Hsu <henryhsu@chromium.org>
|
||||
Tested-by: Heng-ruey Hsu <henryhsu@chromium.org>
|
||||
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
|
||||
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
.../common/videobuf2/videobuf2-dma-contig.c | 16 ++++++++++++++++
|
||||
1 file changed, 16 insertions(+)
|
||||
|
||||
diff --git a/drivers/media/common/videobuf2/videobuf2-dma-contig.c b/drivers/media/common/videobuf2/videobuf2-dma-contig.c
|
||||
index 1150e83c9c8d..8c868c6309b6 100644
|
||||
--- a/drivers/media/common/videobuf2/videobuf2-dma-contig.c
|
||||
+++ b/drivers/media/common/videobuf2/videobuf2-dma-contig.c
|
||||
@@ -152,6 +152,10 @@ static void vb2_dc_put(void *buf_priv)
|
||||
sg_free_table(buf->sgt_base);
|
||||
kfree(buf->sgt_base);
|
||||
}
|
||||
+ if (buf->dma_sgt) {
|
||||
+ sg_free_table(buf->dma_sgt);
|
||||
+ kfree(buf->dma_sgt);
|
||||
+ }
|
||||
dma_free_attrs(buf->dev, buf->size, buf->cookie, buf->dma_addr,
|
||||
buf->attrs);
|
||||
put_device(buf->dev);
|
||||
@@ -193,6 +197,14 @@ static void *vb2_dc_alloc(struct device *dev, unsigned long attrs,
|
||||
buf->handler.put = vb2_dc_put;
|
||||
buf->handler.arg = buf;
|
||||
|
||||
+ /*
|
||||
+ * Enable cache maintenance. Even if userspace doesn't mmap the buffer,
|
||||
+ * sync still should be happening if kernel mapping is present.
|
||||
+ */
|
||||
+ if (!(buf->attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
|
||||
+ buf->attrs & DMA_ATTR_NON_CONSISTENT)
|
||||
+ buf->dma_sgt = vb2_dc_get_base_sgt(buf);
|
||||
+
|
||||
refcount_set(&buf->refcount, 1);
|
||||
|
||||
return buf;
|
||||
@@ -222,6 +234,10 @@ static int vb2_dc_mmap(void *buf_priv, struct vm_area_struct *vma)
|
||||
|
||||
vma->vm_ops->open(vma);
|
||||
|
||||
+ /* Enable cache maintenance if not enabled in allocation. */
|
||||
+ if (!buf->dma_sgt && buf->attrs & DMA_ATTR_NON_CONSISTENT)
|
||||
+ buf->dma_sgt = vb2_dc_get_base_sgt(buf);
|
||||
+
|
||||
pr_debug("%s: mapped dma addr 0x%08lx at 0x%08lx, size %ld\n",
|
||||
__func__, (unsigned long)buf->dma_addr, vma->vm_start,
|
||||
buf->size);
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
From db0c55db061c8e97c909158a7c309563e326f7eb Mon Sep 17 00:00:00 2001
|
||||
From: memeka <mihailescu2m@gmail.com>
|
||||
Date: Mon, 30 Oct 2017 09:31:09 +1030
|
||||
Subject: [PATCH 08/24] MEMEKA: media: s5p-mfc: use cacheable DMA buffers to
|
||||
improve performance
|
||||
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/media/platform/s5p-mfc/s5p_mfc.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
|
||||
index 5c2a23b953a4..20d7dd992f6f 100644
|
||||
--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
|
||||
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
|
||||
@@ -858,7 +858,7 @@ static int s5p_mfc_open(struct file *file)
|
||||
* We'll do mostly sequential access, so sacrifice TLB efficiency for
|
||||
* faster allocation.
|
||||
*/
|
||||
- q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
|
||||
+ q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | DMA_ATTR_NON_CONSISTENT | DMA_ATTR_NO_KERNEL_MAPPING;
|
||||
q->mem_ops = &vb2_dma_contig_memops;
|
||||
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
|
||||
ret = vb2_queue_init(q);
|
||||
@@ -893,7 +893,7 @@ static int s5p_mfc_open(struct file *file)
|
||||
* We'll do mostly sequential access, so sacrifice TLB efficiency for
|
||||
* faster allocation.
|
||||
*/
|
||||
- q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
|
||||
+ q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | DMA_ATTR_NON_CONSISTENT | DMA_ATTR_NO_KERNEL_MAPPING;
|
||||
q->mem_ops = &vb2_dma_contig_memops;
|
||||
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
|
||||
ret = vb2_queue_init(q);
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
From 5ed1a262d49857d2380887f130d37f4094da58a9 Mon Sep 17 00:00:00 2001
|
||||
From: memeka <mihailescu2m@gmail.com>
|
||||
Date: Tue, 10 Jul 2018 22:01:38 +0930
|
||||
Subject: [PATCH 09/24] MEMEKA: media: s5p-mfc: copy timestamp and timecode in
|
||||
encoder output
|
||||
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/media/platform/s5p-mfc/s5p_mfc_enc.c | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
|
||||
index 912fe0c5ab18..d48e7b57d96a 100644
|
||||
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
|
||||
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
|
||||
@@ -1208,6 +1208,7 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)
|
||||
{
|
||||
struct s5p_mfc_dev *dev = ctx->dev;
|
||||
struct s5p_mfc_buf *mb_entry;
|
||||
+ struct s5p_mfc_buf *dst_buf;
|
||||
unsigned long enc_y_addr = 0, enc_c_addr = 0;
|
||||
unsigned long mb_y_addr, mb_c_addr;
|
||||
int slice_type;
|
||||
@@ -1227,8 +1228,12 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)
|
||||
&mb_entry->b->vb2_buf, 0);
|
||||
mb_c_addr = vb2_dma_contig_plane_dma_addr(
|
||||
&mb_entry->b->vb2_buf, 1);
|
||||
+ dst_buf = list_entry(ctx->dst_queue.next,
|
||||
+ struct s5p_mfc_buf, list);
|
||||
if ((enc_y_addr == mb_y_addr) &&
|
||||
(enc_c_addr == mb_c_addr)) {
|
||||
+ dst_buf->b->timecode = mb_entry->b->timecode;
|
||||
+ dst_buf->b->vb2_buf.timestamp = mb_entry->b->vb2_buf.timestamp;
|
||||
list_del(&mb_entry->list);
|
||||
ctx->src_queue_cnt--;
|
||||
vb2_buffer_done(&mb_entry->b->vb2_buf,
|
||||
@@ -1241,8 +1246,12 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)
|
||||
&mb_entry->b->vb2_buf, 0);
|
||||
mb_c_addr = vb2_dma_contig_plane_dma_addr(
|
||||
&mb_entry->b->vb2_buf, 1);
|
||||
+ dst_buf = list_entry(ctx->dst_queue.next,
|
||||
+ struct s5p_mfc_buf, list);
|
||||
if ((enc_y_addr == mb_y_addr) &&
|
||||
(enc_c_addr == mb_c_addr)) {
|
||||
+ dst_buf->b->timecode = mb_entry->b->timecode;
|
||||
+ dst_buf->b->vb2_buf.timestamp = mb_entry->b->vb2_buf.timestamp;
|
||||
list_del(&mb_entry->list);
|
||||
ctx->ref_queue_cnt--;
|
||||
vb2_buffer_done(&mb_entry->b->vb2_buf,
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
From cc2f0760641d5e11c4af1e5517c34dd604470b27 Mon Sep 17 00:00:00 2001
|
||||
From: OtherCrashOverride <OtherCrashOverride@users.noreply.github.com>
|
||||
Date: Fri, 19 May 2017 12:59:51 +0000
|
||||
Subject: [PATCH 10/24] MEMEKA: media: s5p-mfc: stop streaming before releasing
|
||||
queues
|
||||
|
||||
If streaming is active when the MFC device is closed, it will generate an IOMMU page-fault.
|
||||
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/media/platform/s5p-mfc/s5p_mfc.c | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
|
||||
index 20d7dd992f6f..e760e244083f 100644
|
||||
--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
|
||||
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
|
||||
@@ -941,6 +941,11 @@ static int s5p_mfc_release(struct file *file)
|
||||
mfc_debug_enter();
|
||||
if (dev)
|
||||
mutex_lock(&dev->mfc_mutex);
|
||||
+
|
||||
+ /* stop streaming */
|
||||
+ vb2_streamoff(&ctx->vq_src, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
|
||||
+ vb2_streamoff(&ctx->vq_dst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
|
||||
+
|
||||
vb2_queue_release(&ctx->vq_src);
|
||||
vb2_queue_release(&ctx->vq_dst);
|
||||
if (dev) {
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
From e3e981ecd038c1bb43a9902d90eb46019c816588 Mon Sep 17 00:00:00 2001
|
||||
From: Marek Szyprowski <m.szyprowski@samsung.com>
|
||||
Date: Thu, 21 Nov 2019 11:11:45 +0100
|
||||
Subject: [PATCH 12/24] MEMEKA: clk: samsung: exynos5420: Keep top G3D clocks
|
||||
enabled
|
||||
|
||||
All top clocks on G3D path has to be enabled all the time to allow proper
|
||||
G3D power domain operation. This is achieved by adding CRITICAL flag to
|
||||
"mout_sw_aclk_g3d" clock, what keeps this clock and all its parents
|
||||
enabled.
|
||||
|
||||
This fixes following imprecise abort issue observed on Odroid XU3/XU4
|
||||
after enabling Panfrost driver by commit 1a5a85c56402 "ARM: dts: exynos:
|
||||
Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4"):
|
||||
|
||||
panfrost 11800000.gpu: clock rate = 400000000
|
||||
panfrost 11800000.gpu: failed to get regulator: -517
|
||||
panfrost 11800000.gpu: regulator init failed -517
|
||||
Power domain G3D disable failed
|
||||
...
|
||||
panfrost 11800000.gpu: clock rate = 400000000
|
||||
8<--- cut here ---
|
||||
Unhandled fault: imprecise external abort (0x1406) at 0x00000000
|
||||
pgd = (ptrval)
|
||||
[00000000] *pgd=00000000
|
||||
Internal error: : 1406 [#1] PREEMPT SMP ARM
|
||||
Modules linked in:
|
||||
CPU: 7 PID: 53 Comm: kworker/7:1 Not tainted 5.4.0-rc8-next-20191119-00032-g56f1001191a6 #6923
|
||||
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
|
||||
Workqueue: events deferred_probe_work_func
|
||||
PC is at panfrost_gpu_soft_reset+0x94/0x110
|
||||
LR is at ___might_sleep+0x128/0x2dc
|
||||
...
|
||||
[<c05c231c>] (panfrost_gpu_soft_reset) from [<c05c2704>] (panfrost_gpu_init+0x10/0x67c)
|
||||
[<c05c2704>] (panfrost_gpu_init) from [<c05c15d0>] (panfrost_device_init+0x158/0x2cc)
|
||||
[<c05c15d0>] (panfrost_device_init) from [<c05c0cb0>] (panfrost_probe+0x80/0x178)
|
||||
[<c05c0cb0>] (panfrost_probe) from [<c05cfaa0>] (platform_drv_probe+0x48/0x9c)
|
||||
[<c05cfaa0>] (platform_drv_probe) from [<c05cd20c>] (really_probe+0x1c4/0x474)
|
||||
[<c05cd20c>] (really_probe) from [<c05cd694>] (driver_probe_device+0x78/0x1bc)
|
||||
[<c05cd694>] (driver_probe_device) from [<c05cb374>] (bus_for_each_drv+0x74/0xb8)
|
||||
[<c05cb374>] (bus_for_each_drv) from [<c05ccfa8>] (__device_attach+0xd4/0x16c)
|
||||
[<c05ccfa8>] (__device_attach) from [<c05cc110>] (bus_probe_device+0x88/0x90)
|
||||
[<c05cc110>] (bus_probe_device) from [<c05cc634>] (deferred_probe_work_func+0x4c/0xd0)
|
||||
[<c05cc634>] (deferred_probe_work_func) from [<c0149df0>] (process_one_work+0x300/0x864)
|
||||
[<c0149df0>] (process_one_work) from [<c014a3ac>] (worker_thread+0x58/0x5a0)
|
||||
[<c014a3ac>] (worker_thread) from [<c0151174>] (kthread+0x12c/0x160)
|
||||
[<c0151174>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20)
|
||||
Exception stack(0xee03dfb0 to 0xee03dff8)
|
||||
...
|
||||
Code: e594300c e5933020 e3130c01 1a00000f (ebefff50).
|
||||
---[ end trace badde2b74a65a540 ]---
|
||||
|
||||
In the above case, the Panfrost driver disables G3D clocks after failure
|
||||
of getting the needed regulator and return with -EPROVE_DEFER code. This
|
||||
causes G3D power domain disable failure and then, during second probe
|
||||
an imprecise abort is triggered due to undefined power domain state.
|
||||
|
||||
Fixes: 45f10dabb56b ("clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path")
|
||||
Fixes: c9f7567aff31 ("clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU")
|
||||
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
|
||||
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
|
||||
|
||||
Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/clk/samsung/clk-exynos5420.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
|
||||
index c9e5a1fb6653..bba0fe205c4e 100644
|
||||
--- a/drivers/clk/samsung/clk-exynos5420.c
|
||||
+++ b/drivers/clk/samsung/clk-exynos5420.c
|
||||
@@ -714,7 +714,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
|
||||
MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
|
||||
SRC_TOP12, 12, 1),
|
||||
MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
|
||||
- SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
|
||||
+ SRC_TOP12, 16, 1, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
|
||||
MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
|
||||
SRC_TOP12, 20, 1),
|
||||
MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
From 5babc111a40684d30905319f6e6a8688b948f5be Mon Sep 17 00:00:00 2001
|
||||
From: memeka <mihailescu2m@gmail.com>
|
||||
Date: Tue, 10 Jul 2018 22:13:03 +0930
|
||||
Subject: [PATCH 13/24] MEMEKA: thermal: exynos: add support for 8 trip points
|
||||
on Exynos5422 TMU
|
||||
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/thermal/samsung/exynos_tmu.c | 18 ++++++++++++++++--
|
||||
1 file changed, 16 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
|
||||
index e9a90bc23b11..b49df21fa0e7 100644
|
||||
--- a/drivers/thermal/samsung/exynos_tmu.c
|
||||
+++ b/drivers/thermal/samsung/exynos_tmu.c
|
||||
@@ -915,8 +915,6 @@ static int exynos_map_dt_data(struct platform_device *pdev)
|
||||
case SOC_ARCH_EXYNOS4412:
|
||||
case SOC_ARCH_EXYNOS5250:
|
||||
case SOC_ARCH_EXYNOS5260:
|
||||
- case SOC_ARCH_EXYNOS5420:
|
||||
- case SOC_ARCH_EXYNOS5420_TRIMINFO:
|
||||
data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp;
|
||||
data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst;
|
||||
data->tmu_initialize = exynos4412_tmu_initialize;
|
||||
@@ -935,6 +933,22 @@ static int exynos_map_dt_data(struct platform_device *pdev)
|
||||
data->min_efuse_value = 0;
|
||||
data->max_efuse_value = 100;
|
||||
break;
|
||||
+ case SOC_ARCH_EXYNOS5420:
|
||||
+ case SOC_ARCH_EXYNOS5420_TRIMINFO:
|
||||
+ data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp;
|
||||
+ data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst;
|
||||
+ data->tmu_initialize = exynos4412_tmu_initialize;
|
||||
+ data->tmu_control = exynos4210_tmu_control;
|
||||
+ data->tmu_read = exynos4412_tmu_read;
|
||||
+ data->tmu_set_emulation = exynos4412_tmu_set_emulation;
|
||||
+ data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
|
||||
+ data->ntrip = 8;
|
||||
+ data->gain = 8;
|
||||
+ data->reference_voltage = 16;
|
||||
+ data->efuse_value = 55;
|
||||
+ data->min_efuse_value = 16;
|
||||
+ data->max_efuse_value = 76;
|
||||
+ break;
|
||||
case SOC_ARCH_EXYNOS5433:
|
||||
data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp;
|
||||
data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst;
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
From 54322f5f719b57f603f5cb1d92d341b75e4d6ff2 Mon Sep 17 00:00:00 2001
|
||||
From: memeka <mihailescu2m@gmail.com>
|
||||
Date: Tue, 22 Jan 2019 11:55:07 +1030
|
||||
Subject: [PATCH 14/24] MEMEKA: arm: dts: exynos5422: enable Exynos5422 TMU
|
||||
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
index ab27ff8bc3dc..4a4710efb429 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
@@ -1030,22 +1030,27 @@
|
||||
|
||||
&tmu_cpu0 {
|
||||
vtmu-supply = <&ldo7_reg>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&tmu_cpu1 {
|
||||
vtmu-supply = <&ldo7_reg>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&tmu_cpu2 {
|
||||
vtmu-supply = <&ldo7_reg>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&tmu_cpu3 {
|
||||
vtmu-supply = <&ldo7_reg>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&tmu_gpu {
|
||||
vtmu-supply = <&ldo7_reg>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,138 +0,0 @@
|
|||
From 674482a5933e94789105d32872adff0ffce48d01 Mon Sep 17 00:00:00 2001
|
||||
From: Lukasz Luba <l.luba@partner.samsung.com>
|
||||
Date: Wed, 7 Nov 2018 18:09:44 +0100
|
||||
Subject: [PATCH 15/24] MEMEKA: thermal: add irq-mode configuration for trip
|
||||
point
|
||||
|
||||
This patch adds support irq mode in trip point.
|
||||
When that flag is set in DT, there is no need for polling
|
||||
in thermal framework. Crossing the trip point will rise an IRQ.
|
||||
The naming convention for tip point 'type' can be confussing
|
||||
and 'passive' (whic is passive cooling) might be interpretted wrongly.
|
||||
|
||||
This mechanism prevents from missue and adds explicit setting
|
||||
for hardware which support interrupts for pre-configured temperature
|
||||
threshold.
|
||||
|
||||
Cc: Zhang Rui <rui.zhang@intel.com>
|
||||
Cc: Eduardo Valentin <edubezval@gmail.com>
|
||||
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/thermal/of-thermal.c | 17 +++++++++++++++++
|
||||
drivers/thermal/thermal_core.c | 10 ++++++++--
|
||||
include/linux/thermal.h | 5 +++++
|
||||
3 files changed, 30 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c
|
||||
index 874a47d6923f..1549561e28b2 100644
|
||||
--- a/drivers/thermal/of-thermal.c
|
||||
+++ b/drivers/thermal/of-thermal.c
|
||||
@@ -315,6 +315,20 @@ static int of_thermal_get_trip_type(struct thermal_zone_device *tz, int trip,
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int
|
||||
+of_thermal_get_trip_irq_mode(struct thermal_zone_device *tz, int trip,
|
||||
+ bool *mode)
|
||||
+{
|
||||
+ struct __thermal_zone *data = tz->devdata;
|
||||
+
|
||||
+ if (trip >= data->ntrips || trip < 0)
|
||||
+ return -EDOM;
|
||||
+
|
||||
+ *mode = data->trips[trip].irq_mode;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int of_thermal_get_trip_temp(struct thermal_zone_device *tz, int trip,
|
||||
int *temp)
|
||||
{
|
||||
@@ -397,6 +411,7 @@ static struct thermal_zone_device_ops of_thermal_ops = {
|
||||
.set_mode = of_thermal_set_mode,
|
||||
|
||||
.get_trip_type = of_thermal_get_trip_type,
|
||||
+ .get_trip_irq_mode = of_thermal_get_trip_irq_mode,
|
||||
.get_trip_temp = of_thermal_get_trip_temp,
|
||||
.set_trip_temp = of_thermal_set_trip_temp,
|
||||
.get_trip_hyst = of_thermal_get_trip_hyst,
|
||||
@@ -860,6 +875,8 @@ static int thermal_of_populate_trip(struct device_node *np,
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ trip->irq_mode = of_property_read_bool(np, "irq-mode");
|
||||
+
|
||||
/* Required for cooling map matching */
|
||||
trip->np = np;
|
||||
of_node_get(np);
|
||||
diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c
|
||||
index 9a321dc548c8..ef23a33d34b6 100644
|
||||
--- a/drivers/thermal/thermal_core.c
|
||||
+++ b/drivers/thermal/thermal_core.c
|
||||
@@ -410,6 +410,7 @@ static void handle_critical_trips(struct thermal_zone_device *tz,
|
||||
static void handle_thermal_trip(struct thermal_zone_device *tz, int trip)
|
||||
{
|
||||
enum thermal_trip_type type;
|
||||
+ bool irq_mode = false;
|
||||
|
||||
/* Ignore disabled trip points */
|
||||
if (test_bit(trip, &tz->trips_disabled))
|
||||
@@ -423,9 +424,14 @@ static void handle_thermal_trip(struct thermal_zone_device *tz, int trip)
|
||||
handle_non_critical_trips(tz, trip);
|
||||
/*
|
||||
* Alright, we handled this trip successfully.
|
||||
- * So, start monitoring again.
|
||||
+ * So, start monitoring in polling mode if
|
||||
+ * trip is not using irq HW support.
|
||||
*/
|
||||
- monitor_thermal_zone(tz);
|
||||
+ if (tz->ops->get_trip_irq_mode)
|
||||
+ tz->ops->get_trip_irq_mode(tz, trip, &irq_mode);
|
||||
+
|
||||
+ if (!irq_mode)
|
||||
+ monitor_thermal_zone(tz);
|
||||
}
|
||||
|
||||
static void update_temperature(struct thermal_zone_device *tz)
|
||||
diff --git a/include/linux/thermal.h b/include/linux/thermal.h
|
||||
index c91b1e344d56..c4ce2b875b73 100644
|
||||
--- a/include/linux/thermal.h
|
||||
+++ b/include/linux/thermal.h
|
||||
@@ -92,6 +92,7 @@ struct thermal_zone_device_ops {
|
||||
enum thermal_device_mode);
|
||||
int (*get_trip_type) (struct thermal_zone_device *, int,
|
||||
enum thermal_trip_type *);
|
||||
+ int (*get_trip_irq_mode) (struct thermal_zone_device *, int, bool *);
|
||||
int (*get_trip_temp) (struct thermal_zone_device *, int, int *);
|
||||
int (*set_trip_temp) (struct thermal_zone_device *, int, int);
|
||||
int (*get_trip_hyst) (struct thermal_zone_device *, int, int *);
|
||||
@@ -185,6 +186,7 @@ struct thermal_zone_device {
|
||||
struct thermal_attr *trip_temp_attrs;
|
||||
struct thermal_attr *trip_type_attrs;
|
||||
struct thermal_attr *trip_hyst_attrs;
|
||||
+ struct thermal_attr *trip_irq_mode_attrs;
|
||||
void *devdata;
|
||||
int trips;
|
||||
unsigned long trips_disabled; /* bitmap for disabled trips */
|
||||
@@ -353,6 +355,8 @@ struct thermal_zone_of_device_ops {
|
||||
* @temperature: temperature value in miliCelsius
|
||||
* @hysteresis: relative hysteresis in miliCelsius
|
||||
* @type: trip point type
|
||||
+ * @irq_mode: to not use polling in framework set support of HW irq (which will
|
||||
+ * be triggered when temperature reaches this level).
|
||||
*/
|
||||
|
||||
struct thermal_trip {
|
||||
@@ -360,6 +364,7 @@ struct thermal_trip {
|
||||
int temperature;
|
||||
int hysteresis;
|
||||
enum thermal_trip_type type;
|
||||
+ bool irq_mode;
|
||||
};
|
||||
|
||||
/* Function declarations */
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,130 +0,0 @@
|
|||
From 794e70326e4735707ee426d9d45f2c906a68a58d Mon Sep 17 00:00:00 2001
|
||||
From: Lukasz Luba <l.luba@partner.samsung.com>
|
||||
Date: Wed, 7 Nov 2018 18:09:45 +0100
|
||||
Subject: [PATCH 16/24] MEMEKA: thermal: add new sysfs file for irq-mode
|
||||
|
||||
Patch adds show functions for irq-mode feature.
|
||||
It allocates new attributes and extends the old list.
|
||||
|
||||
Cc: Zhang Rui <rui.zhang@intel.com>
|
||||
Cc: Eduardo Valentin <edubezval@gmail.com>
|
||||
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/thermal/thermal_sysfs.c | 53 +++++++++++++++++++++++++++++++--
|
||||
1 file changed, 51 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/thermal/thermal_sysfs.c b/drivers/thermal/thermal_sysfs.c
|
||||
index aa99edb4dff7..e3ede8af79cc 100644
|
||||
--- a/drivers/thermal/thermal_sysfs.c
|
||||
+++ b/drivers/thermal/thermal_sysfs.c
|
||||
@@ -21,6 +21,8 @@
|
||||
|
||||
#include "thermal_core.h"
|
||||
|
||||
+#define TRIP_ATTR_NUM 4
|
||||
+
|
||||
/* sys I/F for thermal zone */
|
||||
|
||||
static ssize_t
|
||||
@@ -166,6 +168,28 @@ trip_point_temp_show(struct device *dev, struct device_attribute *attr,
|
||||
return sprintf(buf, "%d\n", temperature);
|
||||
}
|
||||
|
||||
+static ssize_t
|
||||
+trip_point_irq_mode_show(struct device *dev, struct device_attribute *attr,
|
||||
+ char *buf)
|
||||
+{
|
||||
+ struct thermal_zone_device *tz = to_thermal_zone(dev);
|
||||
+ int trip, ret;
|
||||
+ bool mode;
|
||||
+
|
||||
+ if (!tz->ops->get_trip_irq_mode)
|
||||
+ return -EPERM;
|
||||
+
|
||||
+ if (sscanf(attr->attr.name, "trip_point_%d_irq", &trip) != 1)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ ret = tz->ops->get_trip_irq_mode(tz, trip, &mode);
|
||||
+
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ return sprintf(buf, "%d\n", mode);
|
||||
+}
|
||||
+
|
||||
static ssize_t
|
||||
trip_point_hyst_store(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
@@ -520,10 +544,19 @@ static int create_trip_attrs(struct thermal_zone_device *tz, int mask)
|
||||
if (!tz->trip_type_attrs)
|
||||
return -ENOMEM;
|
||||
|
||||
+ tz->trip_irq_mode_attrs = kcalloc(tz->trips,
|
||||
+ sizeof(*tz->trip_irq_mode_attrs),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!tz->trip_irq_mode_attrs) {
|
||||
+ kfree(tz->trip_type_attrs);
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
tz->trip_temp_attrs = kcalloc(tz->trips, sizeof(*tz->trip_temp_attrs),
|
||||
GFP_KERNEL);
|
||||
if (!tz->trip_temp_attrs) {
|
||||
kfree(tz->trip_type_attrs);
|
||||
+ kfree(tz->trip_irq_mode_attrs);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
@@ -533,14 +566,17 @@ static int create_trip_attrs(struct thermal_zone_device *tz, int mask)
|
||||
GFP_KERNEL);
|
||||
if (!tz->trip_hyst_attrs) {
|
||||
kfree(tz->trip_type_attrs);
|
||||
+ kfree(tz->trip_irq_mode_attrs);
|
||||
kfree(tz->trip_temp_attrs);
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
|
||||
- attrs = kcalloc(tz->trips * 3 + 1, sizeof(*attrs), GFP_KERNEL);
|
||||
+ attrs = kcalloc(tz->trips * TRIP_ATTR_NUM + 1, sizeof(*attrs),
|
||||
+ GFP_KERNEL);
|
||||
if (!attrs) {
|
||||
kfree(tz->trip_type_attrs);
|
||||
+ kfree(tz->trip_irq_mode_attrs);
|
||||
kfree(tz->trip_temp_attrs);
|
||||
if (tz->ops->get_trip_hyst)
|
||||
kfree(tz->trip_hyst_attrs);
|
||||
@@ -559,6 +595,19 @@ static int create_trip_attrs(struct thermal_zone_device *tz, int mask)
|
||||
tz->trip_type_attrs[indx].attr.show = trip_point_type_show;
|
||||
attrs[indx] = &tz->trip_type_attrs[indx].attr.attr;
|
||||
|
||||
+ /* create trip irq_mode attribute */
|
||||
+ snprintf(tz->trip_irq_mode_attrs[indx].name,
|
||||
+ THERMAL_NAME_LENGTH, "trip_point_%d_irq", indx);
|
||||
+
|
||||
+ sysfs_attr_init(&tz->trip_irq_mode_attrs[indx].attr.attr);
|
||||
+ tz->trip_irq_mode_attrs[indx].attr.attr.name =
|
||||
+ tz->trip_irq_mode_attrs[indx].name;
|
||||
+ tz->trip_irq_mode_attrs[indx].attr.attr.mode = S_IRUGO;
|
||||
+ tz->trip_irq_mode_attrs[indx].attr.show =
|
||||
+ trip_point_irq_mode_show;
|
||||
+ attrs[indx + tz->trips * 3] =
|
||||
+ &tz->trip_irq_mode_attrs[indx].attr.attr;
|
||||
+
|
||||
/* create trip temp attribute */
|
||||
snprintf(tz->trip_temp_attrs[indx].name, THERMAL_NAME_LENGTH,
|
||||
"trip_point_%d_temp", indx);
|
||||
@@ -595,7 +644,7 @@ static int create_trip_attrs(struct thermal_zone_device *tz, int mask)
|
||||
attrs[indx + tz->trips * 2] =
|
||||
&tz->trip_hyst_attrs[indx].attr.attr;
|
||||
}
|
||||
- attrs[tz->trips * 3] = NULL;
|
||||
+ attrs[tz->trips * TRIP_ATTR_NUM] = NULL;
|
||||
|
||||
tz->trips_attribute_group.attrs = attrs;
|
||||
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
From 636a335a2705f8da4c73da01f63c696f16f5f8c2 Mon Sep 17 00:00:00 2001
|
||||
From: "k.konieczny@partner.samsung.com" <k.konieczny@partner.samsung.com>
|
||||
Date: Tue, 8 Oct 2019 15:49:23 +0200
|
||||
Subject: [PATCH 17/24] MEMEKA: devfreq: exynos-bus: workaround
|
||||
dev_pm_opp_set_rate() errors on Exynos5422/5800 SoCs
|
||||
|
||||
Commit 4294a779bd8d ("PM / devfreq: exynos-bus: Convert to use
|
||||
dev_pm_opp_set_rate()") introduced errors:
|
||||
exynos-bus: new bus device registered: soc:bus_wcore ( 84000 KHz ~ 400000 KHz)
|
||||
exynos-bus: new bus device registered: soc:bus_noc ( 67000 KHz ~ 100000 KHz)
|
||||
exynos-bus: new bus device registered: soc:bus_fsys_apb (100000 KHz ~ 200000 KHz)
|
||||
...
|
||||
exynos-bus soc:bus_wcore: dev_pm_opp_set_rate: failed to find current OPP for freq 532000000 (-34)
|
||||
exynos-bus soc:bus_noc: dev_pm_opp_set_rate: failed to find current OPP for freq 111000000 (-34)
|
||||
exynos-bus soc:bus_fsys_apb: dev_pm_opp_set_rate: failed to find current OPP for freq 222000000 (-34)
|
||||
|
||||
They are caused by incorrect PLL assigned to clock source, which results
|
||||
in clock rate outside of OPP range. Add workaround for this in
|
||||
exynos_bus_parse_of() by adjusting clock rate to those present in OPP.
|
||||
|
||||
Fixes: 4294a779bd8d ("PM / devfreq: exynos-bus: Convert to use dev_pm_opp_set_rate()")
|
||||
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/devfreq/exynos-bus.c | 14 +++++++++++---
|
||||
1 file changed, 11 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/drivers/devfreq/exynos-bus.c b/drivers/devfreq/exynos-bus.c
|
||||
index 8fa8eb541373..5b167eadb21e 100644
|
||||
--- a/drivers/devfreq/exynos-bus.c
|
||||
+++ b/drivers/devfreq/exynos-bus.c
|
||||
@@ -243,7 +243,7 @@ static int exynos_bus_parse_of(struct device_node *np,
|
||||
{
|
||||
struct device *dev = bus->dev;
|
||||
struct dev_pm_opp *opp;
|
||||
- unsigned long rate;
|
||||
+ unsigned long rate, opp_rate;
|
||||
int ret;
|
||||
|
||||
/* Get the clock to provide each bus with source clock */
|
||||
@@ -267,13 +267,21 @@ static int exynos_bus_parse_of(struct device_node *np,
|
||||
}
|
||||
|
||||
rate = clk_get_rate(bus->clk);
|
||||
-
|
||||
- opp = devfreq_recommended_opp(dev, &rate, 0);
|
||||
+ opp_rate = rate;
|
||||
+ opp = devfreq_recommended_opp(dev, &opp_rate, 0);
|
||||
if (IS_ERR(opp)) {
|
||||
dev_err(dev, "failed to find dev_pm_opp\n");
|
||||
ret = PTR_ERR(opp);
|
||||
goto err_opp;
|
||||
}
|
||||
+ /*
|
||||
+ * FIXME: U-boot leaves clock source at incorrect PLL, this results
|
||||
+ * in clock rate outside defined OPP rate. Work around this bug by
|
||||
+ * setting clock rate to recommended one.
|
||||
+ */
|
||||
+ if (rate > opp_rate)
|
||||
+ clk_set_rate(bus->clk, opp_rate);
|
||||
+
|
||||
bus->curr_freq = dev_pm_opp_get_freq(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
From 4e255483d743cd2d268fdb68601aa2a7a25d65c6 Mon Sep 17 00:00:00 2001
|
||||
From: Anand Moon <moon.linux@yahoo.com>
|
||||
Date: Sun, 12 Jul 2015 18:41:20 +0530
|
||||
Subject: [PATCH 18/24] MEMEKA: regulator: s2mps11: call shutdown function to
|
||||
poweroff
|
||||
|
||||
Added .shutdown function to s2mps11 to help poweroff the board successfully.
|
||||
The device driver clears the register to turn off the PMIC.
|
||||
|
||||
s2mps11-pmic: S2MPS11_REG_CTRL1 reg value 16:00000000000000000000000000010000
|
||||
|
||||
Console log.
|
||||
|
||||
* Unmounting temporary filesystems... [ OK ]
|
||||
* Deactivating swap... [ OK ]
|
||||
* Unmounting local filesystems... [ OK ]
|
||||
* Will now halt
|
||||
[ 209.020280] reboot: Power down
|
||||
[ 209.122039] Power down failed, please power off system manually.
|
||||
|
||||
Change-Id: If6ea0dec154b00ceeaaddbac393c67dc35c26279
|
||||
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/regulator/s2mps11.c | 26 ++++++++++++++++++++++++++
|
||||
1 file changed, 26 insertions(+)
|
||||
|
||||
diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c
|
||||
index 23d288278957..b3ee46955986 100644
|
||||
--- a/drivers/regulator/s2mps11.c
|
||||
+++ b/drivers/regulator/s2mps11.c
|
||||
@@ -1243,6 +1243,31 @@ static int s2mps11_pmic_probe(struct platform_device *pdev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static void s2mps11_pmic_shutdown(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
|
||||
+ unsigned int reg_val, ret;
|
||||
+
|
||||
+ ret = regmap_read(iodev->regmap_pmic, S2MPS11_REG_CTRL1, ®_val);
|
||||
+ if (ret < 0) {
|
||||
+ dev_crit(&pdev->dev, "could not read S2MPS11_REG_CTRL1 value\n");
|
||||
+ } else {
|
||||
+ /*
|
||||
+ * s2mps11-pmic: S2MPS11_REG_CTRL1 reg value
|
||||
+ * is 00000000000000000000000000010000
|
||||
+ * clear the S2MPS11_REG_CTRL1 0x10 value to shutdown.
|
||||
+ */
|
||||
+ if (reg_val & BIT(4)) {
|
||||
+ ret = regmap_update_bits(iodev->regmap_pmic,
|
||||
+ S2MPS11_REG_CTRL1,
|
||||
+ BIT(4), BIT(0));
|
||||
+ if (ret)
|
||||
+ dev_crit(&pdev->dev,
|
||||
+ "could not write S2MPS11_REG_CTRL1 value\n");
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static const struct platform_device_id s2mps11_pmic_id[] = {
|
||||
{ "s2mps11-regulator", S2MPS11X},
|
||||
{ "s2mps13-regulator", S2MPS13X},
|
||||
@@ -1258,6 +1283,7 @@ static struct platform_driver s2mps11_pmic_driver = {
|
||||
.name = "s2mps11-pmic",
|
||||
},
|
||||
.probe = s2mps11_pmic_probe,
|
||||
+ .shutdown = s2mps11_pmic_shutdown,
|
||||
.id_table = s2mps11_pmic_id,
|
||||
};
|
||||
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,92 +0,0 @@
|
|||
From f2bd0138c14fbc5a985a12240eec0f68170af9f9 Mon Sep 17 00:00:00 2001
|
||||
From: memeka <mihailescu2m@gmail.com>
|
||||
Date: Fri, 18 Jan 2019 14:36:21 +1030
|
||||
Subject: [PATCH 19/24] MEMEKA: regulator: s2mps11: add ethernet power reset in
|
||||
shutdown function
|
||||
|
||||
Ethernet device cannot be detected on warm boot sometimes. This patch is
|
||||
to add the power reset routines for ethernet device using PMIC. Then
|
||||
ethernet device can be reset hardware-wise.
|
||||
|
||||
Change-Id: Iffbe2966da7e4679f63b91ab79241167391792df
|
||||
Signed-off-by: Brian Kim <brian.kim@hardkernel.com>
|
||||
Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/regulator/s2mps11.c | 54 +++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 54 insertions(+)
|
||||
|
||||
diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c
|
||||
index b3ee46955986..5c4d4827a173 100644
|
||||
--- a/drivers/regulator/s2mps11.c
|
||||
+++ b/drivers/regulator/s2mps11.c
|
||||
@@ -1117,6 +1117,57 @@ static const struct regulator_desc s2mpu02_regulators[] = {
|
||||
regulator_desc_s2mpu02_buck7(7),
|
||||
};
|
||||
|
||||
+static int s2mps11_pmic_ethonoff(struct platform_device *pdev, bool onoff)
|
||||
+{
|
||||
+ struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
|
||||
+ unsigned int reg_val = 0;
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ ret = regmap_read(iodev->regmap_pmic, S2MPS11_REG_L15CTRL, ®_val);
|
||||
+ if (ret) {
|
||||
+ dev_err(&pdev->dev, "failed to read S2MPS11_REG_L15CTRL value\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = regmap_read(iodev->regmap_pmic, S2MPS11_REG_L17CTRL, ®_val);
|
||||
+ if (ret) {
|
||||
+ dev_err(&pdev->dev, "failed to read S2MPS11_REG_L17CTRL value\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ if (onoff) {
|
||||
+ /* ETH VDD0 ON */
|
||||
+ ret = regmap_update_bits(iodev->regmap_pmic, S2MPS11_REG_L15CTRL, 0xFF, 0x72);
|
||||
+ if (ret) {
|
||||
+ dev_err(&pdev->dev, "cannot update S2MPS11 LDO CTRL15 register\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* ETH VDD1 ON */
|
||||
+ ret = regmap_update_bits(iodev->regmap_pmic, S2MPS11_REG_L17CTRL, 0xFF, 0x72);
|
||||
+ if (ret) {
|
||||
+ dev_err(&pdev->dev, "cannot update S2MPS11 LDO CTRL17 register\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ } else {
|
||||
+ /* ETH VDD0 OFF */
|
||||
+ ret = regmap_update_bits(iodev->regmap_pmic, S2MPS11_REG_L15CTRL, 0x3F, 0x00);
|
||||
+ if (ret) {
|
||||
+ dev_err(&pdev->dev, "cannot update S2MPS11 LDO CTRL15 register\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* ETH VDD1 OFF */
|
||||
+ ret = regmap_update_bits(iodev->regmap_pmic, S2MPS11_REG_L17CTRL, 0x3F, 0x00);
|
||||
+ if (ret) {
|
||||
+ dev_err(&pdev->dev, "cannot update S2MPS11 LDO CTRL17 register\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
static int s2mps11_pmic_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
|
||||
@@ -1266,6 +1317,9 @@ static void s2mps11_pmic_shutdown(struct platform_device *pdev)
|
||||
"could not write S2MPS11_REG_CTRL1 value\n");
|
||||
}
|
||||
}
|
||||
+ s2mps11_pmic_ethonoff(pdev, false);
|
||||
+ mdelay(10);
|
||||
+ s2mps11_pmic_ethonoff(pdev, true);
|
||||
}
|
||||
|
||||
static const struct platform_device_id s2mps11_pmic_id[] = {
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
From 3e027f1d0043d15fa88969a364a3dbe7561574fa Mon Sep 17 00:00:00 2001
|
||||
From: Marian Mihailescu <mihailescu2m@gmail.com>
|
||||
Date: Thu, 14 Nov 2019 12:19:37 +1030
|
||||
Subject: [PATCH 20/24] MEMEKA: fix eMMC clock settings
|
||||
|
||||
---
|
||||
drivers/mmc/host/dw_mmc-exynos.h | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/mmc/host/dw_mmc-exynos.h b/drivers/mmc/host/dw_mmc-exynos.h
|
||||
index 0280d394a32a..7088e39de5d2 100644
|
||||
--- a/drivers/mmc/host/dw_mmc-exynos.h
|
||||
+++ b/drivers/mmc/host/dw_mmc-exynos.h
|
||||
@@ -61,7 +61,7 @@
|
||||
/* Fixed clock divider */
|
||||
#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
|
||||
#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
|
||||
-#define HS400_FIXED_CIU_CLK_DIV 1
|
||||
+#define HS400_FIXED_CIU_CLK_DIV 2
|
||||
|
||||
/* Minimal required clock frequency for cclkin, unit: HZ */
|
||||
#define EXYNOS_CCLKIN_MIN 50000000
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
From 452af1bb7e2d790c440a98473f797b991cfabe0c Mon Sep 17 00:00:00 2001
|
||||
From: Brian Kim <brian.kim@hardkernel.com>
|
||||
Date: Tue, 21 Nov 2017 18:44:03 +0900
|
||||
Subject: [PATCH 21/24] MEMEKA: ODROID-XU4: arm: Set the system revision
|
||||
information
|
||||
|
||||
wiringPi library refers to this information in '/proc/cpuinfo' file.
|
||||
|
||||
Signed-off-by: Yang Deokgyu <secugyu@gmail.com>
|
||||
Change-Id: I4a3368499cecf862eddb1430c6b436283f62d2c7
|
||||
Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
|
||||
---
|
||||
arch/arm/kernel/setup.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
|
||||
index d8e18cdd96d3..e302d6579c2a 100644
|
||||
--- a/arch/arm/kernel/setup.c
|
||||
+++ b/arch/arm/kernel/setup.c
|
||||
@@ -90,7 +90,7 @@ EXPORT_SYMBOL(cacheid);
|
||||
|
||||
unsigned int __atags_pointer __initdata;
|
||||
|
||||
-unsigned int system_rev;
|
||||
+unsigned int system_rev = 0x0100;
|
||||
EXPORT_SYMBOL(system_rev);
|
||||
|
||||
const char *system_serial;
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,106 +0,0 @@
|
|||
From fe64d2622d6fd880f35da93382e1de5077b681f3 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Hewitt <christianshewitt@gmail.com>
|
||||
Date: Wed, 29 Apr 2020 10:37:08 +0000
|
||||
Subject: [PATCH 24/24] WIP: ARM: dts: exynos5422: HC1/XU3/XU4 model name is
|
||||
ODROID not Odroid
|
||||
|
||||
Cosmetic change to model and audio card name for HC1/XU3/XU4 to
|
||||
put ODROID in capitals (as per Hardkernel branding). Also fixup
|
||||
some unneeded backslashes and wrap lines per kernel standards.
|
||||
|
||||
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/exynos5422-odroidhc1.dts | 4 ++--
|
||||
arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 2 +-
|
||||
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 5 +++--
|
||||
arch/arm/boot/dts/exynos5422-odroidxu3.dts | 5 +++--
|
||||
arch/arm/boot/dts/exynos5422-odroidxu4.dts | 6 +++---
|
||||
5 files changed, 12 insertions(+), 10 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
|
||||
index 812659260278..b90da73510cf 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
|
||||
@@ -11,8 +11,8 @@
|
||||
#include "exynos5422-odroid-core.dtsi"
|
||||
|
||||
/ {
|
||||
- model = "Hardkernel Odroid HC1";
|
||||
- compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \
|
||||
+ model = "Hardkernel ODROID HC1";
|
||||
+ compatible = "hardkernel,odroid-hc1", "samsung,exynos5800",
|
||||
"samsung,exynos5";
|
||||
|
||||
pwmleds {
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
|
||||
index c3c2d85267da..26961dcea010 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
|
||||
@@ -13,7 +13,7 @@
|
||||
/ {
|
||||
sound: sound {
|
||||
compatible = "samsung,odroid-xu3-audio";
|
||||
- model = "Odroid-XU3";
|
||||
+ model = "ODROID-XU3";
|
||||
|
||||
samsung,audio-widgets =
|
||||
"Headphone", "Headphone Jack",
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
|
||||
index 98feecad5489..d0084033199a 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
|
||||
@@ -14,8 +14,9 @@
|
||||
#include "exynos54xx-odroidxu-leds.dtsi"
|
||||
|
||||
/ {
|
||||
- model = "Hardkernel Odroid XU3 Lite";
|
||||
- compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5";
|
||||
+ model = "Hardkernel ODROID XU3 Lite";
|
||||
+ compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800",
|
||||
+ "samsung,exynos5";
|
||||
};
|
||||
|
||||
&arm_a7_pmu {
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
|
||||
index db0bc17a667b..3ff7ec514e20 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
|
||||
@@ -13,8 +13,9 @@
|
||||
#include "exynos54xx-odroidxu-leds.dtsi"
|
||||
|
||||
/ {
|
||||
- model = "Hardkernel Odroid XU3";
|
||||
- compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5";
|
||||
+ model = "Hardkernel ODROID XU3";
|
||||
+ compatible = "hardkernel,odroid-xu3", "samsung,exynos5800",
|
||||
+ "samsung,exynos5";
|
||||
};
|
||||
|
||||
&i2c_0 {
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
index 892d389d6d09..d2061b244537 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
@@ -13,8 +13,8 @@
|
||||
#include "exynos5422-odroidxu3-common.dtsi"
|
||||
|
||||
/ {
|
||||
- model = "Hardkernel Odroid XU4";
|
||||
- compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \
|
||||
+ model = "Hardkernel ODROID XU4";
|
||||
+ compatible = "hardkernel,odroid-xu4", "samsung,exynos5800",
|
||||
"samsung,exynos5";
|
||||
|
||||
pwmleds {
|
||||
@@ -31,7 +31,7 @@
|
||||
|
||||
sound: sound {
|
||||
compatible = "samsung,odroid-xu3-audio";
|
||||
- model = "Odroid-XU4";
|
||||
+ model = "ODROID-XU4";
|
||||
|
||||
samsung,audio-routing = "I2S Playback", "Mixer DAI TX";
|
||||
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,96 +0,0 @@
|
|||
From a3357e27883de2957ba36b73766cec00063b26e7 Mon Sep 17 00:00:00 2001
|
||||
From: Brian Kim <brian.kim@hardkernel.com>
|
||||
Date: Thu, 5 Jan 2017 19:05:44 +0900
|
||||
Subject: [PATCH 29/75] ODROID-XU4: drm/exynos/hdmi: add 'HPD' and 'vout' as
|
||||
boot parameters
|
||||
|
||||
Change-Id: Ia3c94b0ee99e761a774ac63398ca86477b703b8c
|
||||
Signed-off-by: Brian Kim <brian.kim@hardkernel.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/gpu/drm/exynos/exynos_hdmi.c | 39 +++++++++++++++++++++++++++-
|
||||
1 file changed, 38 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
|
||||
index dc01c188c0e0..98dc45e2eed6 100644
|
||||
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
|
||||
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
|
||||
@@ -145,6 +145,33 @@ struct hdmi_context {
|
||||
bool powered;
|
||||
};
|
||||
|
||||
+static bool gdvi_mode = false;
|
||||
+static bool gEnableHPD = true;
|
||||
+
|
||||
+static int __init dvi_force_enable(char *str)
|
||||
+{
|
||||
+ if (!strcmp(str, "dvi")) {
|
||||
+ gdvi_mode = true;
|
||||
+ pr_info("hdmi: using DVI mode\n");
|
||||
+ } else {
|
||||
+ gdvi_mode = false;
|
||||
+ pr_info("hdmi: using HDMI mode\n");
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+__setup("vout=", dvi_force_enable);
|
||||
+
|
||||
+static int __init hdmi_hpd_enable(char *str)
|
||||
+{
|
||||
+ if (!strcmp(str, "false")) {
|
||||
+ gEnableHPD = false;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+__setup("HPD=", hdmi_hpd_enable);
|
||||
+
|
||||
static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
|
||||
{
|
||||
return container_of(e, struct hdmi_context, encoder);
|
||||
@@ -845,6 +872,9 @@ static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
|
||||
{
|
||||
struct hdmi_context *hdata = connector_to_hdmi(connector);
|
||||
|
||||
+ if (!gEnableHPD)
|
||||
+ return connector_status_connected;
|
||||
+
|
||||
if (gpiod_get_value(hdata->hpd_gpio))
|
||||
return connector_status_connected;
|
||||
|
||||
@@ -884,7 +914,10 @@ static int hdmi_get_modes(struct drm_connector *connector)
|
||||
if (!edid)
|
||||
return -ENODEV;
|
||||
|
||||
- hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
|
||||
+ if (gdvi_mode)
|
||||
+ hdata->dvi_mode = true;
|
||||
+ else
|
||||
+ hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
|
||||
DRM_DEV_DEBUG_KMS(hdata->dev, "%s : width[%d] x height[%d]\n",
|
||||
(hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
|
||||
edid->width_cm, edid->height_cm);
|
||||
@@ -1581,6 +1614,9 @@ static int hdmi_audio_hw_params(struct device *dev, void *data,
|
||||
{
|
||||
struct hdmi_context *hdata = dev_get_drvdata(dev);
|
||||
|
||||
+ if (hdata->dvi_mode)
|
||||
+ return 0;
|
||||
+
|
||||
if (daifmt->fmt != HDMI_I2S || daifmt->bit_clk_inv ||
|
||||
daifmt->frame_clk_inv || daifmt->bit_clk_master ||
|
||||
daifmt->frame_clk_master) {
|
||||
@@ -1957,6 +1993,7 @@ static int hdmi_probe(struct platform_device *pdev)
|
||||
platform_set_drvdata(pdev, hdata);
|
||||
|
||||
hdata->dev = dev;
|
||||
+ hdata->dvi_mode = gdvi_mode;
|
||||
|
||||
mutex_init(&hdata->mutex);
|
||||
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
From 3cc732d6c3d8d00a1b5c3a00c0268fc45e3ff008 Mon Sep 17 00:00:00 2001
|
||||
From: memeka <mihailescu2m@gmail.com>
|
||||
Date: Tue, 10 Jul 2018 22:13:03 +0930
|
||||
Subject: [PATCH 40/75] ODROID-XU4: thermal: exynos: add support for 8 trip
|
||||
points on Exynos5422 TMU
|
||||
|
||||
Change-Id: I6014d6d3fdecb6f58c6160f79ac969c6816f365d
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/thermal/samsung/exynos_tmu.c | 18 ++++++++++++++++--
|
||||
1 file changed, 16 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
|
||||
index e9a90bc23b11..b49df21fa0e7 100644
|
||||
--- a/drivers/thermal/samsung/exynos_tmu.c
|
||||
+++ b/drivers/thermal/samsung/exynos_tmu.c
|
||||
@@ -915,8 +915,6 @@ static int exynos_map_dt_data(struct platform_device *pdev)
|
||||
case SOC_ARCH_EXYNOS4412:
|
||||
case SOC_ARCH_EXYNOS5250:
|
||||
case SOC_ARCH_EXYNOS5260:
|
||||
- case SOC_ARCH_EXYNOS5420:
|
||||
- case SOC_ARCH_EXYNOS5420_TRIMINFO:
|
||||
data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp;
|
||||
data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst;
|
||||
data->tmu_initialize = exynos4412_tmu_initialize;
|
||||
@@ -935,6 +933,22 @@ static int exynos_map_dt_data(struct platform_device *pdev)
|
||||
data->min_efuse_value = 0;
|
||||
data->max_efuse_value = 100;
|
||||
break;
|
||||
+ case SOC_ARCH_EXYNOS5420:
|
||||
+ case SOC_ARCH_EXYNOS5420_TRIMINFO:
|
||||
+ data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp;
|
||||
+ data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst;
|
||||
+ data->tmu_initialize = exynos4412_tmu_initialize;
|
||||
+ data->tmu_control = exynos4210_tmu_control;
|
||||
+ data->tmu_read = exynos4412_tmu_read;
|
||||
+ data->tmu_set_emulation = exynos4412_tmu_set_emulation;
|
||||
+ data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
|
||||
+ data->ntrip = 8;
|
||||
+ data->gain = 8;
|
||||
+ data->reference_voltage = 16;
|
||||
+ data->efuse_value = 55;
|
||||
+ data->min_efuse_value = 16;
|
||||
+ data->max_efuse_value = 76;
|
||||
+ break;
|
||||
case SOC_ARCH_EXYNOS5433:
|
||||
data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp;
|
||||
data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
From 04304061f1b9191547375092bfc58bc704d8a55c Mon Sep 17 00:00:00 2001
|
||||
From: memeka <mihailescu2m@gmail.com>
|
||||
Date: Tue, 22 Jan 2019 11:55:07 +1030
|
||||
Subject: [PATCH 41/75] ODROID-XU4: arm: dts: exynos5422: enable Exynos5422 TMU
|
||||
|
||||
Change-Id: I3fb73f0f9a2f349fc667354a607c50ffefa7084e
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
index b1cf9414ce17..7f2f53843435 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
@@ -1024,22 +1024,27 @@ &ppmu_dmc1_1 {
|
||||
|
||||
&tmu_cpu0 {
|
||||
vtmu-supply = <&ldo7_reg>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&tmu_cpu1 {
|
||||
vtmu-supply = <&ldo7_reg>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&tmu_cpu2 {
|
||||
vtmu-supply = <&ldo7_reg>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&tmu_cpu3 {
|
||||
vtmu-supply = <&ldo7_reg>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&tmu_gpu {
|
||||
vtmu-supply = <&ldo7_reg>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
From ce0b1374f53bcf6cb7fa16e637d6d8387c31c091 Mon Sep 17 00:00:00 2001
|
||||
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
Date: Tue, 10 Sep 2019 14:36:18 +0200
|
||||
Subject: [PATCH 42/75] ODROID-XU4: ARM: dts: Add samsung,asv-bin property for
|
||||
odroidxu3-lite
|
||||
|
||||
The Exynos5422 SoC used on Odroid XU3 Lite boards belongs to
|
||||
a special ASV bin but this information cannot be read from the
|
||||
CHIPID block registers. Add samsung,asv-bin property for XU3
|
||||
Lite to ensure the ASV bin is properly determined.
|
||||
|
||||
Change-Id: I6e977b9cf0829be7ffff5aa84d7ee6b3e65b49cd
|
||||
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
|
||||
index 98feecad5489..140d81374bfa 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
|
||||
@@ -88,6 +88,10 @@ &cpu3_cooling_map4 {
|
||||
<&cpu7 3 12>;
|
||||
};
|
||||
|
||||
+&chipid {
|
||||
+ samsung,asv-bin = <2>;
|
||||
+};
|
||||
+
|
||||
&pwm {
|
||||
/*
|
||||
* PWM 0 -- fan
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
From 50f1a0085859d61270abd464ba1a08403b8f75f2 Mon Sep 17 00:00:00 2001
|
||||
From: Yang Deokgyu <secugyu@gmail.com>
|
||||
Date: Thu, 14 Nov 2019 13:45:22 +0900
|
||||
Subject: [PATCH 50/75] ODROID-XU4: Add support for SPI1 on the 40 pin header
|
||||
|
||||
Signed-off-by: Yang Deokgyu <secugyu@gmail.com>
|
||||
Change-Id: I0b1d16b0f445838509eeb0cc8093239fa1805605
|
||||
---
|
||||
arch/arm/boot/dts/exynos5422-odroidxu4.dts | 20 ++++++++++++++++++++
|
||||
drivers/spi/spidev.c | 2 ++
|
||||
2 files changed, 22 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
index fcbe23b6a7eb..3d68fca093ee 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
@@ -11,6 +11,7 @@
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/sound/samsung-i2s.h>
|
||||
#include "exynos5422-odroidxu3-common.dtsi"
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Hardkernel Odroid XU4";
|
||||
@@ -103,3 +104,22 @@ &hsi2c_5 {
|
||||
samsung,hs-mode;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
+
|
||||
+&spi_1 {
|
||||
+ status = "okay";
|
||||
+ samsung,spi-src-clk = <0>;
|
||||
+ num-cs = <2>;
|
||||
+ cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>, <&gpx2 1 GPIO_ACTIVE_HIGH>;
|
||||
+
|
||||
+ spidev: spidev@0 {
|
||||
+ status = "okay";
|
||||
+ reg = <0>;
|
||||
+ compatible = "odroid,spidev";
|
||||
+ spi-max-frequency = <1000000>;
|
||||
+
|
||||
+ controller-data {
|
||||
+ cs-gpio = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
+ samsung,spi-feedback-delay = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
|
||||
index 859910ec8d9f..02b01e3bba81 100644
|
||||
--- a/drivers/spi/spidev.c
|
||||
+++ b/drivers/spi/spidev.c
|
||||
@@ -682,6 +682,8 @@ static const struct of_device_id spidev_dt_ids[] = {
|
||||
{ .compatible = "lwn,bk4" },
|
||||
{ .compatible = "dh,dhcom-board" },
|
||||
{ .compatible = "menlo,m53cpld" },
|
||||
+ /* ODROID Modification */
|
||||
+ { .compatible = "odroid,spidev" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, spidev_dt_ids);
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,343 +0,0 @@
|
|||
From 9beecd44246ce55c87bb0641ae5788595c761b8e Mon Sep 17 00:00:00 2001
|
||||
From: Brian Kim <brian.kim@hardkernel.com>
|
||||
Date: Tue, 10 Jan 2017 11:31:52 +0900
|
||||
Subject: [PATCH 51/75] ODROID-XU4: char: exynos: add /dev/gpiomem device for
|
||||
rootless user GPIO access
|
||||
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
Signed-off-by: Yang Deokgyu <secugyu@gmail.com>
|
||||
Change-Id: Ia6b9596501223037ee3be3587d720f74a2494380
|
||||
---
|
||||
.../boot/dts/exynos5422-odroidxu3-common.dtsi | 7 +
|
||||
drivers/char/Kconfig | 9 +
|
||||
drivers/char/Makefile | 1 +
|
||||
drivers/char/exynos-gpiomem.c | 270 ++++++++++++++++++
|
||||
4 files changed, 287 insertions(+)
|
||||
create mode 100644 drivers/char/exynos-gpiomem.c
|
||||
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
|
||||
index 5da2d81e3be2..ad8c85d1b7ae 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
|
||||
@@ -34,6 +34,13 @@ power_key {
|
||||
};
|
||||
};
|
||||
|
||||
+ gpiomem {
|
||||
+ compatible = "samsung,exynos-gpiomem";
|
||||
+ reg = <0x13400000 0x1000>,
|
||||
+ <0x14010000 0x1000>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
emmc_pwrseq: pwrseq {
|
||||
pinctrl-0 = <&emmc_nrst_pin>;
|
||||
pinctrl-names = "default";
|
||||
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
|
||||
index d229a2d0c017..530d3af84aa8 100644
|
||||
--- a/drivers/char/Kconfig
|
||||
+++ b/drivers/char/Kconfig
|
||||
@@ -471,6 +471,15 @@ config ADI
|
||||
and SSM (Silicon Secured Memory). Intended consumers of this
|
||||
driver include crash and makedumpfile.
|
||||
|
||||
+config EXYNOS_GPIOMEM
|
||||
+ tristate "/dev/gpiomem rootless GPIO access via mmap() on the EXYNOS"
|
||||
+ default m
|
||||
+ help
|
||||
+ Provides users with root-free access to the GPIO registers
|
||||
+ on EXYNOS. Calling mmap(/dev/gpiomem) will map the GPIO register
|
||||
+ page to the user's pointer. This drvier can allow to access gpio
|
||||
+ memory area in user account.
|
||||
+
|
||||
endmenu
|
||||
|
||||
config RANDOM_TRUST_CPU
|
||||
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
|
||||
index ffce287ef415..923df22cf799 100644
|
||||
--- a/drivers/char/Makefile
|
||||
+++ b/drivers/char/Makefile
|
||||
@@ -47,3 +47,4 @@ obj-$(CONFIG_PS3_FLASH) += ps3flash.o
|
||||
obj-$(CONFIG_XILLYBUS) += xillybus/
|
||||
obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o
|
||||
obj-$(CONFIG_ADI) += adi.o
|
||||
+obj-$(CONFIG_EXYNOS_GPIOMEM) += exynos-gpiomem.o
|
||||
diff --git a/drivers/char/exynos-gpiomem.c b/drivers/char/exynos-gpiomem.c
|
||||
new file mode 100644
|
||||
index 000000000000..5dd684d48ffc
|
||||
--- /dev/null
|
||||
+++ b/drivers/char/exynos-gpiomem.c
|
||||
@@ -0,0 +1,270 @@
|
||||
+/*
|
||||
+ * linux/drivers/char/exynos-gpiomem.c
|
||||
+ *
|
||||
+ * GPIO memory device driver
|
||||
+ *
|
||||
+ * Creates a chardev /dev/gpiomem which will provide user access to
|
||||
+ * the EXYNOS's GPIO registers when it is mmap()'d.
|
||||
+ * No longer need root for user GPIO access, but without relaxing permissions
|
||||
+ * on /dev/mem.
|
||||
+ *
|
||||
+ * Copyright (c) 2017 Hardkernel Co., Ltd.
|
||||
+ *
|
||||
+ * This driver is based on bcm2835-gpiomem.c in Raspberrypi's linux kernel 4.4:
|
||||
+ * Written by Luke Wren <luke@raspberrypi.org>
|
||||
+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
|
||||
+ *
|
||||
+ * Redistribution and use in source and binary forms, with or without
|
||||
+ * modification, are permitted provided that the following conditions
|
||||
+ * are met:
|
||||
+ * 1. Redistributions of source code must retain the above copyright
|
||||
+ * notice, this list of conditions, and the following disclaimer,
|
||||
+ * without modification.
|
||||
+ * 2. Redistributions in binary form must reproduce the above copyright
|
||||
+ * notice, this list of conditions and the following disclaimer in the
|
||||
+ * documentation and/or other materials provided with the distribution.
|
||||
+ * 3. The names of the above-listed copyright holders may not be used
|
||||
+ * to endorse or promote products derived from this software without
|
||||
+ * specific prior written permission.
|
||||
+ *
|
||||
+ * ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
+ * GNU General Public License ("GPL") version 2, as published by the Free
|
||||
+ * Software Foundation.
|
||||
+ *
|
||||
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/mm.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/cdev.h>
|
||||
+#include <linux/pagemap.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <asm/io.h>
|
||||
+
|
||||
+#define DEVICE_NAME "exynos-gpiomem"
|
||||
+#define DRIVER_NAME "gpiomem-exynos"
|
||||
+#define DEVICE_MINOR 0
|
||||
+
|
||||
+struct exynos_gpiomem_instance {
|
||||
+ unsigned long gpio_regs_phys[32];
|
||||
+ int gpio_area_count;
|
||||
+ struct device *dev;
|
||||
+};
|
||||
+
|
||||
+static struct cdev exynos_gpiomem_cdev;
|
||||
+static dev_t exynos_gpiomem_devid;
|
||||
+static struct class *exynos_gpiomem_class;
|
||||
+static struct device *exynos_gpiomem_dev;
|
||||
+static struct exynos_gpiomem_instance *inst;
|
||||
+
|
||||
+static int exynos_gpiomem_open(struct inode *inode, struct file *file)
|
||||
+{
|
||||
+ int dev = iminor(inode);
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ dev_info(inst->dev, "gpiomem device opened.");
|
||||
+
|
||||
+ if (dev != DEVICE_MINOR) {
|
||||
+ dev_err(inst->dev, "Unknown minor device: %d", dev);
|
||||
+ ret = -ENXIO;
|
||||
+ }
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int exynos_gpiomem_release(struct inode *inode, struct file *file)
|
||||
+{
|
||||
+ int dev = iminor(inode);
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ if (dev != DEVICE_MINOR) {
|
||||
+ dev_err(inst->dev, "Unknown minor device %d", dev);
|
||||
+ ret = -ENXIO;
|
||||
+ }
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static const struct vm_operations_struct exynos_gpiomem_vm_ops = {
|
||||
+#ifdef CONFIG_HAVE_IOREMAP_PROT
|
||||
+ .access = generic_access_phys
|
||||
+#endif
|
||||
+};
|
||||
+
|
||||
+static int exynos_gpiomem_mmap(struct file *file, struct vm_area_struct *vma)
|
||||
+{
|
||||
+ int gpio_area = 0;
|
||||
+
|
||||
+ while (gpio_area < inst->gpio_area_count) {
|
||||
+ if ((inst->gpio_regs_phys[gpio_area] >> PAGE_SHIFT) == vma->vm_pgoff)
|
||||
+ goto found;
|
||||
+
|
||||
+ gpio_area++;
|
||||
+ }
|
||||
+
|
||||
+ return -EACCES;
|
||||
+
|
||||
+found:
|
||||
+ vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_pgoff,
|
||||
+ PAGE_SIZE,
|
||||
+ vma->vm_page_prot);
|
||||
+
|
||||
+ vma->vm_ops = &exynos_gpiomem_vm_ops;
|
||||
+
|
||||
+ if (remap_pfn_range(vma, vma->vm_start,
|
||||
+ vma->vm_pgoff,
|
||||
+ PAGE_SIZE,
|
||||
+ vma->vm_page_prot)) {
|
||||
+ return -EAGAIN;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct file_operations
|
||||
+exynos_gpiomem_fops = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .open = exynos_gpiomem_open,
|
||||
+ .release = exynos_gpiomem_release,
|
||||
+ .mmap = exynos_gpiomem_mmap,
|
||||
+};
|
||||
+
|
||||
+static int exynos_gpiomem_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ int err = 0;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct device_node *np = dev->of_node;
|
||||
+ struct resource *res = NULL;
|
||||
+ int i = 0;
|
||||
+
|
||||
+ /* Allocate buffers and instance data */
|
||||
+ inst = kzalloc(sizeof(struct exynos_gpiomem_instance), GFP_KERNEL);
|
||||
+
|
||||
+ if (!inst) {
|
||||
+ err = -ENOMEM;
|
||||
+ goto failed_inst_alloc;
|
||||
+ }
|
||||
+
|
||||
+ inst->dev = dev;
|
||||
+
|
||||
+ inst->gpio_area_count = of_property_count_elems_of_size(np, "reg",
|
||||
+ sizeof(u32)) / 2;
|
||||
+
|
||||
+ if (inst->gpio_area_count > 32 || inst->gpio_area_count <= 0) {
|
||||
+ dev_err(inst->dev, "failed to get gpio register area.");
|
||||
+ err = -EINVAL;
|
||||
+ goto failed_inst_alloc;
|
||||
+ }
|
||||
+
|
||||
+ dev_info(inst->dev, "Initialised: GPIO register area is %d",
|
||||
+ inst->gpio_area_count);
|
||||
+
|
||||
+ for (i = 0; i < inst->gpio_area_count; ++i) {
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||
+ if (res) {
|
||||
+ inst->gpio_regs_phys[i] = res->start;
|
||||
+ } else {
|
||||
+ dev_err(inst->dev, "failed to get IO resource");
|
||||
+ err = -ENOENT;
|
||||
+ goto failed_get_resource;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* Create character device entries */
|
||||
+ err = alloc_chrdev_region(&exynos_gpiomem_devid,
|
||||
+ DEVICE_MINOR, 1, DEVICE_NAME);
|
||||
+ if (err != 0) {
|
||||
+ dev_err(inst->dev, "unable to allocate device number");
|
||||
+ goto failed_alloc_chrdev;
|
||||
+ }
|
||||
+ cdev_init(&exynos_gpiomem_cdev, &exynos_gpiomem_fops);
|
||||
+ exynos_gpiomem_cdev.owner = THIS_MODULE;
|
||||
+ err = cdev_add(&exynos_gpiomem_cdev, exynos_gpiomem_devid, 1);
|
||||
+ if (err != 0) {
|
||||
+ dev_err(inst->dev, "unable to register device");
|
||||
+ goto failed_cdev_add;
|
||||
+ }
|
||||
+
|
||||
+ /* Create sysfs entries */
|
||||
+ exynos_gpiomem_class = class_create(THIS_MODULE, DEVICE_NAME);
|
||||
+ err = IS_ERR(exynos_gpiomem_class);
|
||||
+ if (err)
|
||||
+ goto failed_class_create;
|
||||
+
|
||||
+ exynos_gpiomem_dev = device_create(exynos_gpiomem_class, NULL,
|
||||
+ exynos_gpiomem_devid, NULL,
|
||||
+ "gpiomem");
|
||||
+ err = IS_ERR(exynos_gpiomem_dev);
|
||||
+ if (err)
|
||||
+ goto failed_device_create;
|
||||
+
|
||||
+ for (i = 0; i < inst->gpio_area_count; ++i) {
|
||||
+ dev_info(inst->dev, "Initialised: Registers at 0x%08lx",
|
||||
+ inst->gpio_regs_phys[i]);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+failed_device_create:
|
||||
+ class_destroy(exynos_gpiomem_class);
|
||||
+failed_class_create:
|
||||
+ cdev_del(&exynos_gpiomem_cdev);
|
||||
+failed_cdev_add:
|
||||
+ unregister_chrdev_region(exynos_gpiomem_devid, 1);
|
||||
+failed_alloc_chrdev:
|
||||
+failed_get_resource:
|
||||
+ kfree(inst);
|
||||
+failed_inst_alloc:
|
||||
+ dev_err(inst->dev, "could not load exynos_gpiomem");
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static int exynos_gpiomem_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = inst->dev;
|
||||
+
|
||||
+ kfree(inst);
|
||||
+ device_destroy(exynos_gpiomem_class, exynos_gpiomem_devid);
|
||||
+ class_destroy(exynos_gpiomem_class);
|
||||
+ cdev_del(&exynos_gpiomem_cdev);
|
||||
+ unregister_chrdev_region(exynos_gpiomem_devid, 1);
|
||||
+
|
||||
+ dev_info(dev, "GPIO mem driver removed - OK");
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id exynos_gpiomem_of_match[] = {
|
||||
+ {.compatible = "samsung,exynos-gpiomem",},
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, exynos_gpiomem_of_match);
|
||||
+
|
||||
+static struct platform_driver exynos_gpiomem_driver = {
|
||||
+ .driver = {
|
||||
+ .name = DRIVER_NAME,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = exynos_gpiomem_of_match,
|
||||
+ },
|
||||
+ .probe = exynos_gpiomem_probe,
|
||||
+ .remove = exynos_gpiomem_remove,
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(exynos_gpiomem_driver);
|
||||
+
|
||||
+MODULE_ALIAS("platform:gpiomem-exynos");
|
||||
+MODULE_DESCRIPTION("EXYNOS gpiomem driver for accessing GPIO from userspace");
|
||||
+MODULE_AUTHOR("Brian Kim <brian.kim@hardkernel.com>");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
From e1c4bb560a505f311dc866b1a957ee7a8d886093 Mon Sep 17 00:00:00 2001
|
||||
From: Dongjin Kim <tobetter@gmail.com>
|
||||
Date: Thu, 9 Nov 2017 22:09:37 -0500
|
||||
Subject: [PATCH 54/75] ODROID-XU4: ARM: exynos: add machine description for
|
||||
ODROID-XU3/4
|
||||
|
||||
Change-Id: Ice75e06366f107f761504512a84fb92affffb124
|
||||
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
|
||||
---
|
||||
arch/arm/mach-exynos/exynos.c | 28 ++++++++++++++++++++++++++++
|
||||
1 file changed, 28 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
|
||||
index 700763e07083..21f372074f19 100644
|
||||
--- a/arch/arm/mach-exynos/exynos.c
|
||||
+++ b/arch/arm/mach-exynos/exynos.c
|
||||
@@ -217,3 +217,31 @@ DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)")
|
||||
.dt_compat = exynos_dt_compat,
|
||||
.dt_fixup = exynos_dt_fixup,
|
||||
MACHINE_END
|
||||
+
|
||||
+#define ODROID_MACHINE_START(name, compat) \
|
||||
+ DT_MACHINE_START(EXYNOS5422_ODROID_##name, "ODROID-"#name) \
|
||||
+ .l2c_aux_val = 0x3c400001, \
|
||||
+ .l2c_aux_mask = 0xc20fffff, \
|
||||
+ .smp = smp_ops(exynos_smp_ops), \
|
||||
+ .map_io = exynos_init_io, \
|
||||
+ .init_early = exynos_firmware_init, \
|
||||
+ .init_irq = exynos_init_irq, \
|
||||
+ .init_machine = exynos_dt_machine_init, \
|
||||
+ .init_late = exynos_init_late, \
|
||||
+ .dt_compat = compat, \
|
||||
+ .dt_fixup = exynos_dt_fixup, \
|
||||
+ MACHINE_END
|
||||
+
|
||||
+static char const *const exynos5422_odroidxu3_dt_compat[] __initconst = {
|
||||
+ "hardkernel,odroid-xu3",
|
||||
+ "hardkernel,odroid-xu3-lite",
|
||||
+ NULL,
|
||||
+};
|
||||
+
|
||||
+static char const *const exynos5422_odroidxu4_dt_compat[] __initconst = {
|
||||
+ "hardkernel,odroid-xu4",
|
||||
+ NULL,
|
||||
+};
|
||||
+
|
||||
+ODROID_MACHINE_START(XU3, exynos5422_odroidxu3_dt_compat)
|
||||
+ODROID_MACHINE_START(XU4, exynos5422_odroidxu4_dt_compat)
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
From c08d687dc99ef9622fe0e88080b9a2868cebfd41 Mon Sep 17 00:00:00 2001
|
||||
From: Yang Deokgyu <secugyu@gmail.com>
|
||||
Date: Thu, 5 Dec 2019 10:09:00 +0900
|
||||
Subject: [PATCH 55/75] ODROID-XU4: arm/exynos: No need to use enynos_init_late
|
||||
|
||||
Signed-off-by: Yang Deokgyu <secugyu@gmail.com>
|
||||
Change-Id: I7d141a655c23bf364753be9831b4428ee3aa6711
|
||||
---
|
||||
arch/arm/mach-exynos/exynos.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
|
||||
index 21f372074f19..e74ce13ba167 100644
|
||||
--- a/arch/arm/mach-exynos/exynos.c
|
||||
+++ b/arch/arm/mach-exynos/exynos.c
|
||||
@@ -227,7 +227,7 @@ MACHINE_END
|
||||
.init_early = exynos_firmware_init, \
|
||||
.init_irq = exynos_init_irq, \
|
||||
.init_machine = exynos_dt_machine_init, \
|
||||
- .init_late = exynos_init_late, \
|
||||
+ .init_late = exynos_pm_init, \
|
||||
.dt_compat = compat, \
|
||||
.dt_fixup = exynos_dt_fixup, \
|
||||
MACHINE_END
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
From 9c9cdceaedec031394e48fd922df8c5c5cf5c1e2 Mon Sep 17 00:00:00 2001
|
||||
From: Yang Deokgyu <secugyu@gmail.com>
|
||||
Date: Thu, 5 Dec 2019 10:13:54 +0900
|
||||
Subject: [PATCH 56/75] ODROID-XU4: arm/exynos: Add vendor name Hardkernel to
|
||||
its H/W information
|
||||
|
||||
Because the other devices we provided have vendor name in /proc/cpuinfo.
|
||||
|
||||
Signed-off-by: Yang Deokgyu <secugyu@gmail.com>
|
||||
Change-Id: I81a553ea8f662016b702cbb5e543ba7a769e8d0f
|
||||
---
|
||||
arch/arm/mach-exynos/exynos.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
|
||||
index e74ce13ba167..e880dedfb184 100644
|
||||
--- a/arch/arm/mach-exynos/exynos.c
|
||||
+++ b/arch/arm/mach-exynos/exynos.c
|
||||
@@ -219,7 +219,7 @@ DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)")
|
||||
MACHINE_END
|
||||
|
||||
#define ODROID_MACHINE_START(name, compat) \
|
||||
- DT_MACHINE_START(EXYNOS5422_ODROID_##name, "ODROID-"#name) \
|
||||
+ DT_MACHINE_START(EXYNOS5422_ODROID_##name, "Hardkernel ODROID-"#name) \
|
||||
.l2c_aux_val = 0x3c400001, \
|
||||
.l2c_aux_mask = 0xc20fffff, \
|
||||
.smp = smp_ops(exynos_smp_ops), \
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
From 88eeb919b3e65227ef22d106e90dc5f8434d0c60 Mon Sep 17 00:00:00 2001
|
||||
From: Yang Deokgyu <secugyu@gmail.com>
|
||||
Date: Tue, 22 Oct 2019 15:17:19 +0900
|
||||
Subject: [PATCH 57/75] ODROID-XU4: char/exynos-gpiomem: Remove unnecessary
|
||||
kernel logs noticed when every time it opens
|
||||
|
||||
Change-Id: If35e49c6d96b960f0ff1a997b2126c2c6378fdad
|
||||
Signed-off-by: Yang Deokgyu <secugyu@gmail.com>
|
||||
---
|
||||
drivers/char/exynos-gpiomem.c | 2 --
|
||||
1 file changed, 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/char/exynos-gpiomem.c b/drivers/char/exynos-gpiomem.c
|
||||
index 5dd684d48ffc..03ea4344346a 100644
|
||||
--- a/drivers/char/exynos-gpiomem.c
|
||||
+++ b/drivers/char/exynos-gpiomem.c
|
||||
@@ -77,8 +77,6 @@ static int exynos_gpiomem_open(struct inode *inode, struct file *file)
|
||||
int dev = iminor(inode);
|
||||
int ret = 0;
|
||||
|
||||
- dev_info(inst->dev, "gpiomem device opened.");
|
||||
-
|
||||
if (dev != DEVICE_MINOR) {
|
||||
dev_err(inst->dev, "Unknown minor device: %d", dev);
|
||||
ret = -ENXIO;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,350 +0,0 @@
|
|||
From 8a0509c200878d64282680772471320f772991be Mon Sep 17 00:00:00 2001
|
||||
From: Yang Deokgyu <secugyu@gmail.com>
|
||||
Date: Mon, 18 Nov 2019 12:10:34 +0900
|
||||
Subject: [PATCH 58/75] ODROID-XU4: drivers/fbtft: Add fb_hktft35 module for
|
||||
Hardkernel 3.5 inch TFT LCD
|
||||
|
||||
No longer use flexfb, fbtft_device that is deprecated since kernel 5.4.
|
||||
|
||||
Signed-off-by: Yang Deokgyu <secugyu@gmail.com>
|
||||
Change-Id: Iae252c64b91b2eabe97eb3aace12d7c4b98801c5
|
||||
---
|
||||
drivers/staging/fbtft/Kconfig | 7 +
|
||||
drivers/staging/fbtft/Makefile | 1 +
|
||||
drivers/staging/fbtft/fb_hktft35.c | 300 +++++++++++++++++++++++++++++
|
||||
3 files changed, 308 insertions(+)
|
||||
create mode 100644 drivers/staging/fbtft/fb_hktft35.c
|
||||
|
||||
diff --git a/drivers/staging/fbtft/Kconfig b/drivers/staging/fbtft/Kconfig
|
||||
index dad1ddcd7b0c..b6cd416ebb26 100644
|
||||
--- a/drivers/staging/fbtft/Kconfig
|
||||
+++ b/drivers/staging/fbtft/Kconfig
|
||||
@@ -206,3 +206,10 @@ config FB_TFT_WATTEROTT
|
||||
depends on FB_TFT
|
||||
help
|
||||
Generic Framebuffer support for WATTEROTT
|
||||
+
|
||||
+config FB_TFT_HKTFT35
|
||||
+ tristate "FB driver for the Hardkernel 3.5 inch TFT LCD"
|
||||
+ depends on FB_TFT
|
||||
+ help
|
||||
+ Generic Framebuffer support for the Hardkernel 3.5 inch TFT LCD
|
||||
+ that uses the ILI9488 LCD Controller
|
||||
diff --git a/drivers/staging/fbtft/Makefile b/drivers/staging/fbtft/Makefile
|
||||
index e87193f7df14..3d41175663ed 100644
|
||||
--- a/drivers/staging/fbtft/Makefile
|
||||
+++ b/drivers/staging/fbtft/Makefile
|
||||
@@ -37,3 +37,4 @@ obj-$(CONFIG_FB_TFT_UC1611) += fb_uc1611.o
|
||||
obj-$(CONFIG_FB_TFT_UC1701) += fb_uc1701.o
|
||||
obj-$(CONFIG_FB_TFT_UPD161704) += fb_upd161704.o
|
||||
obj-$(CONFIG_FB_TFT_WATTEROTT) += fb_watterott.o
|
||||
+obj-$(CONFIG_FB_TFT_HKTFT35) += fb_hktft35.o
|
||||
diff --git a/drivers/staging/fbtft/fb_hktft35.c b/drivers/staging/fbtft/fb_hktft35.c
|
||||
new file mode 100644
|
||||
index 000000000000..2389343492d4
|
||||
--- /dev/null
|
||||
+++ b/drivers/staging/fbtft/fb_hktft35.c
|
||||
@@ -0,0 +1,300 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * FB driver for the Hardkernel 3.5 inch TFT LCD
|
||||
+ * that uses the ILI9488 LCD Controller
|
||||
+ *
|
||||
+ * Copyright (C) 2019 Yang Deokgyu
|
||||
+ *
|
||||
+ * Based on fb_ili9340.c by Noralf Tronnes
|
||||
+ */
|
||||
+
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/vmalloc.h>
|
||||
+#include <linux/gpio/consumer.h>
|
||||
+#include <linux/backlight.h>
|
||||
+#include <linux/delay.h>
|
||||
+
|
||||
+#include "fbtft.h"
|
||||
+
|
||||
+#define DRVNAME "fb_hktft35"
|
||||
+#define WIDTH 320
|
||||
+#define HEIGHT 480
|
||||
+
|
||||
+#define ODROIDXU3_GPX1_REG 0x13400C24
|
||||
+#define ODROIDXU3_GPX2_REG 0x13400C44
|
||||
+#define ODROIDXU3_GPA2_REG 0x14010044
|
||||
+
|
||||
+#define ODROID_TFT35_MACTL_MV 0x20
|
||||
+#define ODROID_TFT35_MACTL_MX 0x40
|
||||
+#define ODROID_TFT35_MACTL_MY 0x80
|
||||
+
|
||||
+union reg_bitfield {
|
||||
+ unsigned int wvalue;
|
||||
+ struct {
|
||||
+ unsigned int bit0 : 1;
|
||||
+ unsigned int bit1 : 1;
|
||||
+ unsigned int bit2 : 1;
|
||||
+ unsigned int bit3 : 1;
|
||||
+ unsigned int bit4 : 1;
|
||||
+ unsigned int bit5 : 1;
|
||||
+ unsigned int bit6 : 1;
|
||||
+ unsigned int bit7 : 1;
|
||||
+ unsigned int bit8_bit31 : 24;
|
||||
+ } bits;
|
||||
+};
|
||||
+
|
||||
+volatile void __iomem *reg_gpx1;
|
||||
+volatile void __iomem *reg_gpx2;
|
||||
+volatile void __iomem *reg_gpa2;
|
||||
+
|
||||
+/* this init sequence matches Hardkernel 3.5 inch TFT LCD */
|
||||
+static const s16 default_init_sequence[] = {
|
||||
+ -1, 0xB0,0x00,
|
||||
+ -1, 0x11,
|
||||
+ -2, 120,
|
||||
+ -1, 0x3A,0x55,
|
||||
+ -1, 0xC2,0x33,
|
||||
+ -1, 0xC5,0x00,0x1E,0x80,
|
||||
+ -1, 0x36,0x28,
|
||||
+ -1, 0xB1,0xB0,
|
||||
+ -1, 0xE0,0x00,0x04,0x0E,0x08,0x17,0x0A,0x40,0x79,0x4D,0x07,0x0E,0x0A,0x1A,0x1D,0x0F,
|
||||
+ -1, 0xE1,0x00,0x1B,0x1F,0x02,0x10,0x05,0x32,0x34,0x43,0x02,0x0A,0x09,0x33,0x37,0x0F,
|
||||
+ -1, 0x11,
|
||||
+ -1, 0x29,
|
||||
+ -3
|
||||
+};
|
||||
+
|
||||
+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
|
||||
+{
|
||||
+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
|
||||
+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
|
||||
+
|
||||
+ /* Column address */
|
||||
+ write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
|
||||
+
|
||||
+ /* Row adress */
|
||||
+ write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
|
||||
+
|
||||
+ /* Memory write */
|
||||
+ write_reg(par, 0x2C);
|
||||
+}
|
||||
+
|
||||
+static int set_var(struct fbtft_par *par)
|
||||
+{
|
||||
+ u8 val;
|
||||
+
|
||||
+ switch (par->info->var.rotate) {
|
||||
+ case 270:
|
||||
+ val = ODROID_TFT35_MACTL_MV;
|
||||
+ break;
|
||||
+ case 180:
|
||||
+ val = ODROID_TFT35_MACTL_MY;
|
||||
+ break;
|
||||
+ case 90:
|
||||
+ val = ODROID_TFT35_MACTL_MV | ODROID_TFT35_MACTL_MX | ODROID_TFT35_MACTL_MY;
|
||||
+ break;
|
||||
+ default:
|
||||
+ val = ODROID_TFT35_MACTL_MX;
|
||||
+ break;
|
||||
+ }
|
||||
+ /* Memory Access Control */
|
||||
+ write_reg(par, 0x36, val | (par->bgr << 3));
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int fbtft_backlight_get_brightness(struct backlight_device *bd)
|
||||
+{
|
||||
+ return bd->props.brightness;
|
||||
+}
|
||||
+
|
||||
+static int fbtft_backlight_update_status(struct backlight_device *bd)
|
||||
+{
|
||||
+ struct fbtft_par *par = bl_get_data(bd);
|
||||
+ bool polarity = par->polarity;
|
||||
+
|
||||
+ fbtft_par_dbg(DEBUG_BACKLIGHT, par,
|
||||
+ "%s: polarity=%d, power=%d, fb_blank=%d\n",
|
||||
+ __func__, polarity, bd->props.power, bd->props.fb_blank);
|
||||
+
|
||||
+ if ((bd->props.power == FB_BLANK_UNBLANK) &&
|
||||
+ (bd->props.fb_blank == FB_BLANK_UNBLANK))
|
||||
+ gpiod_set_value(par->gpio.led[0], polarity);
|
||||
+ else
|
||||
+ gpiod_set_value(par->gpio.led[0], !polarity);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct backlight_ops fbtft_bl_ops = {
|
||||
+ .get_brightness = fbtft_backlight_get_brightness,
|
||||
+ .update_status = fbtft_backlight_update_status,
|
||||
+};
|
||||
+
|
||||
+static void register_backlight(struct fbtft_par *par)
|
||||
+{
|
||||
+ struct backlight_device *bd;
|
||||
+ struct backlight_properties bl_props = { 0, };
|
||||
+
|
||||
+ if (!par->gpio.led[0]) {
|
||||
+ fbtft_par_dbg(DEBUG_BACKLIGHT, par,
|
||||
+ "%s(): led pin not set, exiting.\n", __func__);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ bl_props.type = BACKLIGHT_RAW;
|
||||
+ /* Assume backlight is off, get polarity from current state of pin */
|
||||
+ bl_props.power = FB_BLANK_POWERDOWN;
|
||||
+
|
||||
+ /* Force polarity to true */
|
||||
+ par->polarity = true;
|
||||
+
|
||||
+ bd = backlight_device_register(dev_driver_string(par->info->device),
|
||||
+ par->info->device, par,
|
||||
+ &fbtft_bl_ops, &bl_props);
|
||||
+ if (IS_ERR(bd)) {
|
||||
+ dev_err(par->info->device,
|
||||
+ "cannot register backlight device (%ld)\n",
|
||||
+ PTR_ERR(bd));
|
||||
+ return;
|
||||
+ }
|
||||
+ par->info->bl_dev = bd;
|
||||
+
|
||||
+ if (!par->fbtftops.unregister_backlight)
|
||||
+ par->fbtftops.unregister_backlight = fbtft_unregister_backlight;
|
||||
+}
|
||||
+
|
||||
+static void unregister_backlight(struct fbtft_par *par)
|
||||
+{
|
||||
+ if (par->info->bl_dev) {
|
||||
+ par->info->bl_dev->props.power = FB_BLANK_POWERDOWN;
|
||||
+ backlight_update_status(par->info->bl_dev);
|
||||
+ backlight_device_unregister(par->info->bl_dev);
|
||||
+ par->info->bl_dev = NULL;
|
||||
+ }
|
||||
+
|
||||
+ /* Just to hook the remove routine */
|
||||
+ if (reg_gpx1) iounmap(reg_gpx1);
|
||||
+ if (reg_gpx2) iounmap(reg_gpx2);
|
||||
+ if (reg_gpa2) iounmap(reg_gpa2);
|
||||
+}
|
||||
+
|
||||
+static int verify_gpios(struct fbtft_par *par)
|
||||
+{
|
||||
+ struct fbtft_platform_data *pdata = par->pdata;
|
||||
+ int i;
|
||||
+
|
||||
+ fbtft_par_dbg(DEBUG_VERIFY_GPIOS, par, "%s()\n", __func__);
|
||||
+
|
||||
+ if (pdata->display.buswidth != 9 && par->startbyte == 0 &&
|
||||
+ !par->gpio.dc) {
|
||||
+ dev_err(par->info->device,
|
||||
+ "Missing info about 'dc' gpio. Aborting.\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (!par->pdev)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (!par->gpio.wr) {
|
||||
+ dev_err(par->info->device, "Missing 'wr' gpio. Aborting.\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ for (i = 0; i < pdata->display.buswidth; i++) {
|
||||
+ if (!par->gpio.db[i]) {
|
||||
+ dev_err(par->info->device,
|
||||
+ "Missing 'db%02d' gpio. Aborting.\n", i);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* Just to hook the probe routine */
|
||||
+ reg_gpx1 = ioremap(ODROIDXU3_GPX1_REG, 4);
|
||||
+ reg_gpx2 = ioremap(ODROIDXU3_GPX2_REG, 4);
|
||||
+ reg_gpa2 = ioremap(ODROIDXU3_GPA2_REG, 4);
|
||||
+ if ((reg_gpx1 == NULL) || (reg_gpx2 == NULL) || (reg_gpa2 == NULL)) {
|
||||
+ pr_err("%s : ioremap gpio registers error!\n", __func__);
|
||||
+ } else {
|
||||
+ pr_info("%s : ioremap gpio registers success!\n", __func__);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void reset(struct fbtft_par *par)
|
||||
+{
|
||||
+ if (!par->gpio.reset)
|
||||
+ return;
|
||||
+ fbtft_par_dbg(DEBUG_RESET, par, "%s()\n", __func__);
|
||||
+ gpiod_set_value_cansleep(par->gpio.reset, 0);
|
||||
+ usleep_range(20, 40);
|
||||
+ gpiod_set_value_cansleep(par->gpio.reset, 1);
|
||||
+ msleep(120);
|
||||
+}
|
||||
+
|
||||
+static int write(struct fbtft_par *par, void *buf, size_t len)
|
||||
+{
|
||||
+ u8 data;
|
||||
+ union reg_bitfield gpx1, gpx2, gpa2;
|
||||
+
|
||||
+ if ((reg_gpx1 == NULL) || (reg_gpx2 == NULL) || (reg_gpa2 == NULL)) {
|
||||
+ pr_err("%s : ioremap gpio register fail!\n", __func__);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
|
||||
+ "%s(len=%zu): ", __func__, len);
|
||||
+
|
||||
+ gpx1.wvalue = ioread32(reg_gpx1);
|
||||
+ gpx2.wvalue = ioread32(reg_gpx2);
|
||||
+ gpa2.wvalue = ioread32(reg_gpa2);
|
||||
+
|
||||
+ while (len--) {
|
||||
+ data = *(u8 *) buf;
|
||||
+ gpx1.bits.bit7 = (data & 0x01) ? 1 : 0;
|
||||
+ gpx2.bits.bit0 = (data & 0x02) ? 1 : 0;
|
||||
+ gpx1.bits.bit3 = (data & 0x04) ? 1 : 0;
|
||||
+ gpa2.bits.bit4 = (data & 0x08) ? 1 : 0;
|
||||
+ gpa2.bits.bit6 = (data & 0x10) ? 1 : 0;
|
||||
+ gpa2.bits.bit7 = (data & 0x20) ? 1 : 0;
|
||||
+ gpx1.bits.bit6 = (data & 0x40) ? 1 : 0;
|
||||
+ gpx1.bits.bit5 = (data & 0x80) ? 1 : 0;
|
||||
+ /* Start writing by pulling down /WR */
|
||||
+ gpa2.bits.bit5 = 0;
|
||||
+ iowrite32(gpx1.wvalue, reg_gpx1);
|
||||
+ iowrite32(gpx2.wvalue, reg_gpx2);
|
||||
+ iowrite32(gpa2.wvalue, reg_gpa2);
|
||||
+ gpa2.bits.bit5 = 1;
|
||||
+ iowrite32(gpa2.wvalue, reg_gpa2);
|
||||
+
|
||||
+ buf++;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct fbtft_display display = {
|
||||
+ .regwidth = 8,
|
||||
+ .buswidth = 8,
|
||||
+ .width = WIDTH,
|
||||
+ .height = HEIGHT,
|
||||
+ .init_sequence = default_init_sequence,
|
||||
+ .fbtftops = {
|
||||
+ .set_addr_win = set_addr_win,
|
||||
+ .set_var = set_var,
|
||||
+ .verify_gpios = verify_gpios,
|
||||
+ .register_backlight = register_backlight,
|
||||
+ .unregister_backlight = unregister_backlight,
|
||||
+ .reset = reset,
|
||||
+ .write = write,
|
||||
+ },
|
||||
+};
|
||||
+FBTFT_REGISTER_DRIVER(DRVNAME, "odroid,hktft35", &display);
|
||||
+
|
||||
+MODULE_ALIAS("platform:" DRVNAME);
|
||||
+MODULE_ALIAS("platform:hktft35");
|
||||
+
|
||||
+MODULE_DESCRIPTION("FB driver for the Hardkernel 3.5 inch TFT LCD uses the ILI9488 LCD Controller");
|
||||
+MODULE_AUTHOR("Yang Deokgyu");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,206 +0,0 @@
|
|||
From b0670da75362e10aac97c279cd4921d1dabec26b Mon Sep 17 00:00:00 2001
|
||||
From: Yang Deokgyu <secugyu@gmail.com>
|
||||
Date: Thu, 21 Nov 2019 15:17:36 +0900
|
||||
Subject: [PATCH 59/75] ODROID-XU4: drivers/fbtft: Add fb_hktft32 module for
|
||||
Hardkernel 3.2 inch TFT LCD
|
||||
|
||||
No longer use flexfb, fbtft_device that is deprecated since kernel 5.4.
|
||||
|
||||
Signed-off-by: Yang Deokgyu <secugyu@gmail.com>
|
||||
Change-Id: Iebd014360f90eab5210722102d54c6169be5e28e
|
||||
---
|
||||
drivers/staging/fbtft/Kconfig | 7 ++
|
||||
drivers/staging/fbtft/Makefile | 1 +
|
||||
drivers/staging/fbtft/fb_hktft32.c | 156 +++++++++++++++++++++++++++++
|
||||
3 files changed, 164 insertions(+)
|
||||
create mode 100644 drivers/staging/fbtft/fb_hktft32.c
|
||||
|
||||
diff --git a/drivers/staging/fbtft/Kconfig b/drivers/staging/fbtft/Kconfig
|
||||
index b6cd416ebb26..408ef1a2f978 100644
|
||||
--- a/drivers/staging/fbtft/Kconfig
|
||||
+++ b/drivers/staging/fbtft/Kconfig
|
||||
@@ -213,3 +213,10 @@ config FB_TFT_HKTFT35
|
||||
help
|
||||
Generic Framebuffer support for the Hardkernel 3.5 inch TFT LCD
|
||||
that uses the ILI9488 LCD Controller
|
||||
+
|
||||
+config FB_TFT_HKTFT32
|
||||
+ tristate "FB driver for the Hardkernel 3.2 inch TFT LCD"
|
||||
+ depends on FB_TFT
|
||||
+ help
|
||||
+ Generic Framebuffer support for the Hardkernel 3.2 inch TFT LCD
|
||||
+ that uses the ILI9340 LCD Controller
|
||||
diff --git a/drivers/staging/fbtft/Makefile b/drivers/staging/fbtft/Makefile
|
||||
index 3d41175663ed..34a5a14d1ab4 100644
|
||||
--- a/drivers/staging/fbtft/Makefile
|
||||
+++ b/drivers/staging/fbtft/Makefile
|
||||
@@ -38,3 +38,4 @@ obj-$(CONFIG_FB_TFT_UC1701) += fb_uc1701.o
|
||||
obj-$(CONFIG_FB_TFT_UPD161704) += fb_upd161704.o
|
||||
obj-$(CONFIG_FB_TFT_WATTEROTT) += fb_watterott.o
|
||||
obj-$(CONFIG_FB_TFT_HKTFT35) += fb_hktft35.o
|
||||
+obj-$(CONFIG_FB_TFT_HKTFT32) += fb_hktft32.o
|
||||
diff --git a/drivers/staging/fbtft/fb_hktft32.c b/drivers/staging/fbtft/fb_hktft32.c
|
||||
new file mode 100644
|
||||
index 000000000000..33ac19603cad
|
||||
--- /dev/null
|
||||
+++ b/drivers/staging/fbtft/fb_hktft32.c
|
||||
@@ -0,0 +1,156 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * FB driver for the Hardkernel 3.2 inch TFT LCD
|
||||
+ * that uses the ILI9340 LCD Controller
|
||||
+ *
|
||||
+ * Copyright (C) 2019 Yang Deokgyu
|
||||
+ *
|
||||
+ * Based on fb_ili9340.c by Noralf Tronnes
|
||||
+ */
|
||||
+
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/gpio/consumer.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <video/mipi_display.h>
|
||||
+
|
||||
+#include "fbtft.h"
|
||||
+
|
||||
+#define DRVNAME "fb_hktft32"
|
||||
+#define WIDTH 240
|
||||
+#define HEIGHT 320
|
||||
+
|
||||
+/* Init sequence taken from: Arduino Library for the Adafruit 2.2" display */
|
||||
+static int init_display(struct fbtft_par *par)
|
||||
+{
|
||||
+ par->fbtftops.reset(par);
|
||||
+
|
||||
+ write_reg(par, 0xEF, 0x03, 0x80, 0x02);
|
||||
+ write_reg(par, 0xCF, 0x00, 0XC1, 0X30);
|
||||
+ write_reg(par, 0xED, 0x64, 0x03, 0X12, 0X81);
|
||||
+ write_reg(par, 0xE8, 0x85, 0x00, 0x78);
|
||||
+ write_reg(par, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02);
|
||||
+ write_reg(par, 0xF7, 0x20);
|
||||
+ write_reg(par, 0xEA, 0x00, 0x00);
|
||||
+
|
||||
+ /* Power Control 1 */
|
||||
+ write_reg(par, 0xC0, 0x23);
|
||||
+
|
||||
+ /* Power Control 2 */
|
||||
+ write_reg(par, 0xC1, 0x10);
|
||||
+
|
||||
+ /* VCOM Control 1 */
|
||||
+ write_reg(par, 0xC5, 0x3e, 0x28);
|
||||
+
|
||||
+ /* VCOM Control 2 */
|
||||
+ write_reg(par, 0xC7, 0x86);
|
||||
+
|
||||
+ /* COLMOD: Pixel Format Set */
|
||||
+ /* 16 bits/pixel */
|
||||
+ write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, 0x55);
|
||||
+
|
||||
+ /* Frame Rate Control */
|
||||
+ /* Division ratio = fosc, Frame Rate = 79Hz */
|
||||
+ write_reg(par, 0xB1, 0x00, 0x18);
|
||||
+
|
||||
+ /* Display Function Control */
|
||||
+ write_reg(par, 0xB6, 0x08, 0x82, 0x27);
|
||||
+
|
||||
+ /* Gamma Function Disable */
|
||||
+ write_reg(par, 0xF2, 0x00);
|
||||
+
|
||||
+ /* Gamma curve selection */
|
||||
+ write_reg(par, MIPI_DCS_SET_GAMMA_CURVE, 0x01);
|
||||
+
|
||||
+ /* Positive Gamma Correction */
|
||||
+ write_reg(par, 0xE0,
|
||||
+ 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, 0x4E, 0xF1,
|
||||
+ 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00);
|
||||
+
|
||||
+ /* Negative Gamma Correction */
|
||||
+ write_reg(par, 0xE1,
|
||||
+ 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, 0x31, 0xC1,
|
||||
+ 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F);
|
||||
+
|
||||
+ write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
|
||||
+
|
||||
+ mdelay(120);
|
||||
+
|
||||
+ write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
|
||||
+{
|
||||
+ write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
|
||||
+ xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
|
||||
+
|
||||
+ write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
|
||||
+ ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
|
||||
+
|
||||
+ write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
|
||||
+}
|
||||
+
|
||||
+#define ILI9340_MADCTL_MV 0x20
|
||||
+#define ILI9340_MADCTL_MX 0x40
|
||||
+#define ILI9340_MADCTL_MY 0x80
|
||||
+static int set_var(struct fbtft_par *par)
|
||||
+{
|
||||
+ u8 val;
|
||||
+
|
||||
+ switch (par->info->var.rotate) {
|
||||
+ case 270:
|
||||
+ val = ILI9340_MADCTL_MV;
|
||||
+ break;
|
||||
+ case 180:
|
||||
+ val = ILI9340_MADCTL_MY;
|
||||
+ break;
|
||||
+ case 90:
|
||||
+ val = ILI9340_MADCTL_MV | ILI9340_MADCTL_MY | ILI9340_MADCTL_MX;
|
||||
+ break;
|
||||
+ default:
|
||||
+ val = ILI9340_MADCTL_MX;
|
||||
+ break;
|
||||
+ }
|
||||
+ /* Memory Access Control */
|
||||
+ write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, val | (par->bgr << 3));
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void reset(struct fbtft_par *par)
|
||||
+{
|
||||
+ if (!par->gpio.reset)
|
||||
+ return;
|
||||
+ fbtft_par_dbg(DEBUG_RESET, par, "%s()\n", __func__);
|
||||
+ gpiod_set_value_cansleep(par->gpio.reset, 0);
|
||||
+ usleep_range(20, 40);
|
||||
+ gpiod_set_value_cansleep(par->gpio.reset, 1);
|
||||
+ msleep(120);
|
||||
+}
|
||||
+
|
||||
+static struct fbtft_display display = {
|
||||
+ .regwidth = 8,
|
||||
+ .buswidth = 8,
|
||||
+ .width = WIDTH,
|
||||
+ .height = HEIGHT,
|
||||
+ .fbtftops = {
|
||||
+ .init_display = init_display,
|
||||
+ .set_addr_win = set_addr_win,
|
||||
+ .set_var = set_var,
|
||||
+ .reset = reset,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+FBTFT_REGISTER_DRIVER(DRVNAME, "odroid,hktft32", &display);
|
||||
+
|
||||
+MODULE_ALIAS("spi:" DRVNAME);
|
||||
+MODULE_ALIAS("platform:" DRVNAME);
|
||||
+MODULE_ALIAS("spi:hktft32");
|
||||
+MODULE_ALIAS("platform:hktft32");
|
||||
+
|
||||
+MODULE_DESCRIPTION("FB driver for the Hardkernel 3.2 inch TFT LCD uses the ILI9340 LCD Controller");
|
||||
+MODULE_AUTHOR("Yang Deokgyu");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,134 +0,0 @@
|
|||
From 162be51d321a70125720c21eccad288ff6abada3 Mon Sep 17 00:00:00 2001
|
||||
From: Yang Deokgyu <secugyu@gmail.com>
|
||||
Date: Thu, 5 Dec 2019 12:08:23 +0900
|
||||
Subject: [PATCH 61/75] ODROID-XU4: dts: Add nodes for Hardkernel LCDs of 2
|
||||
HATs, Cloudshell, OGST
|
||||
|
||||
It doesn't include its touchscreen yet.
|
||||
|
||||
Signed-off-by: Yang Deokgyu <secugyu@gmail.com>
|
||||
Change-Id: I110e897746dea17fc32e9fdc442c492d70888dfa
|
||||
---
|
||||
arch/arm/boot/dts/exynos5422-odroidxu4.dts | 101 +++++++++++++++++++++
|
||||
1 file changed, 101 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
index 3d68fca093ee..89a07073712f 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
@@ -44,6 +44,49 @@ codec {
|
||||
sound-dai = <&hdmi>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ hktft35: hktft35 {
|
||||
+ status = "disabled";
|
||||
+ compatible = "odroid,hktft35";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hktft35_pins>;
|
||||
+
|
||||
+ rotate = <270>;
|
||||
+ bgr;
|
||||
+ fps = <20>;
|
||||
+ bpp = <16>;
|
||||
+ reset-gpios = <&gpa0 3 GPIO_ACTIVE_HIGH>;
|
||||
+ dc-gpios = <&gpx2 4 GPIO_ACTIVE_HIGH>;
|
||||
+ wr-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
+ cs-gpios = <&gpa0 2 GPIO_ACTIVE_HIGH>;
|
||||
+ led-gpios = <&gpx2 7 GPIO_ACTIVE_HIGH>;
|
||||
+ db-gpios = <&gpx1 7 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpx2 0 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpx1 3 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpa2 4 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpa2 6 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpa2 7 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpx1 6 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpx1 5 GPIO_ACTIVE_HIGH>;
|
||||
+ debug = <0>;
|
||||
+
|
||||
+ hktft35_pins: hktft35_pins {
|
||||
+ samsung,pins = "gpa0-3", /* reset */
|
||||
+ "gpx2-4", /* dc */
|
||||
+ "gpa2-5", /* wr */
|
||||
+ "gpa0-2", /* cs */
|
||||
+ "gpx2-7", /* led */
|
||||
+ "gpx1-7", /* db00 */
|
||||
+ "gpx2-0", /* db01 */
|
||||
+ "gpx1-3", /* db02 */
|
||||
+ "gpa2-4", /* db03 */
|
||||
+ "gpa2-6", /* db04 */
|
||||
+ "gpa2-7", /* db05 */
|
||||
+ "gpx1-6", /* db06 */
|
||||
+ "gpx1-5"; /* db07 */
|
||||
+ samsung,pin-function = <1>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&i2s0 {
|
||||
@@ -122,4 +165,62 @@ controller-data {
|
||||
samsung,spi-feedback-delay = <0>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ hktft_cs_ogst: hktft_cs_ogst@0 {
|
||||
+ status = "disabled";
|
||||
+ compatible = "odroid,hktft32";
|
||||
+ reg = <0>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hktft_cs_ogst_pins>;
|
||||
+
|
||||
+ spi-max-frequency = <40000000>;
|
||||
+ rotate = <270>;
|
||||
+ bgr;
|
||||
+ backlight;
|
||||
+ fps = <20>;
|
||||
+ bpp = <16>;
|
||||
+ reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
|
||||
+ dc-gpios = <&gpx1 6 GPIO_ACTIVE_HIGH>;
|
||||
+ led-gpios = <&gpx1 2 GPIO_ACTIVE_HIGH>;
|
||||
+ debug = <0>;
|
||||
+
|
||||
+ hktft_cs_ogst_pins: hktft_cs_ogst_pins {
|
||||
+ samsung,pins = "gpx1-5", /* reset */
|
||||
+ "gpx1-6", /* dc */
|
||||
+ "gpx1-2"; /* led */
|
||||
+ };
|
||||
+
|
||||
+ controller-data {
|
||||
+ cs-gpio = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
+ samsung,spi-feedback-delay = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ hktft32: hktft32@0 {
|
||||
+ status = "disabled";
|
||||
+ compatible = "odroid,hktft32";
|
||||
+ reg = <0>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hktft32_pins>;
|
||||
+
|
||||
+ spi-max-frequency = <40000000>;
|
||||
+ rotate = <90>;
|
||||
+ bgr;
|
||||
+ backlight;
|
||||
+ fps = <20>;
|
||||
+ bpp = <16>;
|
||||
+ reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
|
||||
+ dc-gpios = <&gpx1 6 GPIO_ACTIVE_HIGH>;
|
||||
+ debug = <0>;
|
||||
+
|
||||
+ hktft32_pins: hktft32_pins {
|
||||
+ samsung,pins = "gpx1-5", /* reset */
|
||||
+ "gpx1-6"; /* dc */
|
||||
+ };
|
||||
+
|
||||
+ controller-data {
|
||||
+ cs-gpio = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
+ samsung,spi-feedback-delay = <0>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
From 5518b6282813b73d36bc902a76abf5b0327e4bd7 Mon Sep 17 00:00:00 2001
|
||||
From: Dongjin Kim <tobetter@gmail.com>
|
||||
Date: Thu, 27 Feb 2020 11:50:05 +0900
|
||||
Subject: [PATCH 62/75] ODROID-XU4: FIXME: Revert "regulator: core: Let boot-on
|
||||
regulators be powered off"
|
||||
|
||||
FIXME: this patch crashes when Mali is activated
|
||||
|
||||
This reverts commit f44b07472f29ae313ce875dc7b9c75b100c608b8.
|
||||
|
||||
Change-Id: I2f3e8e68b3172c2c1d035032b47fb256c5757be8
|
||||
---
|
||||
drivers/regulator/core.c | 4 +---
|
||||
1 file changed, 1 insertion(+), 3 deletions(-)
|
||||
|
||||
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
|
||||
index a4ffd71696da..a442aa5bdfa3 100644
|
||||
--- a/drivers/regulator/core.c
|
||||
+++ b/drivers/regulator/core.c
|
||||
@@ -1447,9 +1447,7 @@ static int set_machine_constraints(struct regulator_dev *rdev,
|
||||
rdev_err(rdev, "failed to enable: %pe\n", ERR_PTR(ret));
|
||||
return ret;
|
||||
}
|
||||
-
|
||||
- if (rdev->constraints->always_on)
|
||||
- rdev->use_count++;
|
||||
+ rdev->use_count++;
|
||||
}
|
||||
|
||||
print_constraints(rdev);
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
From 6207fe989382f1eedda21594a48ac550a866a946 Mon Sep 17 00:00:00 2001
|
||||
From: ckkim <changkon12@gmail.com>
|
||||
Date: Thu, 5 Mar 2020 14:26:42 +0900
|
||||
Subject: [PATCH 63/75] ODROID-XU4: arm/dts: remove write-protect pin from SD
|
||||
card
|
||||
|
||||
This patch removes the write-protect pin from SD card since it's not
|
||||
being supported by a hardware and used at all.
|
||||
|
||||
Signed-off-by: ckkim <changkon12@gmail.com>
|
||||
Change-Id: I72af94f7fd0a01e65f7ca3e15ccd66e797395df4
|
||||
---
|
||||
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
index 7f2f53843435..deb907d1f523 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
@@ -970,9 +970,10 @@ &mmc_2 {
|
||||
samsung,dw-mshc-sdr-timing = <0 4>;
|
||||
samsung,dw-mshc-ddr-timing = <0 2>;
|
||||
pinctrl-names = "default";
|
||||
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
|
||||
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
max-frequency = <200000000>;
|
||||
vmmc-supply = <&ldo19_reg>;
|
||||
vqmmc-supply = <&ldo13_reg>;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
From f8c04d054d07a020103d454607c5c9d8f06894b8 Mon Sep 17 00:00:00 2001
|
||||
From: "charles.park" <charles.park@hardkernel.com>
|
||||
Date: Fri, 1 Jun 2018 18:12:01 +0900
|
||||
Subject: [PATCH 64/75] ODROID-XU4: Update hack avoiding the invalid
|
||||
temperature by TMU broken
|
||||
|
||||
Change-Id: I6092834427950a50746535458e99bf7089212044
|
||||
---
|
||||
drivers/thermal/thermal_helpers.c | 28 ++++++++++++++++++++++++++++
|
||||
1 file changed, 28 insertions(+)
|
||||
|
||||
diff --git a/drivers/thermal/thermal_helpers.c b/drivers/thermal/thermal_helpers.c
|
||||
index c94bc824e5d3..2880126c5861 100644
|
||||
--- a/drivers/thermal/thermal_helpers.c
|
||||
+++ b/drivers/thermal/thermal_helpers.c
|
||||
@@ -75,6 +75,10 @@ EXPORT_SYMBOL(get_thermal_instance);
|
||||
*
|
||||
* Return: On success returns 0, an error code otherwise
|
||||
*/
|
||||
+
|
||||
+#define CRITICAL_TEMP 120000
|
||||
+int thermal_zone_data[4] = { 0, };
|
||||
+
|
||||
int thermal_zone_get_temp(struct thermal_zone_device *tz, int *temp)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
@@ -108,6 +112,30 @@ int thermal_zone_get_temp(struct thermal_zone_device *tz, int *temp)
|
||||
*temp = tz->emul_temperature;
|
||||
}
|
||||
|
||||
+ /* save thermal_zone data */
|
||||
+ if (!ret)
|
||||
+ thermal_zone_data[tz->id] = *temp;
|
||||
+ /*
|
||||
+ * This case is that the thermal sensor is broken.
|
||||
+ * That's not real temperature. Set the fake temperature value in order to
|
||||
+ * avoid reaching the ciritical temperature.
|
||||
+ */
|
||||
+ if ((thermal_zone_data[tz->id] > CRITICAL_TEMP) && (tz->id != 4)) {
|
||||
+ int i, broken_sensor = 0, correct_temp = 0;
|
||||
+ for (i = 0; i < 4; i++) {
|
||||
+ if ((thermal_zone_data[i] <= CRITICAL_TEMP) &&
|
||||
+ (correct_temp <= thermal_zone_data[i]))
|
||||
+ correct_temp = thermal_zone_data[i];
|
||||
+ if (thermal_zone_data[i] > CRITICAL_TEMP)
|
||||
+ broken_sensor++;
|
||||
+ }
|
||||
+ /*
|
||||
+ * if all thermal sensor broken then critical temperature data send
|
||||
+ * for system poweroff.
|
||||
+ */
|
||||
+ *temp = (broken_sensor == 4) ? CRITICAL_TEMP : correct_temp;
|
||||
+ }
|
||||
+
|
||||
mutex_unlock(&tz->lock);
|
||||
exit:
|
||||
return ret;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
From 9b902c22193ac034428213bc8bed060c0d076c01 Mon Sep 17 00:00:00 2001
|
||||
From: Marian Mihailescu <mihailescu2m@gmail.com>
|
||||
Date: Thu, 14 Nov 2019 10:39:00 +1030
|
||||
Subject: [PATCH 65/75] ODROID-XU4: ARM: dts: exynos5420: add mali dt node and
|
||||
enable mali on Odroid XU3/4
|
||||
|
||||
Add device tree node for Mali GPU for Exynos 542x SoC.
|
||||
GPU is disabled by default, and is enabled for each board after the
|
||||
regulator is defined. Tested on Odroid-XU4.
|
||||
|
||||
Change-Id: I902932d29c7093b666fa3a8a8e1d0fda8fb11d5c
|
||||
Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
index deb907d1f523..c9283ba25fab 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
|
||||
@@ -1053,6 +1053,11 @@ &gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&gpu {
|
||||
+ mali-supply = <&buck4_reg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&rtc {
|
||||
status = "okay";
|
||||
clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,381 +0,0 @@
|
|||
From b4b51b2f34e9e8fd1d011e8acebb45d13ca2f56f Mon Sep 17 00:00:00 2001
|
||||
From: Yang Deokgyu <secugyu@gmail.com>
|
||||
Date: Thu, 5 Dec 2019 18:07:13 +0900
|
||||
Subject: [PATCH 66/75] ODROID-XU4: Introduce device tree overlay
|
||||
|
||||
Copy *.dtbo files at arch/arm/boot/dts/overlays to boot
|
||||
partition, e.g, /media/boot/overlays/. Then use "fdtoverlay" tool
|
||||
to integrate DTB and DTBOs. Or, you also can use "fdt apply" u-boot
|
||||
command to prepare device tree blob at booting time.
|
||||
|
||||
Signed-off-by: Yang Deokgyu <secugyu@gmail.com>
|
||||
Change-Id: I40e6a915e2149952fb548f64e7fae335ba12db18
|
||||
---
|
||||
.gitignore | 1 +
|
||||
Makefile | 3 ++
|
||||
arch/arm/boot/dts/Makefile | 4 +++
|
||||
arch/arm/boot/dts/exynos5422-odroidxu4.dts | 8 ++---
|
||||
arch/arm/boot/dts/overlays/Makefile | 12 +++++++
|
||||
.../dts/overlays/hktft-cs-ogst-overlay.dts | 36 +++++++++++++++++++
|
||||
.../arm/boot/dts/overlays/hktft32-overlay.dts | 36 +++++++++++++++++++
|
||||
.../arm/boot/dts/overlays/hktft35-overlay.dts | 36 +++++++++++++++++++
|
||||
arch/arm/boot/dts/overlays/i2c1-overlay.dts | 12 +++++++
|
||||
arch/arm/boot/dts/overlays/i2c5-overlay.dts | 12 +++++++
|
||||
.../arm/boot/dts/overlays/spidev1-overlay.dts | 20 +++++++++++
|
||||
scripts/Makefile.dtbinst | 6 +++-
|
||||
scripts/Makefile.lib | 16 ++++++++-
|
||||
13 files changed, 196 insertions(+), 6 deletions(-)
|
||||
create mode 100644 arch/arm/boot/dts/overlays/Makefile
|
||||
create mode 100644 arch/arm/boot/dts/overlays/hktft-cs-ogst-overlay.dts
|
||||
create mode 100644 arch/arm/boot/dts/overlays/hktft32-overlay.dts
|
||||
create mode 100644 arch/arm/boot/dts/overlays/hktft35-overlay.dts
|
||||
create mode 100644 arch/arm/boot/dts/overlays/i2c1-overlay.dts
|
||||
create mode 100644 arch/arm/boot/dts/overlays/i2c5-overlay.dts
|
||||
create mode 100644 arch/arm/boot/dts/overlays/spidev1-overlay.dts
|
||||
|
||||
diff --git a/.gitignore b/.gitignore
|
||||
index d01cda8e1177..bb65fa253e58 100644
|
||||
--- a/.gitignore
|
||||
+++ b/.gitignore
|
||||
@@ -18,6 +18,7 @@
|
||||
*.c.[012]*.*
|
||||
*.dt.yaml
|
||||
*.dtb
|
||||
+*.dtbo
|
||||
*.dtb.S
|
||||
*.dwo
|
||||
*.elf
|
||||
diff --git a/Makefile b/Makefile
|
||||
index 9e7fd6a065a7..b09a05a2f97c 100644
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -1331,6 +1331,9 @@ ifneq ($(dtstree),)
|
||||
%.dtb: include/config/kernel.release scripts_dtc
|
||||
$(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@
|
||||
|
||||
+%.dtbo:
|
||||
+ $(Q)$(MAKE) $(build)=$(dtstree)/overlays $(dtstree)/overlays/$@
|
||||
+
|
||||
PHONY += dtbs dtbs_install dtbs_check
|
||||
dtbs: include/config/kernel.release scripts_dtc
|
||||
$(Q)$(MAKE) $(build)=$(dtstree)
|
||||
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
|
||||
index ce66ffd5a1bb..d7c6b3bea288 100644
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -1408,3 +1408,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
|
||||
aspeed-bmc-opp-zaius.dtb \
|
||||
aspeed-bmc-portwell-neptune.dtb \
|
||||
aspeed-bmc-quanta-q71l.dtb
|
||||
+
|
||||
+targets += $(dtb-y)
|
||||
+
|
||||
+subdir-y := overlays
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
index 89a07073712f..be8e6d2f1394 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
@@ -137,25 +137,25 @@ &usbdrd_dwc3_1 {
|
||||
|
||||
/* i2c@12C70000 */
|
||||
&i2c_1 {
|
||||
- status = "okay";
|
||||
+ status = "disabled";
|
||||
samsung,i2c-max-bus-freq = <400000>;
|
||||
};
|
||||
|
||||
/* i2c@12cb0000 */
|
||||
&hsi2c_5 {
|
||||
- status = "okay";
|
||||
+ status = "disabled";
|
||||
samsung,hs-mode;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&spi_1 {
|
||||
- status = "okay";
|
||||
+ status = "disabled";
|
||||
samsung,spi-src-clk = <0>;
|
||||
num-cs = <2>;
|
||||
cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>, <&gpx2 1 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
spidev: spidev@0 {
|
||||
- status = "okay";
|
||||
+ status = "disabled";
|
||||
reg = <0>;
|
||||
compatible = "odroid,spidev";
|
||||
spi-max-frequency = <1000000>;
|
||||
diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile
|
||||
new file mode 100644
|
||||
index 000000000000..9502f67ce928
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/Makefile
|
||||
@@ -0,0 +1,12 @@
|
||||
+# Overlays for the Odroid platform
|
||||
+
|
||||
+dtbo-y += \
|
||||
+ spidev1-overlay.dtbo \
|
||||
+ i2c1-overlay.dtbo \
|
||||
+ i2c5-overlay.dtbo \
|
||||
+ hktft32-overlay.dtbo \
|
||||
+ hktft35-overlay.dtbo \
|
||||
+ hktft-cs-ogst-overlay.dtbo
|
||||
+
|
||||
+targets += $(dtbo-y)
|
||||
+always := $(dtbo-y)
|
||||
diff --git a/arch/arm/boot/dts/overlays/hktft-cs-ogst-overlay.dts b/arch/arm/boot/dts/overlays/hktft-cs-ogst-overlay.dts
|
||||
new file mode 100644
|
||||
index 000000000000..a727fb311574
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/hktft-cs-ogst-overlay.dts
|
||||
@@ -0,0 +1,36 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ target = <&i2c_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@1 {
|
||||
+ target = <&hsi2c_5>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@2 {
|
||||
+ target = <&spi_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@3 {
|
||||
+ target = <&hktft_cs_ogst>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/overlays/hktft32-overlay.dts b/arch/arm/boot/dts/overlays/hktft32-overlay.dts
|
||||
new file mode 100644
|
||||
index 000000000000..7bda6cd8e6d8
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/hktft32-overlay.dts
|
||||
@@ -0,0 +1,36 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ target = <&i2c_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@1 {
|
||||
+ target = <&hsi2c_5>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@2 {
|
||||
+ target = <&spi_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@3 {
|
||||
+ target = <&hktft32>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/overlays/hktft35-overlay.dts b/arch/arm/boot/dts/overlays/hktft35-overlay.dts
|
||||
new file mode 100644
|
||||
index 000000000000..a656dd272165
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/hktft35-overlay.dts
|
||||
@@ -0,0 +1,36 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ target = <&i2c_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@1 {
|
||||
+ target = <&hsi2c_5>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@2 {
|
||||
+ target = <&spi_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@3 {
|
||||
+ target = <&hktft35>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/overlays/i2c1-overlay.dts b/arch/arm/boot/dts/overlays/i2c1-overlay.dts
|
||||
new file mode 100644
|
||||
index 000000000000..2fd27754e7c8
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/i2c1-overlay.dts
|
||||
@@ -0,0 +1,12 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ target = <&i2c_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/overlays/i2c5-overlay.dts b/arch/arm/boot/dts/overlays/i2c5-overlay.dts
|
||||
new file mode 100644
|
||||
index 000000000000..9ef9e66699e0
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/i2c5-overlay.dts
|
||||
@@ -0,0 +1,12 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ target = <&hsi2c_5>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/overlays/spidev1-overlay.dts b/arch/arm/boot/dts/overlays/spidev1-overlay.dts
|
||||
new file mode 100644
|
||||
index 000000000000..c5cb6bcb6011
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/spidev1-overlay.dts
|
||||
@@ -0,0 +1,20 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ target = <&spi_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@1 {
|
||||
+ target = <&spidev>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
|
||||
index 50d580d77ae9..079b83308011 100644
|
||||
--- a/scripts/Makefile.dtbinst
|
||||
+++ b/scripts/Makefile.dtbinst
|
||||
@@ -18,9 +18,10 @@ include scripts/Kbuild.include
|
||||
include $(src)/Makefile
|
||||
|
||||
dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-)))
|
||||
+dtbos := $(addprefix $(dst)/, $(dtbo-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-)))
|
||||
subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m))
|
||||
|
||||
-__dtbs_install: $(dtbs) $(subdirs)
|
||||
+__dtbs_install: $(dtbs) $(dtbos) $(subdirs)
|
||||
@:
|
||||
|
||||
quiet_cmd_dtb_install = INSTALL $@
|
||||
@@ -29,6 +30,9 @@ quiet_cmd_dtb_install = INSTALL $@
|
||||
$(dst)/%.dtb: $(obj)/%.dtb
|
||||
$(call cmd,dtb_install)
|
||||
|
||||
+$(dst)/%.dtbo: $(obj)/%.dtbo
|
||||
+ $(call cmd,dtb_install)
|
||||
+
|
||||
PHONY += $(subdirs)
|
||||
$(subdirs):
|
||||
$(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@)
|
||||
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
|
||||
index 94133708889d..3ee04939ab8d 100644
|
||||
--- a/scripts/Makefile.lib
|
||||
+++ b/scripts/Makefile.lib
|
||||
@@ -281,12 +281,14 @@ DTC_FLAGS += -Wno-interrupt_provider
|
||||
ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),)
|
||||
DTC_FLAGS += -Wno-unit_address_vs_reg \
|
||||
-Wno-unit_address_format \
|
||||
+ -Wno-gpios_property \
|
||||
-Wno-avoid_unnecessary_addr_size \
|
||||
-Wno-alias_paths \
|
||||
-Wno-graph_child_address \
|
||||
-Wno-simple_bus_reg \
|
||||
-Wno-unique_unit_address \
|
||||
- -Wno-pci_device_reg
|
||||
+ -Wno-pci_device_reg \
|
||||
+ --symbol
|
||||
endif
|
||||
|
||||
ifneq ($(findstring 2,$(KBUILD_EXTRA_WARN)),)
|
||||
@@ -341,6 +343,18 @@ endef
|
||||
$(obj)/%.dt.yaml: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE
|
||||
$(call if_changed_rule,dtc,yaml)
|
||||
|
||||
+quiet_cmd_dtco = DTCO $@
|
||||
+cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
|
||||
+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
|
||||
+ $(DTC) -@ -H epapr -O dtb -o $@ -b 0 \
|
||||
+ -i $(dir $<) $(DTC_FLAGS) \
|
||||
+ -Wno-interrupts_property \
|
||||
+ -d $(depfile).dtc.tmp $(dtc-tmp) ; \
|
||||
+ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
|
||||
+
|
||||
+$(obj)/%.dtbo: $(obj)/%.dts FORCE
|
||||
+ $(call if_changed_dep,dtco)
|
||||
+
|
||||
dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
|
||||
|
||||
# Bzip2
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1,754 +0,0 @@
|
|||
From 541b8b1532b852f9c38227564f11a0b67f91ff20 Mon Sep 17 00:00:00 2001
|
||||
From: Deokgyu Yang <secugyu@gmail.com>
|
||||
Date: Thu, 28 May 2020 18:50:32 +0900
|
||||
Subject: [PATCH 67/75] ODROID-XU4: arm/dts: Refactoring device tree overlay
|
||||
structure
|
||||
|
||||
Signed-off-by: Deokgyu Yang <secugyu@gmail.com>
|
||||
Change-Id: Ied2c7fa25d464a7aa24f92bcaa5baa4a67d636f0
|
||||
---
|
||||
.../boot/dts/exynos5422-odroidxu3-common.dtsi | 14 ++
|
||||
arch/arm/boot/dts/exynos5422-odroidxu4.dts | 130 +++---------------
|
||||
arch/arm/boot/dts/overlays/Makefile | 15 +-
|
||||
arch/arm/boot/dts/overlays/ads7846.dts | 58 ++++++++
|
||||
.../dts/overlays/hktft-cs-ogst-overlay.dts | 36 -----
|
||||
arch/arm/boot/dts/overlays/hktft-cs-ogst.dts | 48 +++++++
|
||||
.../arm/boot/dts/overlays/hktft32-overlay.dts | 36 -----
|
||||
arch/arm/boot/dts/overlays/hktft32.dts | 46 +++++++
|
||||
.../arm/boot/dts/overlays/hktft35-overlay.dts | 36 -----
|
||||
arch/arm/boot/dts/overlays/hktft35.dts | 55 ++++++++
|
||||
.../overlays/{i2c1-overlay.dts => i2c0.dts} | 1 +
|
||||
.../overlays/{i2c5-overlay.dts => i2c1.dts} | 1 +
|
||||
arch/arm/boot/dts/overlays/spi0.dts | 30 ++++
|
||||
.../arm/boot/dts/overlays/spidev1-overlay.dts | 20 ---
|
||||
arch/arm/boot/dts/overlays/sx865x-i2c1.dts | 34 +++++
|
||||
arch/arm/boot/dts/overlays/uart0.dts | 12 ++
|
||||
16 files changed, 325 insertions(+), 247 deletions(-)
|
||||
create mode 100644 arch/arm/boot/dts/overlays/ads7846.dts
|
||||
delete mode 100644 arch/arm/boot/dts/overlays/hktft-cs-ogst-overlay.dts
|
||||
create mode 100644 arch/arm/boot/dts/overlays/hktft-cs-ogst.dts
|
||||
delete mode 100644 arch/arm/boot/dts/overlays/hktft32-overlay.dts
|
||||
create mode 100644 arch/arm/boot/dts/overlays/hktft32.dts
|
||||
delete mode 100644 arch/arm/boot/dts/overlays/hktft35-overlay.dts
|
||||
create mode 100644 arch/arm/boot/dts/overlays/hktft35.dts
|
||||
rename arch/arm/boot/dts/overlays/{i2c1-overlay.dts => i2c0.dts} (78%)
|
||||
rename arch/arm/boot/dts/overlays/{i2c5-overlay.dts => i2c1.dts} (78%)
|
||||
create mode 100644 arch/arm/boot/dts/overlays/spi0.dts
|
||||
delete mode 100644 arch/arm/boot/dts/overlays/spidev1-overlay.dts
|
||||
create mode 100644 arch/arm/boot/dts/overlays/sx865x-i2c1.dts
|
||||
create mode 100644 arch/arm/boot/dts/overlays/uart0.dts
|
||||
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
|
||||
index ad8c85d1b7ae..72de20d5ca4c 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
|
||||
@@ -13,6 +13,20 @@
|
||||
#include "exynos5422-odroid-core.dtsi"
|
||||
|
||||
/ {
|
||||
+ aliases {
|
||||
+ /* Hardkernel alignment
|
||||
+ * I2C_0 : Pin 3, 5
|
||||
+ * I2C_1 : Pin 27, 28
|
||||
+ * SPI_0 : Pin 11, 13, 15
|
||||
+ * SERIAL_0 : Pin 8, 10
|
||||
+ */
|
||||
+ i2c0 = &i2c_1;
|
||||
+ i2c1 = &hsi2c_5;
|
||||
+ i2c5 = &i2c_0;
|
||||
+ spi0 = &spi_1;
|
||||
+ spi1 = &spi_0;
|
||||
+ };
|
||||
+
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
index be8e6d2f1394..55ebc4350303 100644
|
||||
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
|
||||
@@ -44,49 +44,6 @@ codec {
|
||||
sound-dai = <&hdmi>;
|
||||
};
|
||||
};
|
||||
-
|
||||
- hktft35: hktft35 {
|
||||
- status = "disabled";
|
||||
- compatible = "odroid,hktft35";
|
||||
- pinctrl-names = "default";
|
||||
- pinctrl-0 = <&hktft35_pins>;
|
||||
-
|
||||
- rotate = <270>;
|
||||
- bgr;
|
||||
- fps = <20>;
|
||||
- bpp = <16>;
|
||||
- reset-gpios = <&gpa0 3 GPIO_ACTIVE_HIGH>;
|
||||
- dc-gpios = <&gpx2 4 GPIO_ACTIVE_HIGH>;
|
||||
- wr-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
- cs-gpios = <&gpa0 2 GPIO_ACTIVE_HIGH>;
|
||||
- led-gpios = <&gpx2 7 GPIO_ACTIVE_HIGH>;
|
||||
- db-gpios = <&gpx1 7 GPIO_ACTIVE_HIGH>,
|
||||
- <&gpx2 0 GPIO_ACTIVE_HIGH>,
|
||||
- <&gpx1 3 GPIO_ACTIVE_HIGH>,
|
||||
- <&gpa2 4 GPIO_ACTIVE_HIGH>,
|
||||
- <&gpa2 6 GPIO_ACTIVE_HIGH>,
|
||||
- <&gpa2 7 GPIO_ACTIVE_HIGH>,
|
||||
- <&gpx1 6 GPIO_ACTIVE_HIGH>,
|
||||
- <&gpx1 5 GPIO_ACTIVE_HIGH>;
|
||||
- debug = <0>;
|
||||
-
|
||||
- hktft35_pins: hktft35_pins {
|
||||
- samsung,pins = "gpa0-3", /* reset */
|
||||
- "gpx2-4", /* dc */
|
||||
- "gpa2-5", /* wr */
|
||||
- "gpa0-2", /* cs */
|
||||
- "gpx2-7", /* led */
|
||||
- "gpx1-7", /* db00 */
|
||||
- "gpx2-0", /* db01 */
|
||||
- "gpx1-3", /* db02 */
|
||||
- "gpa2-4", /* db03 */
|
||||
- "gpa2-6", /* db04 */
|
||||
- "gpa2-7", /* db05 */
|
||||
- "gpx1-6", /* db06 */
|
||||
- "gpx1-5"; /* db07 */
|
||||
- samsung,pin-function = <1>;
|
||||
- };
|
||||
- };
|
||||
};
|
||||
|
||||
&i2s0 {
|
||||
@@ -135,6 +92,23 @@ &usbdrd_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
+&serial_0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&serial_1 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&serial_2 {
|
||||
+ // Debugging UART port
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&serial_3 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
/* i2c@12C70000 */
|
||||
&i2c_1 {
|
||||
status = "disabled";
|
||||
@@ -153,74 +127,4 @@ &spi_1 {
|
||||
samsung,spi-src-clk = <0>;
|
||||
num-cs = <2>;
|
||||
cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>, <&gpx2 1 GPIO_ACTIVE_HIGH>;
|
||||
-
|
||||
- spidev: spidev@0 {
|
||||
- status = "disabled";
|
||||
- reg = <0>;
|
||||
- compatible = "odroid,spidev";
|
||||
- spi-max-frequency = <1000000>;
|
||||
-
|
||||
- controller-data {
|
||||
- cs-gpio = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
- samsung,spi-feedback-delay = <0>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- hktft_cs_ogst: hktft_cs_ogst@0 {
|
||||
- status = "disabled";
|
||||
- compatible = "odroid,hktft32";
|
||||
- reg = <0>;
|
||||
- pinctrl-names = "default";
|
||||
- pinctrl-0 = <&hktft_cs_ogst_pins>;
|
||||
-
|
||||
- spi-max-frequency = <40000000>;
|
||||
- rotate = <270>;
|
||||
- bgr;
|
||||
- backlight;
|
||||
- fps = <20>;
|
||||
- bpp = <16>;
|
||||
- reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
|
||||
- dc-gpios = <&gpx1 6 GPIO_ACTIVE_HIGH>;
|
||||
- led-gpios = <&gpx1 2 GPIO_ACTIVE_HIGH>;
|
||||
- debug = <0>;
|
||||
-
|
||||
- hktft_cs_ogst_pins: hktft_cs_ogst_pins {
|
||||
- samsung,pins = "gpx1-5", /* reset */
|
||||
- "gpx1-6", /* dc */
|
||||
- "gpx1-2"; /* led */
|
||||
- };
|
||||
-
|
||||
- controller-data {
|
||||
- cs-gpio = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
- samsung,spi-feedback-delay = <0>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- hktft32: hktft32@0 {
|
||||
- status = "disabled";
|
||||
- compatible = "odroid,hktft32";
|
||||
- reg = <0>;
|
||||
- pinctrl-names = "default";
|
||||
- pinctrl-0 = <&hktft32_pins>;
|
||||
-
|
||||
- spi-max-frequency = <40000000>;
|
||||
- rotate = <90>;
|
||||
- bgr;
|
||||
- backlight;
|
||||
- fps = <20>;
|
||||
- bpp = <16>;
|
||||
- reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
|
||||
- dc-gpios = <&gpx1 6 GPIO_ACTIVE_HIGH>;
|
||||
- debug = <0>;
|
||||
-
|
||||
- hktft32_pins: hktft32_pins {
|
||||
- samsung,pins = "gpx1-5", /* reset */
|
||||
- "gpx1-6"; /* dc */
|
||||
- };
|
||||
-
|
||||
- controller-data {
|
||||
- cs-gpio = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
- samsung,spi-feedback-delay = <0>;
|
||||
- };
|
||||
- };
|
||||
};
|
||||
diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile
|
||||
index 9502f67ce928..2c69e17a8548 100644
|
||||
--- a/arch/arm/boot/dts/overlays/Makefile
|
||||
+++ b/arch/arm/boot/dts/overlays/Makefile
|
||||
@@ -1,12 +1,15 @@
|
||||
# Overlays for the Odroid platform
|
||||
|
||||
dtbo-y += \
|
||||
- spidev1-overlay.dtbo \
|
||||
- i2c1-overlay.dtbo \
|
||||
- i2c5-overlay.dtbo \
|
||||
- hktft32-overlay.dtbo \
|
||||
- hktft35-overlay.dtbo \
|
||||
- hktft-cs-ogst-overlay.dtbo
|
||||
+ spi0.dtbo \
|
||||
+ i2c0.dtbo \
|
||||
+ i2c1.dtbo \
|
||||
+ uart0.dtbo \
|
||||
+ hktft32.dtbo \
|
||||
+ hktft35.dtbo \
|
||||
+ ads7846.dtbo \
|
||||
+ sx865x-i2c1.dtbo \
|
||||
+ hktft-cs-ogst.dtbo
|
||||
|
||||
targets += $(dtbo-y)
|
||||
always := $(dtbo-y)
|
||||
diff --git a/arch/arm/boot/dts/overlays/ads7846.dts b/arch/arm/boot/dts/overlays/ads7846.dts
|
||||
new file mode 100644
|
||||
index 000000000000..62391a33ee18
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/ads7846.dts
|
||||
@@ -0,0 +1,58 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/pinctrl/samsung.h>
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ // spi_1 aliased with spi0
|
||||
+ target = <&spi_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ ads7846: ads7846@1 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ reg = <1>;
|
||||
+ compatible = "ti,ads7846";
|
||||
+ interrupt-parent = <&gpa0>;
|
||||
+ interrupts = <3 0>;
|
||||
+ spi-max-frequency = <1000000>;
|
||||
+
|
||||
+ /* GPA0.3 Pull-up enable */
|
||||
+ pinctrl-0 = <&ts_pendown_gpio>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ pendown-gpio = <&gpa0 3 GPIO_ACTIVE_HIGH>;
|
||||
+ vcc-supply = <&ldo30_reg>;
|
||||
+
|
||||
+ ti,swap-xy = <1>;
|
||||
+ ti,x-min = /bits/ 16 <0>;
|
||||
+ ti,x-max = /bits/ 16 <8000>;
|
||||
+ ti,y-min = /bits/ 16 <0>;
|
||||
+ ti,y-max = /bits/ 16 <4800>;
|
||||
+ ti,x-plate-ohms = /bits/ 16 <40>;
|
||||
+ ti,pressure-max = /bits/ 16 <255>;
|
||||
+
|
||||
+ linux,wakeup;
|
||||
+
|
||||
+ ts_pendown_gpio: ts-pendown-gpio {
|
||||
+ samsung,pins = "gpa0-3";
|
||||
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
|
||||
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
+ };
|
||||
+
|
||||
+ controller-data {
|
||||
+ cs-gpio = <&gpx2 1 GPIO_ACTIVE_HIGH>;
|
||||
+ samsung,spi-feedback-delay = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/overlays/hktft-cs-ogst-overlay.dts b/arch/arm/boot/dts/overlays/hktft-cs-ogst-overlay.dts
|
||||
deleted file mode 100644
|
||||
index a727fb311574..000000000000
|
||||
--- a/arch/arm/boot/dts/overlays/hktft-cs-ogst-overlay.dts
|
||||
+++ /dev/null
|
||||
@@ -1,36 +0,0 @@
|
||||
-/dts-v1/;
|
||||
-/plugin/;
|
||||
-
|
||||
-/ {
|
||||
- fragment@0 {
|
||||
- target = <&i2c_1>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "disabled";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- fragment@1 {
|
||||
- target = <&hsi2c_5>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "disabled";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- fragment@2 {
|
||||
- target = <&spi_1>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "okay";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- fragment@3 {
|
||||
- target = <&hktft_cs_ogst>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "okay";
|
||||
- };
|
||||
- };
|
||||
-};
|
||||
diff --git a/arch/arm/boot/dts/overlays/hktft-cs-ogst.dts b/arch/arm/boot/dts/overlays/hktft-cs-ogst.dts
|
||||
new file mode 100644
|
||||
index 000000000000..3c2bfb9598b1
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/hktft-cs-ogst.dts
|
||||
@@ -0,0 +1,48 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ // spi_1 aliased with spi0
|
||||
+ target = <&spi_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ hktft_cs_ogst: hktft_cs_ogst@0 {
|
||||
+ status = "okay";
|
||||
+ compatible = "odroid,hktft32";
|
||||
+ reg = <0>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hktft_cs_ogst_pins>;
|
||||
+
|
||||
+ spi-max-frequency = <40000000>;
|
||||
+ rotate = <270>;
|
||||
+ bgr;
|
||||
+ backlight;
|
||||
+ fps = <20>;
|
||||
+ bpp = <16>;
|
||||
+ reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
|
||||
+ dc-gpios = <&gpx1 6 GPIO_ACTIVE_HIGH>;
|
||||
+ led-gpios = <&gpx1 2 GPIO_ACTIVE_HIGH>;
|
||||
+ debug = <0>;
|
||||
+
|
||||
+ hktft_cs_ogst_pins: hktft_cs_ogst_pins {
|
||||
+ samsung,pins = "gpx1-5", /* reset */
|
||||
+ "gpx1-6", /* dc */
|
||||
+ "gpx1-2"; /* led */
|
||||
+ };
|
||||
+
|
||||
+ controller-data {
|
||||
+ cs-gpio = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
+ samsung,spi-feedback-delay = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/overlays/hktft32-overlay.dts b/arch/arm/boot/dts/overlays/hktft32-overlay.dts
|
||||
deleted file mode 100644
|
||||
index 7bda6cd8e6d8..000000000000
|
||||
--- a/arch/arm/boot/dts/overlays/hktft32-overlay.dts
|
||||
+++ /dev/null
|
||||
@@ -1,36 +0,0 @@
|
||||
-/dts-v1/;
|
||||
-/plugin/;
|
||||
-
|
||||
-/ {
|
||||
- fragment@0 {
|
||||
- target = <&i2c_1>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "disabled";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- fragment@1 {
|
||||
- target = <&hsi2c_5>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "disabled";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- fragment@2 {
|
||||
- target = <&spi_1>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "okay";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- fragment@3 {
|
||||
- target = <&hktft32>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "okay";
|
||||
- };
|
||||
- };
|
||||
-};
|
||||
diff --git a/arch/arm/boot/dts/overlays/hktft32.dts b/arch/arm/boot/dts/overlays/hktft32.dts
|
||||
new file mode 100644
|
||||
index 000000000000..81d037216d4f
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/hktft32.dts
|
||||
@@ -0,0 +1,46 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ // spi_1 aliased with spi0
|
||||
+ target = <&spi_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ hktft32: hktft32@0 {
|
||||
+ status = "okay";
|
||||
+ compatible = "odroid,hktft32";
|
||||
+ reg = <0>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hktft32_pins>;
|
||||
+
|
||||
+ spi-max-frequency = <40000000>;
|
||||
+ rotate = <90>;
|
||||
+ bgr;
|
||||
+ backlight;
|
||||
+ fps = <20>;
|
||||
+ bpp = <16>;
|
||||
+ reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
|
||||
+ dc-gpios = <&gpx1 6 GPIO_ACTIVE_HIGH>;
|
||||
+ debug = <0>;
|
||||
+
|
||||
+ hktft32_pins: hktft32_pins {
|
||||
+ samsung,pins = "gpx1-5", /* reset */
|
||||
+ "gpx1-6"; /* dc */
|
||||
+ };
|
||||
+
|
||||
+ controller-data {
|
||||
+ cs-gpio = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
+ samsung,spi-feedback-delay = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/overlays/hktft35-overlay.dts b/arch/arm/boot/dts/overlays/hktft35-overlay.dts
|
||||
deleted file mode 100644
|
||||
index a656dd272165..000000000000
|
||||
--- a/arch/arm/boot/dts/overlays/hktft35-overlay.dts
|
||||
+++ /dev/null
|
||||
@@ -1,36 +0,0 @@
|
||||
-/dts-v1/;
|
||||
-/plugin/;
|
||||
-
|
||||
-/ {
|
||||
- fragment@0 {
|
||||
- target = <&i2c_1>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "disabled";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- fragment@1 {
|
||||
- target = <&hsi2c_5>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "disabled";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- fragment@2 {
|
||||
- target = <&spi_1>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "disabled";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- fragment@3 {
|
||||
- target = <&hktft35>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "okay";
|
||||
- };
|
||||
- };
|
||||
-};
|
||||
diff --git a/arch/arm/boot/dts/overlays/hktft35.dts b/arch/arm/boot/dts/overlays/hktft35.dts
|
||||
new file mode 100644
|
||||
index 000000000000..4f199a3be4c4
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/hktft35.dts
|
||||
@@ -0,0 +1,55 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ target-path = "/";
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ hktft35: hktft35 {
|
||||
+ status = "okay";
|
||||
+ compatible = "odroid,hktft35";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hktft35_pins>;
|
||||
+
|
||||
+ rotate = <270>;
|
||||
+ bgr;
|
||||
+ fps = <20>;
|
||||
+ bpp = <16>;
|
||||
+ reset-gpios = <&gpa0 3 GPIO_ACTIVE_HIGH>;
|
||||
+ dc-gpios = <&gpx2 4 GPIO_ACTIVE_HIGH>;
|
||||
+ wr-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
+ cs-gpios = <&gpa0 2 GPIO_ACTIVE_HIGH>;
|
||||
+ led-gpios = <&gpx2 7 GPIO_ACTIVE_HIGH>;
|
||||
+ db-gpios = <&gpx1 7 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpx2 0 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpx1 3 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpa2 4 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpa2 6 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpa2 7 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpx1 6 GPIO_ACTIVE_HIGH>,
|
||||
+ <&gpx1 5 GPIO_ACTIVE_HIGH>;
|
||||
+ debug = <0>;
|
||||
+
|
||||
+ hktft35_pins: hktft35_pins {
|
||||
+ samsung,pins = "gpa0-3", /* reset */
|
||||
+ "gpx2-4", /* dc */
|
||||
+ "gpa2-5", /* wr */
|
||||
+ "gpa0-2", /* cs */
|
||||
+ "gpx2-7", /* led */
|
||||
+ "gpx1-7", /* db00 */
|
||||
+ "gpx2-0", /* db01 */
|
||||
+ "gpx1-3", /* db02 */
|
||||
+ "gpa2-4", /* db03 */
|
||||
+ "gpa2-6", /* db04 */
|
||||
+ "gpa2-7", /* db05 */
|
||||
+ "gpx1-6", /* db06 */
|
||||
+ "gpx1-5"; /* db07 */
|
||||
+ samsung,pin-function = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/overlays/i2c1-overlay.dts b/arch/arm/boot/dts/overlays/i2c0.dts
|
||||
similarity index 78%
|
||||
rename from arch/arm/boot/dts/overlays/i2c1-overlay.dts
|
||||
rename to arch/arm/boot/dts/overlays/i2c0.dts
|
||||
index 2fd27754e7c8..dbf16972867f 100644
|
||||
--- a/arch/arm/boot/dts/overlays/i2c1-overlay.dts
|
||||
+++ b/arch/arm/boot/dts/overlays/i2c0.dts
|
||||
@@ -3,6 +3,7 @@
|
||||
|
||||
/ {
|
||||
fragment@0 {
|
||||
+ // i2c_1 aliased with i2c0
|
||||
target = <&i2c_1>;
|
||||
|
||||
__overlay__ {
|
||||
diff --git a/arch/arm/boot/dts/overlays/i2c5-overlay.dts b/arch/arm/boot/dts/overlays/i2c1.dts
|
||||
similarity index 78%
|
||||
rename from arch/arm/boot/dts/overlays/i2c5-overlay.dts
|
||||
rename to arch/arm/boot/dts/overlays/i2c1.dts
|
||||
index 9ef9e66699e0..8542709a37df 100644
|
||||
--- a/arch/arm/boot/dts/overlays/i2c5-overlay.dts
|
||||
+++ b/arch/arm/boot/dts/overlays/i2c1.dts
|
||||
@@ -3,6 +3,7 @@
|
||||
|
||||
/ {
|
||||
fragment@0 {
|
||||
+ // hsi2c_5 alised with i2c1
|
||||
target = <&hsi2c_5>;
|
||||
|
||||
__overlay__ {
|
||||
diff --git a/arch/arm/boot/dts/overlays/spi0.dts b/arch/arm/boot/dts/overlays/spi0.dts
|
||||
new file mode 100644
|
||||
index 000000000000..2eab40560ac2
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/spi0.dts
|
||||
@@ -0,0 +1,30 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ // spi_1 aliased with spi0
|
||||
+ target = <&spi_1>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ spidev: spidev@0 {
|
||||
+ status = "okay";
|
||||
+ reg = <0>;
|
||||
+ compatible = "odroid,spidev";
|
||||
+ spi-max-frequency = <1000000>;
|
||||
+
|
||||
+ controller-data {
|
||||
+ cs-gpio = <&gpa2 5 GPIO_ACTIVE_HIGH>;
|
||||
+ samsung,spi-feedback-delay = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/overlays/spidev1-overlay.dts b/arch/arm/boot/dts/overlays/spidev1-overlay.dts
|
||||
deleted file mode 100644
|
||||
index c5cb6bcb6011..000000000000
|
||||
--- a/arch/arm/boot/dts/overlays/spidev1-overlay.dts
|
||||
+++ /dev/null
|
||||
@@ -1,20 +0,0 @@
|
||||
-/dts-v1/;
|
||||
-/plugin/;
|
||||
-
|
||||
-/ {
|
||||
- fragment@0 {
|
||||
- target = <&spi_1>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "okay";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- fragment@1 {
|
||||
- target = <&spidev>;
|
||||
-
|
||||
- __overlay__ {
|
||||
- status = "okay";
|
||||
- };
|
||||
- };
|
||||
-};
|
||||
diff --git a/arch/arm/boot/dts/overlays/sx865x-i2c1.dts b/arch/arm/boot/dts/overlays/sx865x-i2c1.dts
|
||||
new file mode 100644
|
||||
index 000000000000..c0a54ea45c78
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/sx865x-i2c1.dts
|
||||
@@ -0,0 +1,34 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ // hsi2c_5 alised with i2c1
|
||||
+ target = <&hsi2c_5>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ sx865x: sx865x@49 {
|
||||
+ status = "okay";
|
||||
+ compatible = "semtech,sx8650";
|
||||
+ reg = <0x49>;
|
||||
+ #clock-cells = <0>;
|
||||
+
|
||||
+ /* H/W Pin control setup */
|
||||
+ gpio-pendown = <&gpx3 1 GPIO_ACTIVE_HIGH>;
|
||||
+ gpio-reset = <&gpx2 5 GPIO_ACTIVE_LOW>;
|
||||
+
|
||||
+ /* platform data setup */
|
||||
+ invert-x = <0>;
|
||||
+ invert-y = <1>;
|
||||
+ swap-xy = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/overlays/uart0.dts b/arch/arm/boot/dts/overlays/uart0.dts
|
||||
new file mode 100644
|
||||
index 000000000000..34c79f291cac
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/overlays/uart0.dts
|
||||
@@ -0,0 +1,12 @@
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+/ {
|
||||
+ fragment@0 {
|
||||
+ target = <&serial_0>;
|
||||
+
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -1 +0,0 @@
|
|||
rockchip-current
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
Patches act8846 regulator providing the proper reset handle and exploit
|
||||
the SIPC bit in GLB_POWER_OFF register. Mainly used to reset some rockchip
|
||||
boards.
|
||||
|
||||
Origin: <https://patchwork.kernel.org/patch/6409521/>
|
||||
|
||||
diff --git a/drivers/regulator/act8865-regulator.c b/drivers/regulator/act8865-regulator.c
|
||||
index 2ff73d7..836d10b 100644
|
||||
--- a/drivers/regulator/act8865-regulator.c
|
||||
+++ b/drivers/regulator/act8865-regulator.c
|
||||
@@ -27,6 +27,7 @@
|
||||
#include <linux/regulator/of_regulator.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <dt-bindings/regulator/active-semi,8865-regulator.h>
|
||||
+#include <linux/reboot.h>
|
||||
|
||||
/*
|
||||
* ACT8600 Global Register Map.
|
||||
@@ -133,6 +134,8 @@
|
||||
#define ACT8865_VOLTAGE_NUM 64
|
||||
#define ACT8600_SUDCDC_VOLTAGE_NUM 255
|
||||
|
||||
+#define ACT8846_SIPC_MASK 0x01
|
||||
+
|
||||
struct act8865 {
|
||||
struct regmap *regmap;
|
||||
int off_reg;
|
||||
@@ -402,6 +405,22 @@ static void act8865_power_off(void)
|
||||
while (1);
|
||||
}
|
||||
|
||||
+static int act8846_power_cycle(struct notifier_block *this,
|
||||
+ unsigned long code, void *unused)
|
||||
+{
|
||||
+ struct act8865 *act8846;
|
||||
+
|
||||
+ act8846 = i2c_get_clientdata(act8865_i2c_client);
|
||||
+ regmap_write(act8846->regmap, ACT8846_GLB_OFF_CTRL, ACT8846_SIPC_MASK);
|
||||
+
|
||||
+ return NOTIFY_DONE;
|
||||
+}
|
||||
+
|
||||
+static struct notifier_block act8846_restart_handler = {
|
||||
+ .notifier_call = act8846_power_cycle,
|
||||
+ .priority = 129,
|
||||
+};
|
||||
+
|
||||
static int act8865_pmic_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *i2c_id)
|
||||
{
|
||||
@@ -484,6 +503,8 @@ static int act8865_pmic_probe(struct i2c_client *client,
|
||||
}
|
||||
|
||||
if (of_device_is_system_power_controller(dev->of_node)) {
|
||||
+ int ret;
|
||||
+
|
||||
if (!pm_power_off && (off_reg > 0)) {
|
||||
act8865_i2c_client = client;
|
||||
act8865->off_reg = off_reg;
|
||||
@@ -492,6 +513,14 @@ static int act8865_pmic_probe(struct i2c_client *client,
|
||||
} else {
|
||||
dev_err(dev, "Failed to set poweroff capability, already defined\n");
|
||||
}
|
||||
+
|
||||
+ if (type == ACT8846) {
|
||||
+ act8865_i2c_client = client;
|
||||
+ ret = register_restart_handler(&act8846_restart_handler);
|
||||
+ if (ret)
|
||||
+ pr_err("%s: cannot register restart handler, %d\n",
|
||||
+ __func__, ret);
|
||||
+ }
|
||||
}
|
||||
|
||||
/* Finally register devices */
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
From 604ea7fc311af2b3a41e7fe3b4fbde0ee03dfb9c Mon Sep 17 00:00:00 2001
|
||||
From: Myy Miouyouyou <myy@miouyouyou.fr>
|
||||
Date: Thu, 19 Oct 2017 21:09:50 +0200
|
||||
Subject: [PATCH 04/28] dts: rk3288: miqi: Enabling the Mali GPU node
|
||||
|
||||
Why is the MiQi the only one left without a working mali GPU node ?
|
||||
|
||||
Seriously, is there a rk3288 chipset WITHOUT a mali GPU ? Couldn't
|
||||
they enable it once in the DTSI, instead of defining it as "disabled"
|
||||
and enabling it in every DTS file ?
|
||||
|
||||
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-miqi.dts | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
index 4d923aa6..3cd60674 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
@@ -149,6 +149,11 @@
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
--
|
||||
2.11.0
|
||||
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
From 89e5763110ca77d68a4be00cd97a638adc2401d5 Mon Sep 17 00:00:00 2001
|
||||
From: Willy Tarreau <w@1wt.eu>
|
||||
Date: Tue, 2 Aug 2016 08:31:00 +0200
|
||||
Subject: [PATCH 05/28] ARM: dts: rockchip: fix the regulator's voltage range
|
||||
on MiQi board
|
||||
|
||||
The board declared too narrow a voltage range for the CPU and GPU
|
||||
regulators, preventing it from using the full CPU frequency range.
|
||||
The regulators support 712500 to 1500000 microvolts.
|
||||
|
||||
Signed-off-by: Willy Tarreau <w@1wt.eu>
|
||||
(cherry picked from commit 95330e63a9295a2632cee8cce5db80677f01857a)
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-miqi.dts | 8 ++++----
|
||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
index 3cd60674..a1c3cdaa 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
@@ -168,8 +168,8 @@
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
reg = <0x40>;
|
||||
regulator-name = "vdd_cpu";
|
||||
- regulator-min-microvolt = <850000>;
|
||||
- regulator-max-microvolt = <1350000>;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-enable-ramp-delay = <300>;
|
||||
@@ -182,8 +182,8 @@
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
reg = <0x41>;
|
||||
regulator-name = "vdd_gpu";
|
||||
- regulator-min-microvolt = <850000>;
|
||||
- regulator-max-microvolt = <1350000>;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
--
|
||||
2.11.0
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue