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Define safe voltage/cpufreq defaults for sun8i/dev

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This commit is contained in:
ThomasKaiser 2016-04-09 16:02:53 +02:00
parent c25dd4ca08
commit da11a8c01f
5 changed files with 1586 additions and 4 deletions
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54
patch/u-boot/u-boot-dev/u-boot-99-opi-change-build-settings.patch
View file

@ -2,16 +2,18 @@ diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 4e9051d..6fba0b0 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -17,3 +17,5 @@ CONFIG_USB_EHCI_HCD=y
@@ -17,3 +17,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_USB3_VBUS_PIN=""
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_SY8106A_VOUT1_VOLT=1200
+CONFIG_SYS_CLK_FREQ=1008000000
diff -Nur a/configs/orangepi_h3_defconfig b/configs/orangepi_h3_defconfig
--- a/configs/orangepi_h3_defconfig 1970-01-01 01:00:00.000000000 +0100
+++ b/configs/orangepi_h3_defconfig 2016-02-19 00:58:31.007705977 +0100
@@ -0,0 +1,18 @@
@@ -0,0 +1,20 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
@ -33,22 +35,26 @@ diff -Nur a/configs/orangepi_h3_defconfig b/configs/orangepi_h3_defconfig
+CONFIG_USB3_VBUS_PIN=""
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_SY8106A_VOUT1_VOLT=1200
+CONFIG_SYS_CLK_FREQ=1008000000
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index ff124bd..d78f8c7 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -18,3 +18,5 @@ CONFIG_SY8106A_POWER=y
@@ -18,3 +18,7 @@ CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11)"
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_SY8106A_VOUT1_VOLT=1200
+CONFIG_SYS_CLK_FREQ=1008000000
diff --git a/configs/Sinovoip_BPI_M2_plus_defconfig b/configs/Sinovoip_BPI_M2_plus_defconfig
new file mode 100644
index 0000000..2e7c095
--- /dev/null
+++ b/configs/Sinovoip_BPI_M2_plus_defconfig
@@ -0,0 +1,17 @@
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
@ -66,6 +72,7 @@ index 0000000..2e7c095
+CONFIG_USB_EHCI_HCD=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_SYS_CLK_FREQ=816000000
diff --git a/arch/arm/dts/sun8i-h3-bananapi-m2plus.dts b/arch/arm/dts/sun8i-h3-bananapi-m2plus.dts
new file mode 100644
index 0000000..da6481f
@ -381,3 +388,42 @@ index c2f63c5..e7b6334 100644
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index ff9ac09..992cfa1 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -16,3 +16,7 @@ CONFIG_CMD_GPIO=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB1_VBUS_PIN="PG13"
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_SY8106A_VOUT1_VOLT=1200
+CONFIG_SYS_CLK_FREQ=1008000000
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
new file mode 100644
index 0000000..a69961c
--- /dev/null
+++ b/configs/orangepi_one_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB3_VBUS_PIN=""
+CONFIG_SYS_CLK_FREQ=1008000000
+CONFIG_DM=y
+CONFIG_DM_GPIO=y

42
patch/u-boot/u-boot-dev/u-boot-set-safe-axi_apb-clock-dividers.patch Normal file
View file

@ -0,0 +1,42 @@
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 15272c9..cedddc2 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -117,8 +117,8 @@ void clock_set_pll1(unsigned int clk)
sdelay(200);
/* Switch CPU to PLL1 */
- writel(AXI_DIV_3 << AXI_DIV_SHIFT |
- ATB_DIV_2 << ATB_DIV_SHIFT |
+ writel(AXI_DIV_4 << AXI_DIV_SHIFT |
+ ATB_DIV_4 << ATB_DIV_SHIFT |
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_axi_cfg);
}
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index f2990db..b3a8575 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -180,6 +180,7 @@ struct sunxi_ccm_reg {
#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
#define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16)
#define CCM_PLL1_CTRL_EN (0x1 << 31)
+#define CCM_PLL1_CTRL_LOCK (0x1 << 28)
#define CCM_PLL3_CTRL_M_SHIFT 0
#define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT)
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index cedddc2..3fe9305 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -114,7 +114,9 @@ void clock_set_pll1(unsigned int clk)
writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
- sdelay(200);
+
+ while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_CTRL_LOCK))
+ ;
/* Switch CPU to PLL1 */
writel(AXI_DIV_4 << AXI_DIV_SHIFT |