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Update lime2 lan support (#815)
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commit
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1 changed files with 72 additions and 0 deletions
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@ -0,0 +1,72 @@
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diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
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index cba7d7d..1509562 100755
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--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
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+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
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@@ -37,3 +37,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y
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CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
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CONFIG_G_DNL_VENDOR_NUM=0x1f3a
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CONFIG_G_DNL_PRODUCT_NUM=0x1010
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+CONFIG_PHY_MICREL=y
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+CONFIG_PHY_MICREL_KSZ90X1=y
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diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
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index 0bb99e6..ce35daf 100644
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--- a/drivers/net/phy/micrel_ksz90x1.c
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+++ b/drivers/net/phy/micrel_ksz90x1.c
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@@ -16,6 +16,8 @@
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#include <fdtdec.h>
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#include <micrel.h>
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#include <phy.h>
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+#include <asm/io.h>
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+#include <asm/arch/clock.h>
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DECLARE_GLOBAL_DATA_PTR;
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@@ -335,6 +337,10 @@ static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
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static int ksz9031_config(struct phy_device *phydev)
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{
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int ret;
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+ struct sunxi_ccm_reg *const ccm =
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+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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+
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+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(4));
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ret = ksz9031_of_config(phydev);
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if (ret)
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diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
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index 6d917f8..87956c0 100644
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--- a/drivers/net/phy/realtek.c
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+++ b/drivers/net/phy/realtek.c
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@@ -11,6 +11,8 @@
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#include <common.h>
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#include <linux/bitops.h>
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#include <phy.h>
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+#include <asm/io.h>
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+#include <asm/arch/clock.h>
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#define PHY_RTL8211x_FORCE_MASTER BIT(1)
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@@ -63,6 +65,9 @@ static int rtl8211b_probe(struct phy_device *phydev)
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/* RealTek RTL8211x */
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static int rtl8211x_config(struct phy_device *phydev)
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{
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+ struct sunxi_ccm_reg *const ccm =
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+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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+
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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/* mask interrupt at init; if the interrupt is
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@@ -71,6 +76,14 @@ static int rtl8211x_config(struct phy_device *phydev)
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
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MIIM_RTL8211x_PHY_INTR_DIS);
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+ if(phydev->drv->uid == 0x1cc912) {
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+ /* With RTL8211C Force Master must be enabled */
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+ phydev->flags |= PHY_RTL8211x_FORCE_MASTER;
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+ } else if(phydev->drv->uid == 0x1cc915) {
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+ /* RTL8211E has different GMAC_TX_DELAY requirements */
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+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(2));
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+ }
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+
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if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
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unsigned int reg;
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