diff --git a/build-all.sh b/build-all.sh
index ee8f03db8..53a56a8b6 100644
--- a/build-all.sh
+++ b/build-all.sh
@@ -121,7 +121,7 @@ for line in "${buildlist[@]}"; do
 		CPUMIN CPUMAX UBOOT_VER KERNEL_VER GOVERNOR BOOTSIZE UBOOT_TOOLCHAIN KERNEL_TOOLCHAIN PACKAGE_LIST_EXCLUDE KERNEL_IMAGE_TYPE \
 		write_uboot_platform family_tweaks setup_write_uboot_platform BOOTSCRIPT UBOOT_FILES LOCALVERSION UBOOT_COMPILER KERNEL_COMPILER \
 		UBOOT_TARGET MODULES MODULES_NEXT MODULES_DEV INITRD_ARCH HAS_UUID_SUPPORT BOOTENV_FILE BOOTDELAY MODULES_BLACKLIST MODULES_BLACKLIST_NEXT \
-		MODULES_BLACKLIST_DEV MOUNT SDCARD buildtext
+		MODULES_BLACKLIST_DEV MOUNT SDCARD BOOTPATCHDIR buildtext
 
 	read BOARD BRANCH RELEASE BUILD_DESKTOP <<< $line
 	n=$[$n+1]
diff --git a/common.sh b/common.sh
index cc20148b5..60e66b620 100644
--- a/common.sh
+++ b/common.sh
@@ -32,7 +32,7 @@ compile_uboot()
 	fi
 	cd "$ubootdir"
 
-	[[ $FORCE_CHECKOUT == yes ]] && advanced_patch "u-boot" "$BOOTDIR-$BRANCH" "$BOARD" "$BOOTDIR-$BRANCH"
+	[[ $FORCE_CHECKOUT == yes ]] && advanced_patch "u-boot" "$BOOTPATCHDIR" "$BOARD" "${LINUXFAMILY}-${BOARD}-${BRANCH}"
 
 	# create patch for manual source changes
 	[[ $CREATE_PATCHES == yes ]] && userpatch_create "u-boot"
diff --git a/config/sources/cubox.conf b/config/sources/cubox.conf
index 680a2d4ef..27b05c28b 100644
--- a/config/sources/cubox.conf
+++ b/config/sources/cubox.conf
@@ -1,7 +1,7 @@
-
 BOOTSOURCE='https://github.com/SolidRun/u-boot-imx6'
 BOOTBRANCH='branch:imx6'
 BOOTDIR='u-boot-cubox'
+BOOTPATCHDIR='u-boot-cubox'
 BOOTSCRIPT="boot-cubox.cmd:boot.cmd"
 
 UBOOT_NEEDS_GCC='< 5.0'
diff --git a/config/sources/marvell.conf b/config/sources/marvell.conf
index e64504465..b65a6cb9a 100644
--- a/config/sources/marvell.conf
+++ b/config/sources/marvell.conf
@@ -1,13 +1,16 @@
 BOOTSOURCE='https://github.com/SolidRun/u-boot-armada38x'
 BOOTBRANCH='branch:u-boot-2013.01-15t1-clearfog'
 BOOTDIR='u-boot-armada'
+BOOTPATCHDIR='u-boot-armada'
 BOOTSCRIPT="boot-marvell.cmd:boot.cmd"
 
 UBOOT_NEEDS_GCC='< 5.0'
 UBOOT_COMPILER="arm-linux-gnueabi-"
 
+## for SD/eMMC
 UBOOT_TARGET="u-boot.mmc"
-UBOOT_FILES="u-boot.mmc"
+UBOOT_FILES="u-boot.mmc u-boot-uart.mmc"
+
 BOOTENV_FILE='clearfog-default.txt'
 HAS_UUID_SUPPORT=yes
 
diff --git a/config/sources/odroidc1.conf b/config/sources/odroidc1.conf
index c48e73ce0..60ab6c08e 100644
--- a/config/sources/odroidc1.conf
+++ b/config/sources/odroidc1.conf
@@ -1,6 +1,7 @@
 BOOTSOURCE='https://github.com/hardkernel/u-boot.git'
 BOOTBRANCH='branch:odroidc-v2011.03'
 BOOTDIR='u-boot-odroidc1'
+BOOTPATCHDIR='u-boot-odroidc1'
 UBOOT_NEEDS_GCC='< 4.9'
 BOOTSCRIPT="boot-odroid-c1.ini:boot.ini"
 
diff --git a/config/sources/odroidc2.conf b/config/sources/odroidc2.conf
index 532c82b38..aa006072a 100644
--- a/config/sources/odroidc2.conf
+++ b/config/sources/odroidc2.conf
@@ -1,6 +1,7 @@
 BOOTSOURCE='https://github.com/hardkernel/u-boot.git'
 BOOTBRANCH='branch:odroidc2-v2015.01'
 BOOTDIR='u-boot-odroidc2'
+BOOTPATCHDIR='u-boot-odroidc2'
 UBOOT_NEEDS_GCC='< 5.0'
 UBOOT_TARGET="ARCH=arm"
 BOOTSCRIPT="boot-odroid-c2.ini:boot.ini"
diff --git a/config/sources/odroidxu4.conf b/config/sources/odroidxu4.conf
index 1ce94adf6..c6ca5def4 100644
--- a/config/sources/odroidxu4.conf
+++ b/config/sources/odroidxu4.conf
@@ -1,4 +1,3 @@
-BOOTDIR='u-boot-odroidxu'
 OFFSET=4
 
 case $BRANCH in
@@ -6,8 +5,10 @@ case $BRANCH in
 
 	BOOTSOURCE='https://github.com/hardkernel/u-boot.git'
 	BOOTBRANCH='branch:odroidxu3-v2012.07'
-	UBOOT_FILES="sd_fuse/hardkernel/bl1.bin.hardkernel sd_fuse/hardkernel/bl2.bin.hardkernel u-boot.bin sd_fuse/hardkernel/tzsw.bin.hardkernel"
-	BOOTSCRIPT="boot-odroid-xu4-default.ini:boot.ini"
+	UBOOT_FILES='sd_fuse/hardkernel/bl1.bin.hardkernel sd_fuse/hardkernel/bl2.bin.hardkernel u-boot.bin sd_fuse/hardkernel/tzsw.bin.hardkernel'
+	BOOTSCRIPT='boot-odroid-xu4-default.ini:boot.ini'
+	BOOTDIR='u-boot-odroidxu'
+	BOOTPATCHDIR='u-boot-odroidxu4-default'
 
 	KERNELSOURCE='https://github.com/hardkernel/linux'
 	KERNELBRANCH='branch:odroidxu3-3.10.y'
@@ -19,8 +20,10 @@ case $BRANCH in
 	BOOTSOURCE=$MAINLINE_UBOOT_SOURCE
 	BOOTBRANCH=$MAINLINE_UBOOT_BRANCH
 	BOOTCONFIG=odroid-xu3_defconfig
-	UBOOT_FILES="sd_fusing.sh xu4_blobs/bl1.bin.hardkernel xu4_blobs/bl2.bin.hardkernel.1mb_uboot u-boot-dtb.bin xu4_blobs/tzsw.bin.hardkernel"
-	BOOTSCRIPT="boot-odroid-xu4-next.cmd:boot.cmd"
+	UBOOT_FILES='sd_fusing.sh xu4_blobs/bl1.bin.hardkernel xu4_blobs/bl2.bin.hardkernel.1mb_uboot u-boot-dtb.bin xu4_blobs/tzsw.bin.hardkernel'
+	BOOTSCRIPT='boot-odroid-xu4-next.cmd:boot.cmd'
+	BOOTDIR=$MAINLINE_UBOOT_DIR
+	BOOTPATCHDIR='u-boot-odroidxu4-next'
 	BOOTENV_FILE='odroidxu4-next.txt'
 	HAS_UUID_SUPPORT=yes
 
diff --git a/config/sources/pine64.conf b/config/sources/pine64.conf
index 494db99ec..41e2672bb 100644
--- a/config/sources/pine64.conf
+++ b/config/sources/pine64.conf
@@ -1,4 +1,3 @@
-
 BOOTSOURCE='https://github.com/zador-blood-stained/u-boot-pine64-armbian.git'
 BOOTDIR='u-boot-pine64'
 
@@ -10,12 +9,14 @@ case $BRANCH in
 	BOOTBRANCH='branch:master'
 	BOOTSCRIPT='boot-pine64-default.cmd:boot.cmd'
 	BOOTENV_FILE='pine64-default.txt'
+	UBOOT_FILES='u-boot-with-dtb.bin pine64-plus.dtb pine64.dtb pine64drm-plus.dtb pine64drm.dtb'
+	BOOTPATCHDIR='u-boot-pine64-default'
+
 	KERNELSOURCE='https://github.com/longsleep/linux-pine64.git'
 	KERNELBRANCH='branch:pine64-hacks-1.2'
 	KERNELDIR='linux-pine64'
 	GOVERNOR=interactive
 	OFFSET=2
-	UBOOT_FILES="u-boot-with-dtb.bin pine64-plus.dtb pine64.dtb pine64drm-plus.dtb pine64drm.dtb"
 	INITRD_ARCH=arm
 	;;
 
@@ -23,6 +24,8 @@ case $BRANCH in
 	BOOTBRANCH='branch:next'
 	BOOTSCRIPT='boot-pine64-next.cmd:boot.cmd'
 	BOOTENV_FILE='pine64-next.txt'
+	BOOTPATCHDIR='u-boot-pine64-dev'
+
 	KERNELSOURCE='https://github.com/Icenowy/linux'
 	KERNELBRANCH='branch:ice-a64-v6.1'
 	KERNELDIR='linux-pine64-dev'
diff --git a/config/sources/s500.conf b/config/sources/s500.conf
index f980ea7dc..1974915ee 100644
--- a/config/sources/s500.conf
+++ b/config/sources/s500.conf
@@ -16,6 +16,7 @@ case $BOARD in
 	BOOTSOURCE='https://github.com/LeMaker/u-boot-actions'
 	BOOTBRANCH='branch:s500-master'
 	BOOTDIR='u-boot-s500'
+	BOOTPATCHDIR='u-boot-s500'
 	UBOOT_FILES="$SRC/lib/bin/s500-bootloader-guitar.bin u-boot-dtb.img"
 	SERIALCON=ttyS3
 	;;
@@ -24,6 +25,7 @@ case $BOARD in
 	BOOTSOURCE='https://github.com/xapp-le/u-boot'
 	BOOTBRANCH='branch:merge-20160113'
 	BOOTDIR='u-boot-roseapple'
+	BOOTPATCHDIR='u-boot-roseapple'
 	UBOOT_FILES="$SRC/lib/bin/s500-bootloader-roseapple.bin u-boot-dtb.img"
 	SERIALCON=ttyS2
 	;;
diff --git a/config/sources/sunxi_common.inc b/config/sources/sunxi_common.inc
index d181eb525..8596a0989 100644
--- a/config/sources/sunxi_common.inc
+++ b/config/sources/sunxi_common.inc
@@ -1,9 +1,9 @@
-
 BOOTSOURCE=$MAINLINE_UBOOT_SOURCE
 BOOTDIR=$MAINLINE_UBOOT_DIR
 BOOTBRANCH=$MAINLINE_UBOOT_BRANCH
 BOOTSCRIPT="boot-sunxi.cmd:boot.cmd"
 BOOTENV_FILE='sunxi-default.txt'
+BOOTPATCHDIR="u-boot-sunxi"
 
 HAS_UUID_SUPPORT=yes
 BOOTDELAY=0
diff --git a/config/sources/udoo-neo.conf b/config/sources/udoo-neo.conf
index df9b0517a..205da3c7d 100644
--- a/config/sources/udoo-neo.conf
+++ b/config/sources/udoo-neo.conf
@@ -1,5 +1,6 @@
 BOOTSOURCE='https://github.com/UDOOboard/uboot-imx'
 BOOTDIR='u-boot-udoo'
+BOOTPATCHDIR='u-boot-udoo'
 BOOTSCRIPT="boot-$BOARD.cmd:boot.cmd"
 
 case $BOARD in
@@ -32,8 +33,6 @@ CPUMIN=392000
 CPUMAX=996000
 GOVERNOR=interactive
 
-
-
 UBOOT_FILES="SPL u-boot.img"
 
 write_uboot_platform()
diff --git a/config/sources/udoo.conf b/config/sources/udoo.conf
index df9b0517a..205da3c7d 100644
--- a/config/sources/udoo.conf
+++ b/config/sources/udoo.conf
@@ -1,5 +1,6 @@
 BOOTSOURCE='https://github.com/UDOOboard/uboot-imx'
 BOOTDIR='u-boot-udoo'
+BOOTPATCHDIR='u-boot-udoo'
 BOOTSCRIPT="boot-$BOARD.cmd:boot.cmd"
 
 case $BOARD in
@@ -32,8 +33,6 @@ CPUMIN=392000
 CPUMAX=996000
 GOVERNOR=interactive
 
-
-
 UBOOT_FILES="SPL u-boot.img"
 
 write_uboot_platform()
diff --git a/patch/u-boot/u-boot-armada-dev/compiler.patch b/patch/u-boot/u-boot-armada-dev/compiler.patch
deleted file mode 100644
index c5d1c0c81..000000000
--- a/patch/u-boot/u-boot-armada-dev/compiler.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-diff --git a/tools/marvell/bin_hdr/base.mk b/tools/marvell/bin_hdr/base.mk
-index 33ecf70..d1ee228 100755
---- a/tools/marvell/bin_hdr/base.mk
-+++ b/tools/marvell/bin_hdr/base.mk
-@@ -208,7 +208,7 @@ CPUOPTS  = -mthumb -mthumb-interwork -march=armv7 -mlittle-endian
- BH_ROOT_DIR  = $(TOPDIR)/tools/marvell/bin_hdr
- INCLUDE      = -I$(BH_ROOT_DIR)/src_ddr -I$(BH_ROOT_DIR)/src_phy/$(BOARD) -I$(BH_ROOT_DIR)/inc/common \
- 	       -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(INCNAME)  -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(BOARD) -I$(BH_ROOT_DIR)/platform/sysEnv/$(BOARD) -I$(TOPDIR)/include -I$(BH_ROOT_DIR)/src_init/$(BOARD)
--HOSTCFLAGS   = -Wall $(INCLUDE)
-+HOSTCFLAGS   = -fno-stack-protector -Wall $(INCLUDE)
- 
- ifeq ($(BIN_HDR_DEBUG),1)
- DEBUG_FLAGS += -g -O0
-@@ -223,7 +223,7 @@ DEBUG_MODE_FLAG = no
- endif
- endif
- 
--CFLAGS   += -Wall $(INCLUDE) $(DEBUG_FLAGS) $(CPUOPTS) -msoft-float -mabi=aapcs
-+CFLAGS   += -fno-stack-protector -Wall $(INCLUDE) $(DEBUG_FLAGS) $(CPUOPTS) -msoft-float -mabi=aapcs
- 
- ifeq ($(BOARD),msys_bc2)
- CFLAGS   += -fPIE -fno-zero-initialized-in-bss -fno-unwind-tables
-@@ -231,7 +231,7 @@ else
- CFLAGS   += -fdata-sections -ffunction-sections
- endif
- 
--EXTRA_LD_FLAGS = -Wl,--gc-sections --entry=_start
-+EXTRA_LD_FLAGS = -fno-stack-protector -Wl,--gc-sections --entry=_start
- 
- ifeq ($(DDRTYPE),ddr4)
- CFLAGS += -DCONFIG_DDR4
diff --git a/patch/u-boot/u-boot-armada-dev/loading-boot.scr.patch b/patch/u-boot/u-boot-armada-dev/loading-boot.scr.patch
deleted file mode 100644
index 914064bdc..000000000
--- a/patch/u-boot/u-boot-armada-dev/loading-boot.scr.patch
+++ /dev/null
@@ -1,14 +0,0 @@
-diff --git a/board/mv_ebu/a38x/mv_main_a38x.c b/board/mv_ebu/a38x/mv_main_a38x.c
-index 4b43a9c..5489685 100755
---- a/board/mv_ebu/a38x/mv_main_a38x.c
-+++ b/board/mv_ebu/a38x/mv_main_a38x.c
-@@ -679,7 +679,8 @@ void misc_init_r_env(void)
- #if (CONFIG_BOOTDELAY >= 0)
- 	env = getenv("bootcmd");
- 	if (!env)
--		setenv("bootcmd", "tftpboot 0x2000000 $image_name;tftpboot $fdtaddr $fdtfile;"
-+		setenv("bootcmd", "ext4load mmc 0:1 ${script_addr_r} boot/boot.scr;source ${script_addr_r};"
-+		"tftpboot 0x2000000 $image_name;tftpboot $fdtaddr $fdtfile;"
- 		"setenv bootargs $console $nandEcc $mtdparts $bootargs_root nfsroot=$serverip:$rootpath "
- 		"ip=$ipaddr:$serverip$bootargs_end $mvNetConfig video=dovefb:lcd0:$lcd0_params "
- 		"clcd.lcd0_enable=$lcd0_enable clcd.lcd_panel=$lcd_panel; bootz 0x2000000 - $fdtaddr;");
diff --git a/patch/u-boot/u-boot-armada-dev/slot0=mpci_1=sata.patch.disabled b/patch/u-boot/u-boot-armada-dev/slot0=mpci_1=sata.patch.disabled
deleted file mode 100644
index 848ee1551..000000000
--- a/patch/u-boot/u-boot-armada-dev/slot0=mpci_1=sata.patch.disabled
+++ /dev/null
@@ -1,12 +0,0 @@
-diff --git a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-index 3fb7465..70384a0 100755
---- a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-+++ b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-@@ -89,7 +89,7 @@ SERDES_MAP CustomerBoardTopologyConfig[][MAX_SERDES_LANES] =
- {	/* ClarFog A1 board topology */
- 	{ SATA0,	__3Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },
- 	{ SGMII1,	__1_25Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },
--#if 1
-+#if 0
- 	{ PEX1,	  	__5Gbps,	PEX_ROOT_COMPLEX_x1,		MV_FALSE,	MV_FALSE },
- #else
diff --git a/patch/u-boot/u-boot-armada-dev/slot0=sata_1=sata.patch.disabled b/patch/u-boot/u-boot-armada-dev/slot0=sata_1=sata.patch.disabled
deleted file mode 100644
index 892ceb043..000000000
--- a/patch/u-boot/u-boot-armada-dev/slot0=sata_1=sata.patch.disabled
+++ /dev/null
@@ -1,20 +0,0 @@
-diff --git a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-index 3fb7465..70384a0 100755
---- a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-+++ b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-@@ -89,13 +89,13 @@ SERDES_MAP CustomerBoardTopologyConfig[][MAX_SERDES_LANES] =
- {	/* ClarFog A1 board topology */
- 	{ SATA0,	__3Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },
- 	{ SGMII1,	__1_25Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },
--#if 1
-+#if 0
- 	{ PEX1,	  	__5Gbps,	PEX_ROOT_COMPLEX_x1,		MV_FALSE,	MV_FALSE },
- #else
- 	{ SATA1,	__3Gbps,	SERDES_DEFAULT_MODE,		MV_TRUE,	MV_FALSE },
- #endif
- 	{ USB3_HOST1,	__5Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },
--#if 1
-+#if 0
- 	{ PEX2,	  	__5Gbps,	PEX_ROOT_COMPLEX_x1,		MV_FALSE,	MV_FALSE },
- #else
- 	{ SATA2,	__3Gbps,	SERDES_DEFAULT_MODE,		MV_TRUE,	MV_FALSE },
diff --git a/patch/u-boot/u-boot-armada-next/compiler.patch b/patch/u-boot/u-boot-armada-next/compiler.patch
deleted file mode 100644
index c5d1c0c81..000000000
--- a/patch/u-boot/u-boot-armada-next/compiler.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-diff --git a/tools/marvell/bin_hdr/base.mk b/tools/marvell/bin_hdr/base.mk
-index 33ecf70..d1ee228 100755
---- a/tools/marvell/bin_hdr/base.mk
-+++ b/tools/marvell/bin_hdr/base.mk
-@@ -208,7 +208,7 @@ CPUOPTS  = -mthumb -mthumb-interwork -march=armv7 -mlittle-endian
- BH_ROOT_DIR  = $(TOPDIR)/tools/marvell/bin_hdr
- INCLUDE      = -I$(BH_ROOT_DIR)/src_ddr -I$(BH_ROOT_DIR)/src_phy/$(BOARD) -I$(BH_ROOT_DIR)/inc/common \
- 	       -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(INCNAME)  -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(BOARD) -I$(BH_ROOT_DIR)/platform/sysEnv/$(BOARD) -I$(TOPDIR)/include -I$(BH_ROOT_DIR)/src_init/$(BOARD)
--HOSTCFLAGS   = -Wall $(INCLUDE)
-+HOSTCFLAGS   = -fno-stack-protector -Wall $(INCLUDE)
- 
- ifeq ($(BIN_HDR_DEBUG),1)
- DEBUG_FLAGS += -g -O0
-@@ -223,7 +223,7 @@ DEBUG_MODE_FLAG = no
- endif
- endif
- 
--CFLAGS   += -Wall $(INCLUDE) $(DEBUG_FLAGS) $(CPUOPTS) -msoft-float -mabi=aapcs
-+CFLAGS   += -fno-stack-protector -Wall $(INCLUDE) $(DEBUG_FLAGS) $(CPUOPTS) -msoft-float -mabi=aapcs
- 
- ifeq ($(BOARD),msys_bc2)
- CFLAGS   += -fPIE -fno-zero-initialized-in-bss -fno-unwind-tables
-@@ -231,7 +231,7 @@ else
- CFLAGS   += -fdata-sections -ffunction-sections
- endif
- 
--EXTRA_LD_FLAGS = -Wl,--gc-sections --entry=_start
-+EXTRA_LD_FLAGS = -fno-stack-protector -Wl,--gc-sections --entry=_start
- 
- ifeq ($(DDRTYPE),ddr4)
- CFLAGS += -DCONFIG_DDR4
diff --git a/patch/u-boot/u-boot-armada-next/loading-boot.scr.patch b/patch/u-boot/u-boot-armada-next/loading-boot.scr.patch
deleted file mode 100644
index 914064bdc..000000000
--- a/patch/u-boot/u-boot-armada-next/loading-boot.scr.patch
+++ /dev/null
@@ -1,14 +0,0 @@
-diff --git a/board/mv_ebu/a38x/mv_main_a38x.c b/board/mv_ebu/a38x/mv_main_a38x.c
-index 4b43a9c..5489685 100755
---- a/board/mv_ebu/a38x/mv_main_a38x.c
-+++ b/board/mv_ebu/a38x/mv_main_a38x.c
-@@ -679,7 +679,8 @@ void misc_init_r_env(void)
- #if (CONFIG_BOOTDELAY >= 0)
- 	env = getenv("bootcmd");
- 	if (!env)
--		setenv("bootcmd", "tftpboot 0x2000000 $image_name;tftpboot $fdtaddr $fdtfile;"
-+		setenv("bootcmd", "ext4load mmc 0:1 ${script_addr_r} boot/boot.scr;source ${script_addr_r};"
-+		"tftpboot 0x2000000 $image_name;tftpboot $fdtaddr $fdtfile;"
- 		"setenv bootargs $console $nandEcc $mtdparts $bootargs_root nfsroot=$serverip:$rootpath "
- 		"ip=$ipaddr:$serverip$bootargs_end $mvNetConfig video=dovefb:lcd0:$lcd0_params "
- 		"clcd.lcd0_enable=$lcd0_enable clcd.lcd_panel=$lcd_panel; bootz 0x2000000 - $fdtaddr;");
diff --git a/patch/u-boot/u-boot-armada-next/slot0=mpci_1=sata.patch.disabled b/patch/u-boot/u-boot-armada-next/slot0=mpci_1=sata.patch.disabled
deleted file mode 100644
index 848ee1551..000000000
--- a/patch/u-boot/u-boot-armada-next/slot0=mpci_1=sata.patch.disabled
+++ /dev/null
@@ -1,12 +0,0 @@
-diff --git a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-index 3fb7465..70384a0 100755
---- a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-+++ b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-@@ -89,7 +89,7 @@ SERDES_MAP CustomerBoardTopologyConfig[][MAX_SERDES_LANES] =
- {	/* ClarFog A1 board topology */
- 	{ SATA0,	__3Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },
- 	{ SGMII1,	__1_25Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },
--#if 1
-+#if 0
- 	{ PEX1,	  	__5Gbps,	PEX_ROOT_COMPLEX_x1,		MV_FALSE,	MV_FALSE },
- #else
diff --git a/patch/u-boot/u-boot-armada-next/slot0=sata_1=sata.patch.disabled b/patch/u-boot/u-boot-armada-next/slot0=sata_1=sata.patch.disabled
deleted file mode 100644
index 892ceb043..000000000
--- a/patch/u-boot/u-boot-armada-next/slot0=sata_1=sata.patch.disabled
+++ /dev/null
@@ -1,20 +0,0 @@
-diff --git a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-index 3fb7465..70384a0 100755
---- a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-+++ b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
-@@ -89,13 +89,13 @@ SERDES_MAP CustomerBoardTopologyConfig[][MAX_SERDES_LANES] =
- {	/* ClarFog A1 board topology */
- 	{ SATA0,	__3Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },
- 	{ SGMII1,	__1_25Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },
--#if 1
-+#if 0
- 	{ PEX1,	  	__5Gbps,	PEX_ROOT_COMPLEX_x1,		MV_FALSE,	MV_FALSE },
- #else
- 	{ SATA1,	__3Gbps,	SERDES_DEFAULT_MODE,		MV_TRUE,	MV_FALSE },
- #endif
- 	{ USB3_HOST1,	__5Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },
--#if 1
-+#if 0
- 	{ PEX2,	  	__5Gbps,	PEX_ROOT_COMPLEX_x1,		MV_FALSE,	MV_FALSE },
- #else
- 	{ SATA2,	__3Gbps,	SERDES_DEFAULT_MODE,		MV_TRUE,	MV_FALSE },
diff --git a/patch/u-boot/u-boot-armada-default/compiler.patch b/patch/u-boot/u-boot-armada/compiler.patch
similarity index 100%
rename from patch/u-boot/u-boot-armada-default/compiler.patch
rename to patch/u-boot/u-boot-armada/compiler.patch
diff --git a/patch/u-boot/u-boot-armada-default/loading-boot.scr.patch b/patch/u-boot/u-boot-armada/loading-boot.scr.patch
similarity index 100%
rename from patch/u-boot/u-boot-armada-default/loading-boot.scr.patch
rename to patch/u-boot/u-boot-armada/loading-boot.scr.patch
diff --git a/patch/u-boot/u-boot-armada-default/slot0=mpci_1=sata.patch.disabled b/patch/u-boot/u-boot-armada/slot0=mpci_1=sata.patch.disabled
similarity index 100%
rename from patch/u-boot/u-boot-armada-default/slot0=mpci_1=sata.patch.disabled
rename to patch/u-boot/u-boot-armada/slot0=mpci_1=sata.patch.disabled
diff --git a/patch/u-boot/u-boot-armada-default/slot0=sata_1=sata.patch.disabled b/patch/u-boot/u-boot-armada/slot0=sata_1=sata.patch.disabled
similarity index 100%
rename from patch/u-boot/u-boot-armada-default/slot0=sata_1=sata.patch.disabled
rename to patch/u-boot/u-boot-armada/slot0=sata_1=sata.patch.disabled
diff --git a/patch/u-boot/u-boot-cubox-dev/broken_uboot.patch b/patch/u-boot/u-boot-cubox-dev/broken_uboot.patch
deleted file mode 100644
index 21def986c..000000000
--- a/patch/u-boot/u-boot-cubox-dev/broken_uboot.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-diff --git a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
-old mode 100644
-new mode 100755
-index 7c49f4e..6c92c1d
---- a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
-+++ b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
-@@ -78,9 +78,85 @@ DECLARE_GLOBAL_DATA_PTR;
- 
- int hb_cuboxi_ = 0; /* 2 is HummingBoard2, 1 is HummingBoard, 0 is CuBox-i */
- 
-+/*
-+ * Check memory range for valid RAM. A simple memory test determines
-+ * the actually available RAM size between addresses `base' and
-+ * `base + maxsize'.
-+ * This algorithm uses value MEM_STRIDE (like 128MByte) steps instead of the one bit right shift
-+ * algorithm originally used in get_ram_size() since a 4GByte memory setup in
-+ * a 32bit architecture forbids addressing all the memory, so right shift
-+ * algorithm that assumes total memory size is exponents of 2 would fail.
-+ */
-+#define MEM_STRIDE 0x04000000
-+static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
-+{
-+	volatile u32 *addr;
-+	u32            save[64];
-+	u32            cnt;
-+	long           size;
-+	u32		size_tmp;
-+	int            i = 0;
-+	cnt = maxsize;
-+	/* First save the data */
-+	for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
-+		addr = (volatile u32 *)((u32)base + cnt);	/* pointer arith! */
-+		sync ();
-+		save[i] = *addr;
-+		i++;
-+		sync ();
-+	}
-+	/* First write a signature */
-+	* (volatile u32 *) base = 0x12345678;
-+	for (size_tmp = MEM_STRIDE; size_tmp < (u32)maxsize; size_tmp += MEM_STRIDE) {
-+		long tmp;
-+		* (volatile u32 *)((u32)base + (u32)size_tmp) = (u32)size_tmp;
-+		sync ();
-+		tmp = * (volatile u32 *)((u32)base + (u32)size);
-+		if (tmp == size_tmp) { /* Looks we reached overlapping address */
-+			break;
-+		}
-+	}
-+	/* Resotre the data */
-+	for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
-+		i--;
-+		addr = (volatile u32 *)((u32)base + cnt);	/* pointer arith! */
-+		sync ();
-+		* addr = save[i];
-+		sync ();
-+	}
-+	maxsize = size_tmp;
-+
-+	return (maxsize);
-+}
-+
- int dram_init(void)
- {
--	gd->ram_size = imx_ddr_size();
-+	uint cpurev, imxtype;
-+	u32 sdram_size;
-+
-+	cpurev = get_cpu_rev();
-+	imxtype = (cpurev & 0xFF000) >> 12;
-+
-+	switch (imxtype){
-+	case MXC_CPU_MX6SOLO:
-+		sdram_size = 0x20000000;
-+		break;
-+	case MXC_CPU_MX6Q:
-+	{
-+		/* Read first the snoop control unit config register */
-+		u32 scu_config = *(u32 *)(SCU_BASE_ADDR + 0x4);
-+		if ((scu_config & 0x3) == 0x3) /* Quad core */
-+			sdram_size = 0xf0000000;
-+		else /* Dual core */
-+			sdram_size = 0x40000000;
-+		break;
-+	}
-+	case MXC_CPU_MX6DL:
-+	default:
-+		sdram_size = 0x40000000;
-+		break;
-+	}
-+	gd->ram_size = get_ram_size_stride_test((void *)PHYS_SDRAM, sdram_size);
- 
- 	return 0;
- }
-@@ -624,4 +700,4 @@ int board_late_init(void)
- #endif
- 
- 	return 0;
--}
-+}
-\ No newline at end of file
diff --git a/patch/u-boot/u-boot-cubox-next/broken_uboot.patch b/patch/u-boot/u-boot-cubox-next/broken_uboot.patch
deleted file mode 100644
index 21def986c..000000000
--- a/patch/u-boot/u-boot-cubox-next/broken_uboot.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-diff --git a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
-old mode 100644
-new mode 100755
-index 7c49f4e..6c92c1d
---- a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
-+++ b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
-@@ -78,9 +78,85 @@ DECLARE_GLOBAL_DATA_PTR;
- 
- int hb_cuboxi_ = 0; /* 2 is HummingBoard2, 1 is HummingBoard, 0 is CuBox-i */
- 
-+/*
-+ * Check memory range for valid RAM. A simple memory test determines
-+ * the actually available RAM size between addresses `base' and
-+ * `base + maxsize'.
-+ * This algorithm uses value MEM_STRIDE (like 128MByte) steps instead of the one bit right shift
-+ * algorithm originally used in get_ram_size() since a 4GByte memory setup in
-+ * a 32bit architecture forbids addressing all the memory, so right shift
-+ * algorithm that assumes total memory size is exponents of 2 would fail.
-+ */
-+#define MEM_STRIDE 0x04000000
-+static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
-+{
-+	volatile u32 *addr;
-+	u32            save[64];
-+	u32            cnt;
-+	long           size;
-+	u32		size_tmp;
-+	int            i = 0;
-+	cnt = maxsize;
-+	/* First save the data */
-+	for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
-+		addr = (volatile u32 *)((u32)base + cnt);	/* pointer arith! */
-+		sync ();
-+		save[i] = *addr;
-+		i++;
-+		sync ();
-+	}
-+	/* First write a signature */
-+	* (volatile u32 *) base = 0x12345678;
-+	for (size_tmp = MEM_STRIDE; size_tmp < (u32)maxsize; size_tmp += MEM_STRIDE) {
-+		long tmp;
-+		* (volatile u32 *)((u32)base + (u32)size_tmp) = (u32)size_tmp;
-+		sync ();
-+		tmp = * (volatile u32 *)((u32)base + (u32)size);
-+		if (tmp == size_tmp) { /* Looks we reached overlapping address */
-+			break;
-+		}
-+	}
-+	/* Resotre the data */
-+	for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
-+		i--;
-+		addr = (volatile u32 *)((u32)base + cnt);	/* pointer arith! */
-+		sync ();
-+		* addr = save[i];
-+		sync ();
-+	}
-+	maxsize = size_tmp;
-+
-+	return (maxsize);
-+}
-+
- int dram_init(void)
- {
--	gd->ram_size = imx_ddr_size();
-+	uint cpurev, imxtype;
-+	u32 sdram_size;
-+
-+	cpurev = get_cpu_rev();
-+	imxtype = (cpurev & 0xFF000) >> 12;
-+
-+	switch (imxtype){
-+	case MXC_CPU_MX6SOLO:
-+		sdram_size = 0x20000000;
-+		break;
-+	case MXC_CPU_MX6Q:
-+	{
-+		/* Read first the snoop control unit config register */
-+		u32 scu_config = *(u32 *)(SCU_BASE_ADDR + 0x4);
-+		if ((scu_config & 0x3) == 0x3) /* Quad core */
-+			sdram_size = 0xf0000000;
-+		else /* Dual core */
-+			sdram_size = 0x40000000;
-+		break;
-+	}
-+	case MXC_CPU_MX6DL:
-+	default:
-+		sdram_size = 0x40000000;
-+		break;
-+	}
-+	gd->ram_size = get_ram_size_stride_test((void *)PHYS_SDRAM, sdram_size);
- 
- 	return 0;
- }
-@@ -624,4 +700,4 @@ int board_late_init(void)
- #endif
- 
- 	return 0;
--}
-+}
-\ No newline at end of file
diff --git a/patch/u-boot/u-boot-cubox-default/broken_uboot.patch b/patch/u-boot/u-boot-cubox/broken_uboot.patch
similarity index 100%
rename from patch/u-boot/u-boot-cubox-default/broken_uboot.patch
rename to patch/u-boot/u-boot-cubox/broken_uboot.patch
diff --git a/patch/u-boot/u-boot-default/add-h3-hdmi-driver-jernej.patch b/patch/u-boot/u-boot-default/add-h3-hdmi-driver-jernej.patch
deleted file mode 100644
index 431dbf251..000000000
--- a/patch/u-boot/u-boot-default/add-h3-hdmi-driver-jernej.patch
+++ /dev/null
@@ -1,1494 +0,0 @@
-commit b973987576822640f35dbb805a048b1706dc8e6d
-Author: Jernej Skrabec <jernej.skrabec@siol.net>
-Date:   Tue Nov 8 01:04:32 2016 +0100
-
-    sunxi: video: Add video driver for H3 SoC
-    
-    Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
-
-diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
-index be9fcfd..a414f69 100644
---- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
-+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
-@@ -67,12 +67,20 @@ struct sunxi_ccm_reg {
- 	u32 dram_pll_cfg;	/* 0xf8 PLL_DDR cfg register, A33 only */
- 	u32 mbus_reset;		/* 0xfc MBUS reset control, A33 only */
- 	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
-+#ifdef CONFIG_MACH_SUN8I
-+	u32 de_clk_cfg;		/* 0x104 DE module clock */
-+#else
- 	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
-+#endif
- 	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
- 	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
- 	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
- 	u32 mp_clk_cfg;		/* 0x114 MP module clock */
-+#ifdef CONFIG_MACH_SUN8I
-+	u32 tcon0_clk_cfg;	/* 0x118 TCON0 module clock */
-+#else
- 	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
-+#endif
- 	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
- 	u32 reserved14[3];
- 	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
-@@ -85,7 +93,11 @@ struct sunxi_ccm_reg {
- 	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
- 	u32 reserved15;
- 	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
-+#ifdef CONFIG_MACH_SUN8I
-+	u32 hdmi_slow_clk_cfg;	/* 0x154 HDMI slow module clock */
-+#else
- 	u32 ps_clk_cfg;		/* 0x154 PS module clock */
-+#endif
- 	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
- 	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
- 	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
-@@ -220,6 +232,15 @@ struct sunxi_ccm_reg {
- #define CCM_MIPI_PLL_CTRL_LDO_EN	(0x3 << 22)
- #define CCM_MIPI_PLL_CTRL_EN		(0x1 << 31)
- 
-+#define CCM_PLL10_CTRL_M_SHIFT		0
-+#define CCM_PLL10_CTRL_M_MASK		(0xf << CCM_PLL10_CTRL_M_SHIFT)
-+#define CCM_PLL10_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
-+#define CCM_PLL10_CTRL_N_SHIFT		8
-+#define CCM_PLL10_CTRL_N_MASK		(0x7f << CCM_PLL10_CTRL_N_SHIFT)
-+#define CCM_PLL10_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
-+#define CCM_PLL10_CTRL_INTEGER_MODE	(0x1 << 24)
-+#define CCM_PLL10_CTRL_EN		(0x1 << 31)
-+
- #define CCM_PLL11_CTRL_N(n)		((((n) - 1) & 0x3f) << 8)
- #define CCM_PLL11_CTRL_SIGMA_DELTA_EN	(0x1 << 24)
- #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
-@@ -271,9 +292,12 @@ struct sunxi_ccm_reg {
- #define AHB_GATE_OFFSET_DRC0		25
- #define AHB_GATE_OFFSET_DE_FE0		14
- #define AHB_GATE_OFFSET_DE_BE0		12
-+#define AHB_GATE_OFFSET_DE		12
- #define AHB_GATE_OFFSET_HDMI		11
- #define AHB_GATE_OFFSET_LCD1		5
- #define AHB_GATE_OFFSET_LCD0		4
-+#define AHB_GATE_OFFSET_TCON1		4
-+#define AHB_GATE_OFFSET_TCON0		3
- 
- #define CCM_MMC_CTRL_M(x)		((x) - 1)
- #define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
-@@ -346,6 +370,9 @@ struct sunxi_ccm_reg {
- #define CCM_LCD_CH0_CTRL_RST		0
- #define CCM_LCD_CH0_CTRL_GATE		(0x1 << 31)
- 
-+#define CCM_TCON0_CTRL_GATE		(0x1 << 31)
-+#define CCM_TCON0_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
-+
- #define CCM_LCD_CH1_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
- #define CCM_LCD_CH1_CTRL_HALF_SCLK1	0 /* no seperate sclk1 & 2 on sun6i */
- #define CCM_LCD_CH1_CTRL_PLL3		(0 << 24)
-@@ -355,6 +382,7 @@ struct sunxi_ccm_reg {
- #define CCM_LCD_CH1_CTRL_GATE		(0x1 << 31)
- 
- #define CCM_HDMI_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
-+#define CCM_HDMI_CTRL_M_MASK		(0xf << 0)
- #define CCM_HDMI_CTRL_PLL_MASK		(3 << 24)
- #define CCM_HDMI_CTRL_PLL3		(0 << 24)
- #define CCM_HDMI_CTRL_PLL7		(1 << 24)
-@@ -363,6 +391,8 @@ struct sunxi_ccm_reg {
- #define CCM_HDMI_CTRL_DDC_GATE		(0x1 << 30)
- #define CCM_HDMI_CTRL_GATE		(0x1 << 31)
- 
-+#define CCM_HDMI_SLOW_CTRL_DDC_GATE	(1 << 31)
-+
- #if defined(CONFIG_MACH_SUN50I)
- #define MBUS_CLK_DEFAULT		0x81000002 /* PLL6x2 / 3 */
- #elif defined(CONFIG_MACH_SUN8I)
-@@ -390,9 +420,13 @@ struct sunxi_ccm_reg {
- #define AHB_RESET_OFFSET_DRC0		25
- #define AHB_RESET_OFFSET_DE_FE0		14
- #define AHB_RESET_OFFSET_DE_BE0		12
-+#define AHB_RESET_OFFSET_DE		12
- #define AHB_RESET_OFFSET_HDMI		11
-+#define AHB_RESET_OFFSET_HDMI2		10
- #define AHB_RESET_OFFSET_LCD1		5
- #define AHB_RESET_OFFSET_LCD0		4
-+#define AHB_RESET_OFFSET_TCON1		4
-+#define AHB_RESET_OFFSET_TCON0		3
- 
- /* ahb_reset2 offsets */
- #define AHB_RESET_OFFSET_EPHY		2
-@@ -406,6 +440,7 @@ struct sunxi_ccm_reg {
- 
- /* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
- #define CCM_DE_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
-+#ifndef CONFIG_MACH_SUN8I
- #define CCM_DE_CTRL_PLL_MASK		(0xf << 24)
- #define CCM_DE_CTRL_PLL3		(0 << 24)
- #define CCM_DE_CTRL_PLL7		(1 << 24)
-@@ -413,6 +448,11 @@ struct sunxi_ccm_reg {
- #define CCM_DE_CTRL_PLL8		(3 << 24)
- #define CCM_DE_CTRL_PLL9		(4 << 24)
- #define CCM_DE_CTRL_PLL10		(5 << 24)
-+#else
-+#define CCM_DE_CTRL_PLL_MASK		(3 << 24)
-+#define CCM_DE_CTRL_PLL6_2X		(0 << 24)
-+#define CCM_DE_CTRL_PLL10		(1 << 24)
-+#endif
- #define CCM_DE_CTRL_GATE		(1 << 31)
- 
- /* CCU security switch, H3 only */
-@@ -423,7 +463,9 @@ struct sunxi_ccm_reg {
- #ifndef __ASSEMBLY__
- void clock_set_pll1(unsigned int hz);
- void clock_set_pll3(unsigned int hz);
-+void clock_set_pll3_factors(int m, int n);
- void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
-+void clock_set_pll10(unsigned int hz);
- void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
- void clock_set_mipi_pll(unsigned int hz);
- unsigned int clock_get_pll3(void);
-diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
-index 5f93830..9758a14 100644
---- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
-+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
-@@ -46,7 +46,9 @@
- #define SUNXI_USB1_BASE			0x01c14000
- #endif
- #define SUNXI_SS_BASE			0x01c15000
-+#ifndef CONFIG_MACH_SUN8I_H3
- #define SUNXI_HDMI_BASE			0x01c16000
-+#endif
- #define SUNXI_SPI2_BASE			0x01c17000
- #define SUNXI_SATA_BASE			0x01c18000
- #ifdef CONFIG_SUNXI_GEN_SUN4I
-@@ -163,6 +165,10 @@ defined(CONFIG_MACH_SUN50I)
- #define SUNXI_MP_BASE			0x01e80000
- #define SUNXI_AVG_BASE			0x01ea0000
- 
-+#ifdef CONFIG_MACH_SUN8I_H3
-+#define SUNXI_HDMI_BASE			0x01ee0000
-+#endif
-+
- #define SUNXI_RTC_BASE			0x01f00000
- #define SUNXI_PRCM_BASE			0x01f01400
- 
-diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h
-new file mode 100644
-index 0000000..755adeb
---- /dev/null
-+++ b/arch/arm/include/asm/arch-sunxi/display2.h
-@@ -0,0 +1,261 @@
-+/*
-+ * Sunxi platform display controller register and constant defines
-+ *
-+ * (C) Copyright 2016 Jernej Skrabec <jernej.skrabec@siol.net>
-+ *
-+ * Based on work by:
-+ * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
-+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
-+ * 
-+ * SPDX-License-Identifier:	GPL-2.0+
-+ */
-+
-+#ifndef _SUNXI_DISPLAY_H
-+#define _SUNXI_DISPLAY_H
-+
-+struct sun8i_lcdc_reg {
-+	u32 gctl;
-+	u32 gint0;
-+	u32 gint1;
-+	u32 dum0[13];
-+	u32 tcon0_ctl;				/* 0x40 */
-+	u32 dum1[19];
-+	u32 tcon1_ctl;				/* 0x90 */
-+	u32 basic0;			/* XI/YI */
-+	u32 basic1;			/* LS_XO/LS_YO */
-+	u32 basic2;			/* XO/YO */
-+	u32 basic3;			/* HT/HBP */
-+	u32 basic4;			/* VT/VBP */
-+	u32 basic5;			/* HSPW/VSPW */
-+	u32 dum2;
-+	u32 ps_sync;				/* 0xb0 */
-+	u32 dum3[15];
-+	u32 io_pol;				/* 0xf0 */
-+	u32 io_tri;
-+	u32 dum4[2];
-+
-+	u32 ceu_ctl;				/* 0x100 */
-+	u32 dum5[3];
-+	u32 ceu_rr;
-+	u32 ceu_rg;
-+	u32 ceu_rb;
-+	u32 ceu_rc;
-+	u32 ceu_gr;
-+	u32 ceu_gg;
-+	u32 ceu_gb;
-+	u32 ceu_gc;
-+	u32 ceu_br;
-+	u32 ceu_bg;
-+	u32 ceu_bb;
-+	u32 ceu_bc;
-+	u32 ceu_rv;
-+	u32 ceu_gv;
-+	u32 ceu_bv;
-+	u32 dum6[45];
-+
-+	u32 mux_ctl;				/* 0x200 */
-+	u32 dum7[63];
-+
-+	u32 fill_ctl;				/* 0x300 */
-+	u32 fill_start0;
-+	u32 fill_end0;
-+	u32 fill_data0;
-+};
-+
-+/* global control */
-+struct de_glb {
-+	u32 ctl;
-+#define		DE_MUX_GLB_CTL_rt_en BIT(0)
-+#define		DE_MUX_GLB_CTL_finish_irq_en BIT(4)
-+#define		DE_MUX_GLB_CTL_rtwb_port BIT(12)
-+	u32 status;
-+	u32 dbuff;
-+	u32 size;
-+};
-+
-+/* alpha blending */
-+struct de_bld {
-+	u32 fcolor_ctl;			/* 00 */
-+	struct {
-+		u32 fcolor;
-+		u32 insize;
-+		u32 offset;
-+		u32 dum;
-+	} attr[4];
-+	u32 dum0[15];			/* (end of clear offset) */
-+	u32 route;			/* 80 */
-+	u32 premultiply;
-+	u32 bkcolor;
-+	u32 output_size;
-+	u32 bld_mode[4];
-+	u32 dum1[4];
-+	u32 ck_ctl;			/* b0 */
-+	u32 ck_cfg;
-+	u32 dum2[2];
-+	u32 ck_max[4];			/* c0 */
-+	u32 dum3[4];
-+	u32 ck_min[4];			/* e0 */
-+	u32 dum4[3];
-+	u32 out_ctl;			/* fc */
-+};
-+
-+/* VI channel */
-+struct de_vi {
-+	struct {
-+		u32 attr;
-+#define			VI_CFG_ATTR_en BIT(0)
-+#define			VI_CFG_ATTR_fcolor_en BIT(4)
-+#define			VI_CFG_ATTR_fmt_SHIFT 8
-+#define			VI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
-+#define			VI_CFG_ATTR_ui_sel BIT(15)
-+#define			VI_CFG_ATTR_top_down BIT(23)
-+		u32 size;
-+		u32 coord;
-+#define VI_N_PLANES 3
-+		u32 pitch[VI_N_PLANES];
-+		u32 top_laddr[VI_N_PLANES];
-+		u32 bot_laddr[VI_N_PLANES];
-+	} cfg[4];
-+	u32 fcolor[4];			/* c0 */
-+	u32 top_haddr[VI_N_PLANES];	/* d0 */
-+	u32 bot_haddr[VI_N_PLANES];	/* dc */
-+	u32 ovl_size[2];		/* e8 */
-+	u32 hori[2];			/* f0 */
-+	u32 vert[2];			/* f8 */
-+};
-+
-+struct de_ui {
-+	struct {
-+		u32 attr;
-+#define			UI_CFG_ATTR_en BIT(0)
-+#define			UI_CFG_ATTR_alpmod_SHIFT 1
-+#define			UI_CFG_ATTR_alpmod_MASK GENMASK(2, 1)
-+#define			UI_CFG_ATTR_fcolor_en BIT(4)
-+#define			UI_CFG_ATTR_fmt_SHIFT 8
-+#define			UI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
-+#define			UI_CFG_ATTR_top_down BIT(23)
-+#define			UI_CFG_ATTR_alpha_SHIFT 24
-+#define			UI_CFG_ATTR_alpha_MASK GENMASK(31, 24)
-+		u32 size;
-+		u32 coord;
-+		u32 pitch;
-+		u32 top_laddr;
-+		u32 bot_laddr;
-+		u32 fcolor;
-+		u32 dum;
-+	} cfg[4];			/* 00 */
-+	u32 top_haddr;			/* 80 */
-+	u32 bot_haddr;
-+	u32 ovl_size;			/* 88 */
-+};
-+
-+#define HDMI_EDID_BLOCK_SIZE 			128
-+
-+/*
-+ * HDMI register addresses
-+ */
-+#define SUN8I_HDMI_PHY_CTRL_REG			(u32*)(SUNXI_HDMI_BASE + 0x10020)
-+#define SUN8I_HDMI_PHY_UNK1_REG			(u32*)(SUNXI_HDMI_BASE + 0x10024)
-+#define SUN8I_HDMI_PHY_UNK2_REG			(u32*)(SUNXI_HDMI_BASE + 0x10028)
-+#define SUN8I_HDMI_PHY_PLL_REG			(u32*)(SUNXI_HDMI_BASE + 0x1002c)
-+#define SUN8I_HDMI_PHY_CLK_REG			(u32*)(SUNXI_HDMI_BASE + 0x10030)
-+#define SUN8I_HDMI_PHY_UNK3_REG			(u32*)(SUNXI_HDMI_BASE + 0x10034)
-+#define SUN8I_HDMI_PHY_STATUS_REG		(u32*)(SUNXI_HDMI_BASE + 0x10038)
-+
-+#define SUN8I_HDMI_IH_I2CM_STAT0		(u32*)(SUNXI_HDMI_BASE + 0x0013)
-+
-+#define SUN8I_HDMI_I2CM_SLAVE			(u32*)(SUNXI_HDMI_BASE + 0x0EE0)
-+#define SUN8I_HDMI_I2CM_ADDRESS			(u32*)(SUNXI_HDMI_BASE + 0x0EE1)
-+#define SUN8I_HDMI_I2CM_DATAI			(u32*)(SUNXI_HDMI_BASE + 0x8EE1)
-+#define SUN8I_HDMI_I2CM_OPERATION		(u32*)(SUNXI_HDMI_BASE + 0x0EE2)
-+#define SUN8I_HDMI_I2CM_INT			(u32*)(SUNXI_HDMI_BASE + 0x0EE3)
-+#define SUN8I_HDMI_I2CM_DIV			(u32*)(SUNXI_HDMI_BASE + 0x8EE3)
-+#define SUN8I_HDMI_I2CM_SEGADDR			(u32*)(SUNXI_HDMI_BASE + 0x4EE0)
-+#define SUN8I_HDMI_I2CM_SOFTRSTZ		(u32*)(SUNXI_HDMI_BASE + 0x4EE1)
-+#define SUN8I_HDMI_I2CM_SEGPTR			(u32*)(SUNXI_HDMI_BASE + 0xCEE0)
-+#define SUN8I_HDMI_I2CM_SS_SCL_HCNT_0_ADDR	(u32*)(SUNXI_HDMI_BASE + 0x4EE2)
-+#define SUN8I_HDMI_I2CM_SS_SCL_LCNT_0_ADDR	(u32*)(SUNXI_HDMI_BASE + 0xCEE2)
-+
-+/*
-+ * DE register constants.
-+ */
-+/* TODO: move to appropriate place */
-+#define SUN8I_DE_BASE				0x01000000
-+#define SUN8I_DE_GATE_REG			(u32*)(SUN8I_DE_BASE + 0x0004)
-+#define SUN8I_DE_MOD_REG			(u32*)(SUN8I_DE_BASE + 0x0000)
-+#define SUN8I_DE_RESET_REG			(u32*)(SUN8I_DE_BASE + 0x0008)
-+#define SUN8I_DE_DIV_REG			(u32*)(SUN8I_DE_BASE + 0x000c)
-+#define SUN8I_DE_SEL_REG			(u32*)(SUN8I_DE_BASE + 0x0010)
-+
-+#define DE_MUX0_BASE 				(u8*)(SUN8I_DE_BASE + 0x00100000)
-+/* MUX registers (addr / MUX base) */
-+#define DE_MUX_GLB_REGS 0x00000		/* global control */
-+#define DE_MUX_BLD_REGS 0x01000		/* alpha blending */
-+#define DE_MUX_CHAN_REGS 0x02000	/* VI/UI overlay channels */
-+#define		DE_MUX_CHAN_SZ 0x1000	/* size of a channel */
-+#define DE_MUX_VSU_REGS 0x20000		/* VSU */
-+#define DE_MUX_GSU1_REGS 0x30000	/* GSUs */
-+#define DE_MUX_GSU2_REGS 0x40000
-+#define DE_MUX_GSU3_REGS 0x50000
-+#define DE_MUX_FCE_REGS 0xa0000		/* FCE */
-+#define DE_MUX_BWS_REGS 0xa2000		/* BWS */
-+#define DE_MUX_LTI_REGS 0xa4000		/* LTI */
-+#define DE_MUX_PEAK_REGS 0xa6000	/* PEAK */
-+#define DE_MUX_ASE_REGS 0xa8000		/* ASE */
-+#define DE_MUX_FCC_REGS 0xaa000		/* FCC */
-+#define DE_MUX_DCSC_REGS 0xb0000 /* DCSC/SMBL */
-+
-+#define DE2_FORMAT_ARGB_8888 0
-+#define DE2_FORMAT_BGRA_8888 3
-+#define DE2_FORMAT_XRGB_8888 4
-+#define DE2_FORMAT_RGB_888 8
-+#define DE2_FORMAT_BGR_888 9
-+
-+/* coordinates and sizes */
-+#define XY(x, y) (((y) << 16) | (x))
-+#define WH(w, h) (((h - 1) << 16) | (w - 1))
-+
-+/*
-+ * LCDC register constants.
-+ */
-+#define SUN8I_TCON_GCTL_TCON_En			(1 << 31)
-+#define SUN8I_TCON_GINT0_TCON1_Vb_Int_En	(1 << 30)
-+#define SUN8I_TCON_GINT0_TCON1_Vb_Int_Flag	(1 << 14)
-+#define SUN8I_TCON0_CTL_TCON_En			(1 << 31)
-+#define SUN8I_TCON1_CTL_TCON_En			(1 << 31)
-+#define SUN8I_TCON1_CTL_Interlace_En		(1 << 20)
-+#define SUN8I_TCON1_CTL_Start_Delay_SHIFT	4
-+/*#define SUN8I_TCON1_CTL_Start_Delay_MASK	GENMASK(8, 4)*/
-+#define SUN8I_TCON1_IO_POL_IO0_inv		(1 << 24)
-+#define SUN8I_TCON1_IO_POL_IO1_inv		(1 << 25)
-+#define SUN8I_TCON1_IO_POL_IO2_inv		(1 << 26)
-+#define SUN8I_TCON_CEU_CTL_ceu_en		(1 << 31)
-+
-+#define SUNXI_LCDC_X(x)				(((x) - 1) << 16)
-+#define SUNXI_LCDC_Y(y)				(((y) - 1) << 0)
-+#define SUNXI_LCDC_TCON_VSYNC_MASK		(1 << 24)
-+#define SUNXI_LCDC_TCON_HSYNC_MASK		(1 << 25)
-+#define SUNXI_LCDC_CTRL_IO_MAP_MASK		(1 << 0)
-+#define SUNXI_LCDC_CTRL_IO_MAP_TCON0		(0 << 0)
-+#define SUNXI_LCDC_CTRL_IO_MAP_TCON1		(1 << 0)
-+#define SUNXI_LCDC_CTRL_TCON_ENABLE		(1 << 31)
-+#define SUNXI_LCDC_TCON1_CTRL_SRC_BLUE		(1 << 1)
-+#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
-+#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE	(1 << 20)
-+#define SUNXI_LCDC_TCON1_CTRL_ENABLE		(1 << 31)
-+#define SUNXI_LCDC_TCON1_TIMING_H_BP(n)		(((n) - 1) << 0)
-+#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
-+#define SUNXI_LCDC_TCON1_TIMING_V_BP(n)		(((n) - 1) << 0)
-+#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n)	((n) << 16)
-+
-+/*
-+ * HDMI register constants.
-+ */
-+#define SUNXI_HDMI_HPD_DETECT			(1 << 19)
-+
-+#define SUN8I_HMDI_DDC_CTRL_RESET		(1 << 0)
-+#define SUN8I_HMDI_DDC_ADDR_SLAVE_ADDR		(0x50 << 0)
-+#define SUN8I_HMDI_DDC_ADDR_SEG_ADDR		(0x30 << 0)
-+
-+
-+#endif /* _SUNXI_DISPLAY_H */
-diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
-index ed8cd9b..bcf9aa1 100644
---- a/arch/arm/mach-sunxi/clock_sun6i.c
-+++ b/arch/arm/mach-sunxi/clock_sun6i.c
-@@ -141,6 +141,17 @@ void clock_set_pll3(unsigned int clk)
- 	       &ccm->pll3_cfg);
- }
- 
-+void clock_set_pll3_factors(int m, int n)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+
-+	/* PLL3 rate = 24000000 * n / m */
-+	writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
-+	       CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m),
-+	       &ccm->pll3_cfg);
-+}
-+
- void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
- {
- 	struct sunxi_ccm_reg * const ccm =
-@@ -213,6 +224,23 @@ done:
- }
- #endif
- 
-+void clock_set_pll10(unsigned int clk)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+	const int m = 2; /* 12 MHz steps */
-+
-+	if (clk == 0) {
-+		clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);
-+		return;
-+	}
-+
-+	/* PLL10 rate = 24000000 * n / m */
-+	writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE |
-+	       CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m),
-+	       &ccm->pll10_cfg);
-+}
-+
- #ifdef CONFIG_MACH_SUN8I_A33
- void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
- {
-@@ -267,6 +295,7 @@ unsigned int clock_get_mipi_pll(void)
- 	return ((src / 1000) * n * k / m) * 1000;
- }
- 
-+#ifndef CONFIG_MACH_SUN8I
- void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
- {
- 	int pll = clock_get_pll6() * 2;
-@@ -278,3 +307,4 @@ void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
- 	writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
- 	       clk_cfg);
- }
-+#endif
-diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
-index c0ffeb3..77fdc8f 100644
---- a/board/sunxi/Kconfig
-+++ b/board/sunxi/Kconfig
-@@ -458,7 +458,7 @@ config AXP_GPIO
- 
- config VIDEO
- 	bool "Enable graphical uboot console on HDMI, LCD or VGA"
--	depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
-+	depends on !MACH_SUN8I_A83T && !MACH_SUN9I && !MACH_SUN50I
- 	default y
- 	---help---
- 	Say Y here to add support for using a cfb console on the HDMI, LCD
-@@ -467,7 +467,7 @@ config VIDEO
- 
- config VIDEO_HDMI
- 	bool "HDMI output support"
--	depends on VIDEO && !MACH_SUN8I
-+	depends on VIDEO
- 	default y
- 	---help---
- 	Say Y here to add support for outputting video over HDMI.
-diff --git a/drivers/video/Makefile b/drivers/video/Makefile
-index db34904..d05b745 100644
---- a/drivers/video/Makefile
-+++ b/drivers/video/Makefile
-@@ -52,6 +52,7 @@ obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
- obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
- obj-$(CONFIG_VIDEO_SM501) += sm501.o
- obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
-+obj-$(CONFIG_VIDEO_SUNXI_H3) += sun8i_display.o videomodes.o
- obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
- obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
- obj-$(CONFIG_VIDEO_VESA) += vesa.o
-diff --git a/drivers/video/sun8i_display.c b/drivers/video/sun8i_display.c
-new file mode 100644
-index 0000000..e596e4c
---- /dev/null
-+++ b/drivers/video/sun8i_display.c
-@@ -0,0 +1,928 @@
-+/*
-+ * Display driver for sunxi Allwinner SoCs with DE2.
-+ * 
-+ * Copyright (C) 2016 Jernej Skrabec <jernej.skrabec@siol.net>
-+ *
-+ * Based on sunxi_display.c:
-+ * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
-+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
-+ * 
-+ * Based on Linux DRM driver:
-+ * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
-+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
-+ *
-+ * Based on rk_hdmi.c:
-+ * Copyright (c) 2015 Google, Inc
-+ * Copyright 2014 Rockchip Inc.
-+ * 
-+ * SPDX-License-Identifier:	GPL-2.0+
-+ */
-+
-+#include <common.h>
-+
-+#include <asm/arch/clock.h>
-+#include <asm/arch/display2.h>
-+#include <asm/global_data.h>
-+#include <asm/io.h>
-+#include <errno.h>
-+#include <video_fb.h>
-+#include "videomodes.h"
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+enum sunxi_monitor {
-+	sunxi_monitor_none,
-+	sunxi_monitor_dvi,
-+	sunxi_monitor_hdmi,
-+};
-+#define SUNXI_MONITOR_LAST sunxi_monitor_hdmi
-+
-+struct sunxi_display {
-+	GraphicDevice graphic_device;
-+	enum sunxi_monitor monitor;
-+	unsigned int depth;
-+	unsigned int fb_addr;
-+	unsigned int fb_size;
-+} sunxi_display;
-+
-+#ifdef CONFIG_VIDEO_HDMI
-+
-+static void sun8i_hdmi_phy_init(void)
-+{
-+	unsigned long tmo;
-+	u32 tmp;
-+
-+	writel(0, SUN8I_HDMI_PHY_CTRL_REG);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(0));
-+	udelay(5);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(16));
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(1));
-+	udelay(10);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(2));
-+	udelay(5);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(3));
-+	udelay(40);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(19));
-+	udelay(100);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(18));
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, 7 << 4);
-+
-+	/* Note that Allwinner code doesn't fail in case of timeout  */
-+	tmo = timer_get_us() + 2000;
-+	while ((readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x80) == 0) {
-+		if (timer_get_us() > tmo) {
-+			printf("Warning: HDMI phy init timeout!\n");
-+			break;
-+		}
-+	}
-+
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, 0xf << 8);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(7));
-+
-+	writel(0x39dc5040, SUN8I_HDMI_PHY_PLL_REG);
-+	writel(0x80084343, SUN8I_HDMI_PHY_CLK_REG);
-+	udelay(10000);
-+	writel(1, SUN8I_HDMI_PHY_UNK3_REG);
-+	setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(25));
-+	udelay(100000);
-+	tmp = (readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x1f800) >> 11;
-+	setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(31) | BIT(30));
-+	setbits_le32(SUN8I_HDMI_PHY_PLL_REG, tmp);
-+	writel(0x01FF0F7F, SUN8I_HDMI_PHY_CTRL_REG);
-+	writel(0x80639000, SUN8I_HDMI_PHY_UNK1_REG);
-+	writel(0x0F81C405, SUN8I_HDMI_PHY_UNK2_REG);
-+
-+	/* enable read access to HDMI controller*/
-+	writel(0x54524545, SUNXI_HDMI_BASE + 0x10010);
-+	
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8080);
-+
-+	udelay(1);
-+
-+	writeb(0x00, SUNXI_HDMI_BASE + 0xF01F);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8403);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x904C);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x904E);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0xD04C);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8250);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8A50);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8272);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x40C0);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x86F0);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x0EE3);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8EE2);
-+	writeb(0xf0, SUNXI_HDMI_BASE + 0xA049);
-+	writeb(0x1e, SUNXI_HDMI_BASE + 0xB045);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x00C1);
-+	writeb(0x03, SUNXI_HDMI_BASE + 0x00C1);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x00C0);
-+	writeb(0x10, SUNXI_HDMI_BASE + 0x40C1);
-+	writeb(0xfd, SUNXI_HDMI_BASE + 0x0081);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x0081);
-+	writeb(0xfd, SUNXI_HDMI_BASE + 0x0081);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x0010);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x0011);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8010);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8011);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x0013);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8012);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8013);
-+}
-+
-+static int sun8i_hdmi_hpd_detect(int hpd_delay)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+	unsigned long tmo = timer_get_us() + hpd_delay * 1000;
-+	int status = 0;
-+
-+	/* Set pll3 to 297 MHz */
-+	clock_set_pll3(297000000);
-+
-+	/* Set hdmi parent to pll3 */
-+	clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
-+			CCM_HDMI_CTRL_PLL3);
-+
-+	/* Set ahb gating to pass */
-+	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
-+	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
-+	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
-+	setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
-+
-+	/* Clock on */
-+	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
-+
-+	sun8i_hdmi_phy_init();
-+
-+	while (timer_get_us() < tmo) {
-+		if (readl(SUN8I_HDMI_PHY_STATUS_REG) & SUNXI_HDMI_HPD_DETECT) {
-+			status = 1;
-+			break;
-+		}
-+	}
-+
-+	return status;
-+}
-+
-+static void sunxi_hdmi_shutdown(void)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+
-+	writel(0, SUN8I_HDMI_PHY_CTRL_REG);
-+	clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
-+	clrbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
-+	clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
-+	clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
-+	clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
-+	clock_set_pll3(0);
-+}
-+
-+static int sun8i_hdmi_ddc_wait_i2c_done(int msec)
-+{
-+	u32 val;
-+	ulong start;
-+
-+	start = get_timer(0);
-+	do {
-+		val = readb(SUN8I_HDMI_IH_I2CM_STAT0);
-+		writeb(val, SUN8I_HDMI_IH_I2CM_STAT0);
-+
-+		if (val & 0x2)
-+			return 0;
-+		if (val & 0x1)
-+			return -EIO;
-+
-+		udelay(100);
-+	} while (get_timer(start) < msec);
-+
-+	return 1;
-+}
-+
-+static int sunxi_hdmi_ddc_read(int block, u8 *buf)
-+{
-+	int shift = (block % 2) * 0x80;
-+	int trytime = 5;
-+	int edid_read_err = 0;
-+	u32 op = (block == 0) ? 1 : 2;
-+	int n;
-+
-+	writeb(block >> 1, SUN8I_HDMI_I2CM_SEGPTR);
-+
-+	while (trytime--) {
-+		edid_read_err = 0;
-+
-+		for (n = 0; n < HDMI_EDID_BLOCK_SIZE; n++) {
-+			writeb(shift + n, SUN8I_HDMI_I2CM_ADDRESS);
-+			writeb(op, SUN8I_HDMI_I2CM_OPERATION);
-+
-+			if (sun8i_hdmi_ddc_wait_i2c_done(10)) {
-+				edid_read_err = 1;
-+				break;
-+			}
-+
-+			*buf++ = readb(SUN8I_HDMI_I2CM_DATAI);
-+		}
-+
-+		if (!edid_read_err)
-+			break;
-+	}
-+
-+	return edid_read_err;
-+}
-+
-+static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
-+{
-+	int r, retries = 2;
-+
-+	do {
-+		r = sunxi_hdmi_ddc_read(block, buf);
-+		if (r)
-+			continue;
-+		r = edid_check_checksum(buf);
-+		if (r) {
-+			printf("EDID block %d: checksum error%s\n",
-+			       block, retries ? ", retrying" : "");
-+		}
-+	} while (r && retries--);
-+
-+	return r;
-+}
-+
-+static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
-+{
-+	struct edid1_info edid1;
-+	struct edid_cea861_info cea681[4];
-+	struct edid_detailed_timing *t =
-+		(struct edid_detailed_timing *)edid1.monitor_details.timing;
-+	int i, r, ext_blocks = 0;
-+
-+	/* Reset i2c controller */
-+	writeb(0, SUN8I_HDMI_I2CM_SOFTRSTZ);
-+
-+	writeb(0x05, SUN8I_HDMI_I2CM_DIV);
-+	writeb(0x08, SUN8I_HDMI_I2CM_INT);
-+	writeb(0xd8, SUN8I_HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
-+	writeb(0xfe, SUN8I_HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
-+	writeb(SUN8I_HMDI_DDC_ADDR_SLAVE_ADDR, SUN8I_HDMI_I2CM_SLAVE);
-+	writeb(SUN8I_HMDI_DDC_ADDR_SEG_ADDR, SUN8I_HDMI_I2CM_SEGADDR);
-+
-+	r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
-+	if (r == 0) {
-+		r = edid_check_info(&edid1);
-+		if (r) {
-+			printf("EDID: invalid EDID data\n");
-+			r = -EINVAL;
-+		}
-+	}
-+	if (r == 0) {
-+		ext_blocks = edid1.extension_flag;
-+		if (ext_blocks > 4)
-+			ext_blocks = 4;
-+		for (i = 0; i < ext_blocks; i++) {
-+			if (sunxi_hdmi_edid_get_block(1 + i,
-+						(u8 *)&cea681[i]) != 0) {
-+				ext_blocks = i;
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (r)
-+		return r;
-+
-+	/* We want version 1.3 or 1.2 with detailed timing info */
-+	if (edid1.version != 1 || (edid1.revision < 3 &&
-+			!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
-+		printf("EDID: unsupported version %d.%d\n",
-+		       edid1.version, edid1.revision);
-+		return -EINVAL;
-+	}
-+
-+	/* Take the first usable detailed timing */
-+	for (i = 0; i < 4; i++, t++) {
-+		r = video_edid_dtd_to_ctfb_res_modes(t, mode);
-+		if (r == 0)
-+			break;
-+	}
-+	if (i == 4) {
-+		printf("EDID: no usable detailed timing found\n");
-+		return -ENOENT;
-+	}
-+
-+	/* Check for basic audio support, if found enable hdmi output */
-+	sunxi_display.monitor = sunxi_monitor_dvi;
-+	for (i = 0; i < ext_blocks; i++) {
-+		if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
-+		    cea681[i].revision < 2)
-+			continue;
-+
-+		if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
-+			sunxi_display.monitor = sunxi_monitor_hdmi;
-+	}
-+
-+	return 0;
-+}
-+
-+#endif /* CONFIG_VIDEO_HDMI */
-+
-+/*
-+ * This is the entity that mixes and matches the different layers and inputs.
-+ * Allwinner calls it display engine, but here is called composer.
-+ */
-+static void sunxi_composer_init(void)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+
-+	clock_set_pll10(432000000);
-+	
-+	/* Set DE parent to pll10 */
-+	clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE_CTRL_PLL_MASK,
-+			CCM_DE_CTRL_PLL10);
-+
-+	/* Set ahb gating to pass */
-+	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
-+	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
-+
-+	/* Clock on */
-+	setbits_le32(&ccm->de_clk_cfg, CCM_DE_CTRL_GATE);
-+}
-+
-+static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
-+				    unsigned int address)
-+{
-+	struct de_glb * const de_glb_regs =
-+		(struct de_glb *)(DE_MUX0_BASE + DE_MUX_GLB_REGS);
-+	struct de_bld * const de_bld_regs =
-+		(struct de_bld *)(DE_MUX0_BASE + DE_MUX_BLD_REGS);
-+	struct de_ui * const de_ui_regs =
-+		(struct de_ui *)(DE_MUX0_BASE + DE_MUX_CHAN_REGS +
-+			DE_MUX_CHAN_SZ * 1);
-+	u32 size = WH(mode->xres, mode->yres);
-+	int channel, i;
-+	u32 data;
-+
-+	/* enable clock */
-+	setbits_le32(SUN8I_DE_RESET_REG, 1);
-+	setbits_le32(SUN8I_DE_GATE_REG, 1);
-+	setbits_le32(SUN8I_DE_MOD_REG, 1);
-+	
-+	clrbits_le32(SUN8I_DE_SEL_REG, 1);
-+
-+	writel(DE_MUX_GLB_CTL_rt_en, &de_glb_regs->ctl);
-+	writel(0, &de_glb_regs->status);
-+	writel(1, &de_glb_regs->dbuff);
-+	writel(size, &de_glb_regs->size);
-+
-+	for (channel = 0; channel < 4; channel++) {
-+		void *chan = DE_MUX0_BASE + DE_MUX_CHAN_REGS +
-+			DE_MUX_CHAN_SZ * channel;
-+		memset(chan, 0, channel == 0 ?
-+			sizeof(struct de_vi) : sizeof(struct de_ui));
-+	}
-+
-+	memset(de_bld_regs, 0, 0x44);
-+	writel(0x00000101, &de_bld_regs->fcolor_ctl);
-+
-+	writel(1, &de_bld_regs->route);
-+
-+	writel(0, &de_bld_regs->premultiply);
-+	writel(0xff000000, &de_bld_regs->bkcolor);
-+
-+	writel(0x03010301, &de_bld_regs->bld_mode[0]);
-+	writel(0x03010301, &de_bld_regs->bld_mode[1]);
-+	
-+	writel(size, &de_bld_regs->output_size);
-+	writel(mode->vmode & FB_VMODE_INTERLACED ? 2 : 0,
-+		&de_bld_regs->out_ctl);
-+	writel(0, &de_bld_regs->ck_ctl);
-+
-+	for (i = 0; i < 4; i++) {
-+		writel(0xff000000, &de_bld_regs->attr[i].fcolor);
-+		writel(size, &de_bld_regs->attr[i].insize);
-+	}
-+	
-+	writel(0, DE_MUX0_BASE + DE_MUX_VSU_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_GSU1_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_GSU2_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_GSU3_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_FCE_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_BWS_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_LTI_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_PEAK_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_ASE_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_FCC_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_DCSC_REGS);
-+
-+	data = UI_CFG_ATTR_en | (DE2_FORMAT_XRGB_8888 << UI_CFG_ATTR_fmt_SHIFT) |
-+		(1 << UI_CFG_ATTR_alpmod_SHIFT) | (0xff << UI_CFG_ATTR_alpha_SHIFT);
-+	writel(data, &de_ui_regs->cfg[0].attr);
-+	writel(size, &de_ui_regs->cfg[0].size);
-+	writel(0, &de_ui_regs->cfg[0].coord);
-+	writel(4 * mode->xres, &de_ui_regs->cfg[0].pitch);
-+	writel(address, &de_ui_regs->cfg[0].top_laddr);
-+	writel(size, &de_ui_regs->ovl_size);
-+}
-+
-+static void sunxi_composer_enable(void)
-+{
-+	struct de_glb * const de_glb_regs =
-+		(struct de_glb *)(DE_MUX0_BASE + DE_MUX_GLB_REGS);
-+
-+	writel(1, &de_glb_regs->dbuff);
-+}
-+
-+/*
-+ * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
-+ */
-+static void sunxi_lcdc_pll_set(int dotclock, int *clk_div)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+	int value, n, m, x = 0, diff;
-+	int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
-+
-+	if (dotclock <= 27000)
-+		x = 11;
-+	else if (dotclock <= 74250)
-+		x = 4;
-+	else if (dotclock <= 148500)
-+		x = 2;
-+	else if (dotclock <= 297000)
-+		x = 1;
-+
-+	/*
-+	 * Find the lowest divider resulting in a matching clock, if there
-+	 * is no match, pick the closest lower clock, as monitors tend to
-+	 * not sync to higher frequencies.
-+	 */
-+	for (m = 1; m <= 16; m++) {
-+		n = (m * x * dotclock) / 24000;
-+
-+		if ((n >= 1) && (n <= 128)) {
-+			value = (24000 * n) / m / x;
-+			diff = dotclock - value;
-+			if (diff < best_diff) {
-+				best_diff = diff;
-+				best_m = m;
-+				best_n = n;
-+			}
-+		}
-+	}
-+
-+	clock_set_pll3_factors(best_m, best_n);
-+	printf("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
-+		dotclock, (clock_get_pll3() / 1000) / x,
-+		best_n, best_m, x);
-+
-+	writel(CCM_TCON0_CTRL_GATE | CCM_TCON0_CTRL_M(x),
-+	       &ccm->tcon0_clk_cfg);
-+
-+	*clk_div = x;
-+}
-+
-+static void sunxi_lcdc_init(void)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+	struct sun8i_lcdc_reg * const lcdc =
-+		(struct sun8i_lcdc_reg *)SUNXI_LCD0_BASE;
-+
-+	/* Reset off */
-+	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_TCON0);
-+
-+	/* Clock on */
-+	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TCON0);
-+	setbits_le32(&ccm->tcon0_clk_cfg, CCM_TCON0_CTRL_GATE);
-+
-+	/* Init lcdc */
-+	clrbits_le32(&lcdc->tcon0_ctl, SUN8I_TCON0_CTL_TCON_En); /* Disable tcon0 */
-+	clrbits_le32(&lcdc->gctl, SUN8I_TCON_GCTL_TCON_En); /* Disable tcon globally */
-+	writel(0, &lcdc->gint0); /* Disable all interrupts */
-+
-+	/* Set all io lines to tristate */
-+	writel(0x0fffffff, &lcdc->io_tri);
-+}
-+
-+static void sunxi_lcdc_enable(void)
-+{
-+	struct sun8i_lcdc_reg * const lcdc =
-+		(struct sun8i_lcdc_reg *)SUNXI_LCD0_BASE;
-+
-+	setbits_le32(&lcdc->gctl, SUN8I_TCON_GCTL_TCON_En);
-+}
-+
-+static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode, int tcon)
-+{
-+	int delay;
-+
-+	delay = mode->lower_margin + mode->vsync_len + mode->upper_margin;
-+	if (mode->vmode == FB_VMODE_INTERLACED)
-+		delay /= 2;
-+	if (tcon == 1)
-+		delay -= 2;
-+
-+	return (delay > 31) ? 31 : delay;
-+}
-+
-+#if defined CONFIG_VIDEO_HDMI
-+static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
-+				      int *clk_div)
-+{
-+	struct sun8i_lcdc_reg * const lcdc =
-+		(struct sun8i_lcdc_reg *)SUNXI_LCD0_BASE;
-+	int bp, clk_delay, total, yres;
-+
-+	setbits_le32(&lcdc->gctl, SUN8I_TCON_GCTL_TCON_En);
-+
-+	clk_delay = sunxi_lcdc_get_clk_delay(mode, 1);
-+	writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
-+	       ((mode->vmode == FB_VMODE_INTERLACED) ?
-+			SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
-+	       SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctl);
-+
-+	yres = mode->yres;
-+	if (mode->vmode == FB_VMODE_INTERLACED)
-+		yres /= 2;
-+	writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
-+	       &lcdc->basic0);
-+	writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
-+	       &lcdc->basic1);
-+	writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
-+	       &lcdc->basic2);
-+
-+	bp = mode->hsync_len + mode->left_margin;
-+	total = mode->xres + mode->right_margin + bp;
-+	writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
-+	       SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->basic3);
-+
-+	bp = mode->vsync_len + mode->upper_margin;
-+	total = mode->yres + mode->lower_margin + bp;
-+	if (mode->vmode == FB_VMODE_NONINTERLACED)
-+		total *= 2;
-+	writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
-+	       SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->basic4);
-+
-+	writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
-+	       &lcdc->basic5);
-+
-+	writel(0, &lcdc->ceu_ctl);
-+	writel(0, &lcdc->fill_ctl);
-+
-+	sunxi_lcdc_pll_set(mode->pixclock_khz, clk_div);
-+}
-+#endif /* CONFIG_VIDEO_HDMI */
-+
-+#ifdef CONFIG_VIDEO_HDMI
-+
-+static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
-+{
-+	u8 tmp;
-+
-+	if (mode->pixclock_khz <= 27000)
-+		tmp = 0x40; /* SD-modes, ITU601 colorspace */
-+	else
-+		tmp = 0x80; /* HD-modes, ITU709 colorspace */
-+
-+	if (mode->xres * 100 / mode->yres < 156)
-+		tmp |= 0x18;  /* 4 : 3 */
-+	else
-+		tmp |= 0x28; /* 16 : 9 */
-+
-+	setbits_8(SUNXI_HDMI_BASE + 0x0040, 0x08);
-+	writeb(0x60, SUNXI_HDMI_BASE + 0x4045);
-+	writeb(tmp, SUNXI_HDMI_BASE + 0xC044);
-+	writeb(0x88, SUNXI_HDMI_BASE + 0xC045);
-+}
-+
-+static int hdmi_phy_set(u32 divider)
-+{
-+	u32 tmp;
-+
-+	switch(divider)
-+	{
-+		case 1:
-+			writel(0x30dc5fc0, SUN8I_HDMI_PHY_PLL_REG);
-+			writel(0x800863C0, SUN8I_HDMI_PHY_CLK_REG);
-+			mdelay(10);
-+			writel(0x00000001, SUN8I_HDMI_PHY_UNK3_REG);
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(25));
-+			mdelay(200);
-+			tmp = (readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x1f800) >> 11;
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(31) | BIT(30));
-+			if (tmp < 0x3d)
-+				setbits_le32(SUN8I_HDMI_PHY_PLL_REG, tmp + 2);
-+			else
-+				setbits_le32(SUN8I_HDMI_PHY_PLL_REG, 0x3f);
-+			mdelay(100);
-+			writel(0x01FFFF7F, SUN8I_HDMI_PHY_CTRL_REG);
-+			writel(0x8063b000, SUN8I_HDMI_PHY_UNK1_REG);
-+			writel(0x0F8246B5, SUN8I_HDMI_PHY_UNK2_REG);
-+			break;
-+		case 2:
-+			writel(0x39dc5040, SUN8I_HDMI_PHY_PLL_REG);
-+			writel(0x80084381, SUN8I_HDMI_PHY_CLK_REG);
-+			mdelay(10);
-+			writel(0x00000001, SUN8I_HDMI_PHY_UNK3_REG);
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(25));
-+			mdelay(100);
-+			tmp = (readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x1f800) >> 11;
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(31) | BIT(30));
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, tmp);
-+			writel(0x01FFFF7F, SUN8I_HDMI_PHY_CTRL_REG);
-+			writel(0x8063a800, SUN8I_HDMI_PHY_UNK1_REG);
-+			writel(0x0F81C485, SUN8I_HDMI_PHY_UNK2_REG);
-+			break;
-+		case 4:
-+			writel(0x39dc5040, SUN8I_HDMI_PHY_PLL_REG);
-+			writel(0x80084343, SUN8I_HDMI_PHY_CLK_REG);
-+			mdelay(10);
-+			writel(0x00000001, SUN8I_HDMI_PHY_UNK3_REG);
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(25));
-+			mdelay(100);
-+			tmp = (readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x1f800) >> 11;
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(31) | BIT(30));
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, tmp);
-+			writel(0x01FFFF7F, SUN8I_HDMI_PHY_CTRL_REG);
-+			writel(0x8063b000, SUN8I_HDMI_PHY_UNK1_REG);
-+			writel(0x0F81C405, SUN8I_HDMI_PHY_UNK2_REG);
-+			break;
-+		case 11:
-+			writel(0x39dc5040, SUN8I_HDMI_PHY_PLL_REG);
-+			writel(0x8008430a, SUN8I_HDMI_PHY_CLK_REG);
-+			mdelay(10);
-+			writel(0x00000001, SUN8I_HDMI_PHY_UNK3_REG);
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(25));
-+			mdelay(100);
-+			tmp = (readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x1f800) >> 11;
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(31) | BIT(30));
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, tmp);
-+			writel(0x01FFFF7F, SUN8I_HDMI_PHY_CTRL_REG);
-+			writel(0x8063b000, SUN8I_HDMI_PHY_UNK1_REG);
-+			writel(0x0F81C405, SUN8I_HDMI_PHY_UNK2_REG);
-+			break;
-+		default:
-+			return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
-+				int clk_div)
-+{
-+	u8 invidconf, v_blanking;
-+	u32 h_blanking;
-+
-+	if(hdmi_phy_set(clk_div) != 0) {
-+		printf("HDMI divider is invalid!\n");
-+		return;
-+	}
-+	
-+	invidconf = 0;
-+	if(mode->vmode & FB_VMODE_INTERLACED)
-+		invidconf |= 0x01;
-+	if(mode->sync & FB_SYNC_HOR_HIGH_ACT)
-+		invidconf |= 0x20;
-+	if(mode->sync & FB_SYNC_VERT_HIGH_ACT)
-+		invidconf |= 0x40;
-+
-+	h_blanking = mode->left_margin + mode->right_margin + mode->hsync_len;
-+	v_blanking = mode->upper_margin + mode->lower_margin + mode->vsync_len;
-+
-+	writeb(invidconf | 0x10, SUNXI_HDMI_BASE + 0x0040);
-+	writeb(((invidconf < 96) ? 0x03 : 0x00), SUNXI_HDMI_BASE + 0x10001);
-+
-+	writeb(mode->xres >> 8, SUNXI_HDMI_BASE + 0x8040);
-+	writeb(mode->xres, SUNXI_HDMI_BASE + 0x0041);
-+	writeb(mode->yres >> 8, SUNXI_HDMI_BASE + 0x8042);
-+	writeb(mode->yres, SUNXI_HDMI_BASE + 0x0043);
-+	writeb(mode->vsync_len, SUNXI_HDMI_BASE + 0x4043);
-+	writeb(h_blanking >> 8, SUNXI_HDMI_BASE + 0x0042);
-+	writeb(h_blanking, SUNXI_HDMI_BASE + 0x8041);
-+	writeb(mode->lower_margin, SUNXI_HDMI_BASE + 0x4042);
-+	writeb(mode->right_margin >> 8, SUNXI_HDMI_BASE + 0x4041);
-+	writeb(mode->right_margin, SUNXI_HDMI_BASE + 0x4040);
-+	writeb(mode->hsync_len >> 8, SUNXI_HDMI_BASE + 0xC041);
-+	writeb(mode->hsync_len, SUNXI_HDMI_BASE + 0xC040);
-+	writeb(v_blanking, SUNXI_HDMI_BASE + 0x8043);
-+
-+	writeb(0x0c, SUNXI_HDMI_BASE + 0x0045);
-+	writeb(0x20, SUNXI_HDMI_BASE + 0x8044);
-+	writeb(0x01, SUNXI_HDMI_BASE + 0x8045);
-+	writeb(0x0b, SUNXI_HDMI_BASE + 0x0046);
-+	writeb(0x16, SUNXI_HDMI_BASE + 0x0047);
-+	writeb(0x21, SUNXI_HDMI_BASE + 0x8046);
-+
-+	writeb(0x40, SUNXI_HDMI_BASE + 0x0401);
-+	writeb(0x07, SUNXI_HDMI_BASE + 0x8400);
-+
-+	// default value, written 0 by rk_hdmi
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8401);
-+
-+	writeb(0x47, SUNXI_HDMI_BASE + 0x0402);
-+	writeb(0x01, SUNXI_HDMI_BASE + 0x0800);
-+	writeb(0x07, SUNXI_HDMI_BASE + 0x0801);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8800);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8801);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x0802);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x0803);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8802);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8803);
-+
-+	if (sunxi_display.monitor == sunxi_monitor_hdmi)
-+		sunxi_hdmi_setup_info_frames(mode);
-+
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x0082);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x0081);
-+}
-+
-+static void sunxi_hdmi_enable(void)
-+{
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, 0xf << 12);
-+	printf("hdmi enabled\n");
-+}
-+
-+#endif /* CONFIG_VIDEO_HDMI */
-+ 
-+static void sunxi_engines_init(void)
-+{
-+	sunxi_composer_init();
-+	sunxi_lcdc_init();
-+}
-+ 
-+static void sunxi_mode_set(const struct ctfb_res_modes *mode,
-+			   unsigned int address)
-+{
-+	int __maybe_unused clk_div;
-+
-+	switch (sunxi_display.monitor) {
-+	case sunxi_monitor_none:
-+		break;
-+	case sunxi_monitor_dvi:
-+	case sunxi_monitor_hdmi:
-+#ifdef CONFIG_VIDEO_HDMI
-+		sunxi_composer_mode_set(mode, address);
-+		sunxi_lcdc_tcon0_mode_set(mode, &clk_div);
-+		sunxi_hdmi_mode_set(mode, clk_div);
-+		sunxi_composer_enable();
-+		sunxi_lcdc_enable();
-+		sunxi_hdmi_enable();
-+#endif
-+		break;
-+	}
-+}
-+
-+static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
-+{
-+	switch (monitor) {
-+	case sunxi_monitor_none:		return "none";
-+	case sunxi_monitor_dvi:			return "dvi";
-+	case sunxi_monitor_hdmi:		return "hdmi";
-+	}
-+	return NULL; /* never reached */
-+}
-+
-+ulong board_get_usable_ram_top(ulong total_size)
-+{
-+	return gd->ram_top - CONFIG_SUNXI_MAX_FB_SIZE;
-+}
-+
-+static bool sunxi_has_hdmi(void)
-+{
-+#ifdef CONFIG_VIDEO_HDMI
-+	return true;
-+#else
-+	return false;
-+#endif
-+}
-+
-+static enum sunxi_monitor sunxi_get_default_mon(bool allow_hdmi)
-+{
-+	if (allow_hdmi && sunxi_has_hdmi())
-+		return sunxi_monitor_dvi;
-+	else
-+		return sunxi_monitor_none;
-+}
-+
-+void *video_hw_init(void)
-+{
-+	static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
-+	const struct ctfb_res_modes *mode;
-+	struct ctfb_res_modes custom;
-+	const char *options;
-+#ifdef CONFIG_VIDEO_HDMI
-+	int ret, hpd, hpd_delay, edid;
-+#endif
-+	int i, overscan_offset, overscan_x, overscan_y;
-+	unsigned int fb_dma_addr;
-+	char mon[16];
-+
-+	memset(&sunxi_display, 0, sizeof(struct sunxi_display));
-+
-+	video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
-+				 &sunxi_display.depth, &options);
-+#ifdef CONFIG_VIDEO_HDMI
-+	hpd = video_get_option_int(options, "hpd", 1);
-+	hpd_delay = video_get_option_int(options, "hpd_delay", 500);
-+	edid = video_get_option_int(options, "edid", 1);
-+#endif
-+	overscan_x = video_get_option_int(options, "overscan_x", -1);
-+	overscan_y = video_get_option_int(options, "overscan_y", -1);
-+	sunxi_display.monitor = sunxi_get_default_mon(true);
-+	video_get_option_string(options, "monitor", mon, sizeof(mon),
-+				sunxi_get_mon_desc(sunxi_display.monitor));
-+	for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
-+		if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
-+			sunxi_display.monitor = i;
-+			break;
-+		}
-+	}
-+	if (i > SUNXI_MONITOR_LAST)
-+		printf("Unknown monitor: '%s', falling back to '%s'\n",
-+		       mon, sunxi_get_mon_desc(sunxi_display.monitor));
-+
-+#ifdef CONFIG_VIDEO_HDMI
-+	/* If HDMI/DVI is selected do HPD & EDID, and handle fallback */
-+	if (sunxi_display.monitor == sunxi_monitor_dvi ||
-+	    sunxi_display.monitor == sunxi_monitor_hdmi) {
-+		/* Always call hdp_detect, as it also enables clocks, etc. */
-+		ret = sun8i_hdmi_hpd_detect(hpd_delay);
-+		if (ret) {
-+			printf("HDMI connected: ");
-+			if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
-+				mode = &custom;
-+		} else if (hpd) {
-+			sunxi_hdmi_shutdown();
-+			sunxi_display.monitor = sunxi_get_default_mon(false);
-+		} /* else continue with hdmi/dvi without a cable connected */
-+	}
-+#endif
-+
-+	switch (sunxi_display.monitor) {
-+	case sunxi_monitor_none:
-+		return NULL;
-+	case sunxi_monitor_dvi:
-+	case sunxi_monitor_hdmi:
-+		if (!sunxi_has_hdmi()) {
-+			printf("HDMI/DVI not supported on this board\n");
-+			sunxi_display.monitor = sunxi_monitor_none;
-+			return NULL;
-+		}
-+		break;
-+	}
-+
-+	if (overscan_x == -1)
-+		overscan_x = 0;
-+	if (overscan_y == -1)
-+		overscan_y = 0;
-+
-+	sunxi_display.fb_size =
-+		(mode->xres * mode->yres * 4 + 0xfff) & ~0xfff;
-+	overscan_offset = (overscan_y * mode->xres + overscan_x) * 4;
-+	/* We want to keep the fb_base for simplefb page aligned, where as
-+	 * the sunxi dma engines will happily accept an unaligned address. */
-+	if (overscan_offset)
-+		sunxi_display.fb_size += 0x1000;
-+
-+	if (sunxi_display.fb_size > CONFIG_SUNXI_MAX_FB_SIZE) {
-+		printf("Error need %dkB for fb, but only %dkB is reserved\n",
-+		       sunxi_display.fb_size >> 10,
-+		       CONFIG_SUNXI_MAX_FB_SIZE >> 10);
-+		return NULL;
-+	}
-+
-+	printf("Setting up a %dx%d%s %s console (overscan %dx%d)\n",
-+	       mode->xres, mode->yres,
-+	       (mode->vmode == FB_VMODE_INTERLACED) ? "i" : "",
-+	       sunxi_get_mon_desc(sunxi_display.monitor),
-+	       overscan_x, overscan_y);
-+
-+	gd->fb_base = gd->bd->bi_dram[0].start +
-+		      gd->bd->bi_dram[0].size - sunxi_display.fb_size;
-+	sunxi_engines_init();
-+
-+	fb_dma_addr = gd->fb_base;
-+	sunxi_display.fb_addr = gd->fb_base;
-+	if (overscan_offset) {
-+		fb_dma_addr += 0x1000 - (overscan_offset & 0xfff);
-+		sunxi_display.fb_addr += (overscan_offset + 0xfff) & ~0xfff;
-+		memset((void *)gd->fb_base, 0, sunxi_display.fb_size);
-+		flush_cache(gd->fb_base, sunxi_display.fb_size);
-+	}
-+	sunxi_mode_set(mode, fb_dma_addr);
-+
-+	/*
-+	 * These are the only members of this structure that are used. All the
-+	 * others are driver specific. The pitch is stored in plnSizeX.
-+	 */
-+	graphic_device->frameAdrs = sunxi_display.fb_addr;
-+	graphic_device->gdfIndex = GDF_32BIT_X888RGB;
-+	graphic_device->gdfBytesPP = 4;
-+	graphic_device->winSizeX = mode->xres - 2 * overscan_x;
-+	graphic_device->winSizeY = mode->yres - 2 * overscan_y;
-+	graphic_device->plnSizeX = mode->xres * graphic_device->gdfBytesPP;
-+
-+	return graphic_device;
-+}
-diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
-index e0464df..c63c1bc 100644
---- a/include/configs/sunxi-common.h
-+++ b/include/configs/sunxi-common.h
-@@ -284,9 +284,13 @@ extern int soft_i2c_gpio_scl;
- #define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20)
- 
- /* Do we want to initialize a simple FB? */
-+#ifndef CONFIG_MACH_SUN8I_H3
- #define CONFIG_VIDEO_DT_SIMPLEFB
- 
- #define CONFIG_VIDEO_SUNXI
-+#else
-+#define CONFIG_VIDEO_SUNXI_H3
-+#endif
- 
- #define CONFIG_VIDEO_LOGO
- #define CONFIG_VIDEO_STD_TIMINGS
-diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
-index 11b5a22..cef476f 100644
---- a/scripts/config_whitelist.txt
-+++ b/scripts/config_whitelist.txt
-@@ -8270,6 +8270,7 @@ CONFIG_VIDEO_SM501_8BPP
- CONFIG_VIDEO_SM501_PCI
- CONFIG_VIDEO_STD_TIMINGS
- CONFIG_VIDEO_SUNXI
-+CONFIG_VIDEO_SUNXI_H3
- CONFIG_VIDEO_VCXK
- CONFIG_VID_FLS_ENV
- CONFIG_VM86
diff --git a/patch/u-boot/u-boot-dev/add-awsom-uboot.patch b/patch/u-boot/u-boot-dev/add-awsom-uboot.patch
deleted file mode 100644
index 578d6df3d..000000000
--- a/patch/u-boot/u-boot-dev/add-awsom-uboot.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-===================================================================
---- /dev/null
-+++ u-boot-2015.01/configs/Awsom_defconfig
-@@ -0,0 +1,23 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_MACH_SUN7I=y
-+CONFIG_DRAM_CLK=480
-+CONFIG_DRAM_ZQ=127
-+CONFIG_DRAM_EMR1=4
-+CONFIG_MMC0_CD_PIN="PB9"
-+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_SPL=y
-+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
-+CONFIG_HUSH_PARSER=y
-+CONFIG_CMD_BOOTZ=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_CMD_FPGA is not set
-+CONFIG_CMD_DHCP=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_I2C=y
-+CONFIG_DM_ETH=y
-+CONFIG_ETH_DESIGNWARE=y
-+CONFIG_DM_SERIAL=y
-+CONFIG_USB=y
-+CONFIG_DM_USB=y
diff --git a/patch/u-boot/u-boot-dev/add-h3-hdmi-driver-jernej.patch b/patch/u-boot/u-boot-dev/add-h3-hdmi-driver-jernej.patch
deleted file mode 100644
index 431dbf251..000000000
--- a/patch/u-boot/u-boot-dev/add-h3-hdmi-driver-jernej.patch
+++ /dev/null
@@ -1,1494 +0,0 @@
-commit b973987576822640f35dbb805a048b1706dc8e6d
-Author: Jernej Skrabec <jernej.skrabec@siol.net>
-Date:   Tue Nov 8 01:04:32 2016 +0100
-
-    sunxi: video: Add video driver for H3 SoC
-    
-    Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
-
-diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
-index be9fcfd..a414f69 100644
---- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
-+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
-@@ -67,12 +67,20 @@ struct sunxi_ccm_reg {
- 	u32 dram_pll_cfg;	/* 0xf8 PLL_DDR cfg register, A33 only */
- 	u32 mbus_reset;		/* 0xfc MBUS reset control, A33 only */
- 	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
-+#ifdef CONFIG_MACH_SUN8I
-+	u32 de_clk_cfg;		/* 0x104 DE module clock */
-+#else
- 	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
-+#endif
- 	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
- 	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
- 	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
- 	u32 mp_clk_cfg;		/* 0x114 MP module clock */
-+#ifdef CONFIG_MACH_SUN8I
-+	u32 tcon0_clk_cfg;	/* 0x118 TCON0 module clock */
-+#else
- 	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
-+#endif
- 	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
- 	u32 reserved14[3];
- 	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
-@@ -85,7 +93,11 @@ struct sunxi_ccm_reg {
- 	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
- 	u32 reserved15;
- 	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
-+#ifdef CONFIG_MACH_SUN8I
-+	u32 hdmi_slow_clk_cfg;	/* 0x154 HDMI slow module clock */
-+#else
- 	u32 ps_clk_cfg;		/* 0x154 PS module clock */
-+#endif
- 	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
- 	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
- 	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
-@@ -220,6 +232,15 @@ struct sunxi_ccm_reg {
- #define CCM_MIPI_PLL_CTRL_LDO_EN	(0x3 << 22)
- #define CCM_MIPI_PLL_CTRL_EN		(0x1 << 31)
- 
-+#define CCM_PLL10_CTRL_M_SHIFT		0
-+#define CCM_PLL10_CTRL_M_MASK		(0xf << CCM_PLL10_CTRL_M_SHIFT)
-+#define CCM_PLL10_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
-+#define CCM_PLL10_CTRL_N_SHIFT		8
-+#define CCM_PLL10_CTRL_N_MASK		(0x7f << CCM_PLL10_CTRL_N_SHIFT)
-+#define CCM_PLL10_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
-+#define CCM_PLL10_CTRL_INTEGER_MODE	(0x1 << 24)
-+#define CCM_PLL10_CTRL_EN		(0x1 << 31)
-+
- #define CCM_PLL11_CTRL_N(n)		((((n) - 1) & 0x3f) << 8)
- #define CCM_PLL11_CTRL_SIGMA_DELTA_EN	(0x1 << 24)
- #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
-@@ -271,9 +292,12 @@ struct sunxi_ccm_reg {
- #define AHB_GATE_OFFSET_DRC0		25
- #define AHB_GATE_OFFSET_DE_FE0		14
- #define AHB_GATE_OFFSET_DE_BE0		12
-+#define AHB_GATE_OFFSET_DE		12
- #define AHB_GATE_OFFSET_HDMI		11
- #define AHB_GATE_OFFSET_LCD1		5
- #define AHB_GATE_OFFSET_LCD0		4
-+#define AHB_GATE_OFFSET_TCON1		4
-+#define AHB_GATE_OFFSET_TCON0		3
- 
- #define CCM_MMC_CTRL_M(x)		((x) - 1)
- #define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
-@@ -346,6 +370,9 @@ struct sunxi_ccm_reg {
- #define CCM_LCD_CH0_CTRL_RST		0
- #define CCM_LCD_CH0_CTRL_GATE		(0x1 << 31)
- 
-+#define CCM_TCON0_CTRL_GATE		(0x1 << 31)
-+#define CCM_TCON0_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
-+
- #define CCM_LCD_CH1_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
- #define CCM_LCD_CH1_CTRL_HALF_SCLK1	0 /* no seperate sclk1 & 2 on sun6i */
- #define CCM_LCD_CH1_CTRL_PLL3		(0 << 24)
-@@ -355,6 +382,7 @@ struct sunxi_ccm_reg {
- #define CCM_LCD_CH1_CTRL_GATE		(0x1 << 31)
- 
- #define CCM_HDMI_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
-+#define CCM_HDMI_CTRL_M_MASK		(0xf << 0)
- #define CCM_HDMI_CTRL_PLL_MASK		(3 << 24)
- #define CCM_HDMI_CTRL_PLL3		(0 << 24)
- #define CCM_HDMI_CTRL_PLL7		(1 << 24)
-@@ -363,6 +391,8 @@ struct sunxi_ccm_reg {
- #define CCM_HDMI_CTRL_DDC_GATE		(0x1 << 30)
- #define CCM_HDMI_CTRL_GATE		(0x1 << 31)
- 
-+#define CCM_HDMI_SLOW_CTRL_DDC_GATE	(1 << 31)
-+
- #if defined(CONFIG_MACH_SUN50I)
- #define MBUS_CLK_DEFAULT		0x81000002 /* PLL6x2 / 3 */
- #elif defined(CONFIG_MACH_SUN8I)
-@@ -390,9 +420,13 @@ struct sunxi_ccm_reg {
- #define AHB_RESET_OFFSET_DRC0		25
- #define AHB_RESET_OFFSET_DE_FE0		14
- #define AHB_RESET_OFFSET_DE_BE0		12
-+#define AHB_RESET_OFFSET_DE		12
- #define AHB_RESET_OFFSET_HDMI		11
-+#define AHB_RESET_OFFSET_HDMI2		10
- #define AHB_RESET_OFFSET_LCD1		5
- #define AHB_RESET_OFFSET_LCD0		4
-+#define AHB_RESET_OFFSET_TCON1		4
-+#define AHB_RESET_OFFSET_TCON0		3
- 
- /* ahb_reset2 offsets */
- #define AHB_RESET_OFFSET_EPHY		2
-@@ -406,6 +440,7 @@ struct sunxi_ccm_reg {
- 
- /* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
- #define CCM_DE_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
-+#ifndef CONFIG_MACH_SUN8I
- #define CCM_DE_CTRL_PLL_MASK		(0xf << 24)
- #define CCM_DE_CTRL_PLL3		(0 << 24)
- #define CCM_DE_CTRL_PLL7		(1 << 24)
-@@ -413,6 +448,11 @@ struct sunxi_ccm_reg {
- #define CCM_DE_CTRL_PLL8		(3 << 24)
- #define CCM_DE_CTRL_PLL9		(4 << 24)
- #define CCM_DE_CTRL_PLL10		(5 << 24)
-+#else
-+#define CCM_DE_CTRL_PLL_MASK		(3 << 24)
-+#define CCM_DE_CTRL_PLL6_2X		(0 << 24)
-+#define CCM_DE_CTRL_PLL10		(1 << 24)
-+#endif
- #define CCM_DE_CTRL_GATE		(1 << 31)
- 
- /* CCU security switch, H3 only */
-@@ -423,7 +463,9 @@ struct sunxi_ccm_reg {
- #ifndef __ASSEMBLY__
- void clock_set_pll1(unsigned int hz);
- void clock_set_pll3(unsigned int hz);
-+void clock_set_pll3_factors(int m, int n);
- void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
-+void clock_set_pll10(unsigned int hz);
- void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
- void clock_set_mipi_pll(unsigned int hz);
- unsigned int clock_get_pll3(void);
-diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
-index 5f93830..9758a14 100644
---- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
-+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
-@@ -46,7 +46,9 @@
- #define SUNXI_USB1_BASE			0x01c14000
- #endif
- #define SUNXI_SS_BASE			0x01c15000
-+#ifndef CONFIG_MACH_SUN8I_H3
- #define SUNXI_HDMI_BASE			0x01c16000
-+#endif
- #define SUNXI_SPI2_BASE			0x01c17000
- #define SUNXI_SATA_BASE			0x01c18000
- #ifdef CONFIG_SUNXI_GEN_SUN4I
-@@ -163,6 +165,10 @@ defined(CONFIG_MACH_SUN50I)
- #define SUNXI_MP_BASE			0x01e80000
- #define SUNXI_AVG_BASE			0x01ea0000
- 
-+#ifdef CONFIG_MACH_SUN8I_H3
-+#define SUNXI_HDMI_BASE			0x01ee0000
-+#endif
-+
- #define SUNXI_RTC_BASE			0x01f00000
- #define SUNXI_PRCM_BASE			0x01f01400
- 
-diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h
-new file mode 100644
-index 0000000..755adeb
---- /dev/null
-+++ b/arch/arm/include/asm/arch-sunxi/display2.h
-@@ -0,0 +1,261 @@
-+/*
-+ * Sunxi platform display controller register and constant defines
-+ *
-+ * (C) Copyright 2016 Jernej Skrabec <jernej.skrabec@siol.net>
-+ *
-+ * Based on work by:
-+ * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
-+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
-+ * 
-+ * SPDX-License-Identifier:	GPL-2.0+
-+ */
-+
-+#ifndef _SUNXI_DISPLAY_H
-+#define _SUNXI_DISPLAY_H
-+
-+struct sun8i_lcdc_reg {
-+	u32 gctl;
-+	u32 gint0;
-+	u32 gint1;
-+	u32 dum0[13];
-+	u32 tcon0_ctl;				/* 0x40 */
-+	u32 dum1[19];
-+	u32 tcon1_ctl;				/* 0x90 */
-+	u32 basic0;			/* XI/YI */
-+	u32 basic1;			/* LS_XO/LS_YO */
-+	u32 basic2;			/* XO/YO */
-+	u32 basic3;			/* HT/HBP */
-+	u32 basic4;			/* VT/VBP */
-+	u32 basic5;			/* HSPW/VSPW */
-+	u32 dum2;
-+	u32 ps_sync;				/* 0xb0 */
-+	u32 dum3[15];
-+	u32 io_pol;				/* 0xf0 */
-+	u32 io_tri;
-+	u32 dum4[2];
-+
-+	u32 ceu_ctl;				/* 0x100 */
-+	u32 dum5[3];
-+	u32 ceu_rr;
-+	u32 ceu_rg;
-+	u32 ceu_rb;
-+	u32 ceu_rc;
-+	u32 ceu_gr;
-+	u32 ceu_gg;
-+	u32 ceu_gb;
-+	u32 ceu_gc;
-+	u32 ceu_br;
-+	u32 ceu_bg;
-+	u32 ceu_bb;
-+	u32 ceu_bc;
-+	u32 ceu_rv;
-+	u32 ceu_gv;
-+	u32 ceu_bv;
-+	u32 dum6[45];
-+
-+	u32 mux_ctl;				/* 0x200 */
-+	u32 dum7[63];
-+
-+	u32 fill_ctl;				/* 0x300 */
-+	u32 fill_start0;
-+	u32 fill_end0;
-+	u32 fill_data0;
-+};
-+
-+/* global control */
-+struct de_glb {
-+	u32 ctl;
-+#define		DE_MUX_GLB_CTL_rt_en BIT(0)
-+#define		DE_MUX_GLB_CTL_finish_irq_en BIT(4)
-+#define		DE_MUX_GLB_CTL_rtwb_port BIT(12)
-+	u32 status;
-+	u32 dbuff;
-+	u32 size;
-+};
-+
-+/* alpha blending */
-+struct de_bld {
-+	u32 fcolor_ctl;			/* 00 */
-+	struct {
-+		u32 fcolor;
-+		u32 insize;
-+		u32 offset;
-+		u32 dum;
-+	} attr[4];
-+	u32 dum0[15];			/* (end of clear offset) */
-+	u32 route;			/* 80 */
-+	u32 premultiply;
-+	u32 bkcolor;
-+	u32 output_size;
-+	u32 bld_mode[4];
-+	u32 dum1[4];
-+	u32 ck_ctl;			/* b0 */
-+	u32 ck_cfg;
-+	u32 dum2[2];
-+	u32 ck_max[4];			/* c0 */
-+	u32 dum3[4];
-+	u32 ck_min[4];			/* e0 */
-+	u32 dum4[3];
-+	u32 out_ctl;			/* fc */
-+};
-+
-+/* VI channel */
-+struct de_vi {
-+	struct {
-+		u32 attr;
-+#define			VI_CFG_ATTR_en BIT(0)
-+#define			VI_CFG_ATTR_fcolor_en BIT(4)
-+#define			VI_CFG_ATTR_fmt_SHIFT 8
-+#define			VI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
-+#define			VI_CFG_ATTR_ui_sel BIT(15)
-+#define			VI_CFG_ATTR_top_down BIT(23)
-+		u32 size;
-+		u32 coord;
-+#define VI_N_PLANES 3
-+		u32 pitch[VI_N_PLANES];
-+		u32 top_laddr[VI_N_PLANES];
-+		u32 bot_laddr[VI_N_PLANES];
-+	} cfg[4];
-+	u32 fcolor[4];			/* c0 */
-+	u32 top_haddr[VI_N_PLANES];	/* d0 */
-+	u32 bot_haddr[VI_N_PLANES];	/* dc */
-+	u32 ovl_size[2];		/* e8 */
-+	u32 hori[2];			/* f0 */
-+	u32 vert[2];			/* f8 */
-+};
-+
-+struct de_ui {
-+	struct {
-+		u32 attr;
-+#define			UI_CFG_ATTR_en BIT(0)
-+#define			UI_CFG_ATTR_alpmod_SHIFT 1
-+#define			UI_CFG_ATTR_alpmod_MASK GENMASK(2, 1)
-+#define			UI_CFG_ATTR_fcolor_en BIT(4)
-+#define			UI_CFG_ATTR_fmt_SHIFT 8
-+#define			UI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
-+#define			UI_CFG_ATTR_top_down BIT(23)
-+#define			UI_CFG_ATTR_alpha_SHIFT 24
-+#define			UI_CFG_ATTR_alpha_MASK GENMASK(31, 24)
-+		u32 size;
-+		u32 coord;
-+		u32 pitch;
-+		u32 top_laddr;
-+		u32 bot_laddr;
-+		u32 fcolor;
-+		u32 dum;
-+	} cfg[4];			/* 00 */
-+	u32 top_haddr;			/* 80 */
-+	u32 bot_haddr;
-+	u32 ovl_size;			/* 88 */
-+};
-+
-+#define HDMI_EDID_BLOCK_SIZE 			128
-+
-+/*
-+ * HDMI register addresses
-+ */
-+#define SUN8I_HDMI_PHY_CTRL_REG			(u32*)(SUNXI_HDMI_BASE + 0x10020)
-+#define SUN8I_HDMI_PHY_UNK1_REG			(u32*)(SUNXI_HDMI_BASE + 0x10024)
-+#define SUN8I_HDMI_PHY_UNK2_REG			(u32*)(SUNXI_HDMI_BASE + 0x10028)
-+#define SUN8I_HDMI_PHY_PLL_REG			(u32*)(SUNXI_HDMI_BASE + 0x1002c)
-+#define SUN8I_HDMI_PHY_CLK_REG			(u32*)(SUNXI_HDMI_BASE + 0x10030)
-+#define SUN8I_HDMI_PHY_UNK3_REG			(u32*)(SUNXI_HDMI_BASE + 0x10034)
-+#define SUN8I_HDMI_PHY_STATUS_REG		(u32*)(SUNXI_HDMI_BASE + 0x10038)
-+
-+#define SUN8I_HDMI_IH_I2CM_STAT0		(u32*)(SUNXI_HDMI_BASE + 0x0013)
-+
-+#define SUN8I_HDMI_I2CM_SLAVE			(u32*)(SUNXI_HDMI_BASE + 0x0EE0)
-+#define SUN8I_HDMI_I2CM_ADDRESS			(u32*)(SUNXI_HDMI_BASE + 0x0EE1)
-+#define SUN8I_HDMI_I2CM_DATAI			(u32*)(SUNXI_HDMI_BASE + 0x8EE1)
-+#define SUN8I_HDMI_I2CM_OPERATION		(u32*)(SUNXI_HDMI_BASE + 0x0EE2)
-+#define SUN8I_HDMI_I2CM_INT			(u32*)(SUNXI_HDMI_BASE + 0x0EE3)
-+#define SUN8I_HDMI_I2CM_DIV			(u32*)(SUNXI_HDMI_BASE + 0x8EE3)
-+#define SUN8I_HDMI_I2CM_SEGADDR			(u32*)(SUNXI_HDMI_BASE + 0x4EE0)
-+#define SUN8I_HDMI_I2CM_SOFTRSTZ		(u32*)(SUNXI_HDMI_BASE + 0x4EE1)
-+#define SUN8I_HDMI_I2CM_SEGPTR			(u32*)(SUNXI_HDMI_BASE + 0xCEE0)
-+#define SUN8I_HDMI_I2CM_SS_SCL_HCNT_0_ADDR	(u32*)(SUNXI_HDMI_BASE + 0x4EE2)
-+#define SUN8I_HDMI_I2CM_SS_SCL_LCNT_0_ADDR	(u32*)(SUNXI_HDMI_BASE + 0xCEE2)
-+
-+/*
-+ * DE register constants.
-+ */
-+/* TODO: move to appropriate place */
-+#define SUN8I_DE_BASE				0x01000000
-+#define SUN8I_DE_GATE_REG			(u32*)(SUN8I_DE_BASE + 0x0004)
-+#define SUN8I_DE_MOD_REG			(u32*)(SUN8I_DE_BASE + 0x0000)
-+#define SUN8I_DE_RESET_REG			(u32*)(SUN8I_DE_BASE + 0x0008)
-+#define SUN8I_DE_DIV_REG			(u32*)(SUN8I_DE_BASE + 0x000c)
-+#define SUN8I_DE_SEL_REG			(u32*)(SUN8I_DE_BASE + 0x0010)
-+
-+#define DE_MUX0_BASE 				(u8*)(SUN8I_DE_BASE + 0x00100000)
-+/* MUX registers (addr / MUX base) */
-+#define DE_MUX_GLB_REGS 0x00000		/* global control */
-+#define DE_MUX_BLD_REGS 0x01000		/* alpha blending */
-+#define DE_MUX_CHAN_REGS 0x02000	/* VI/UI overlay channels */
-+#define		DE_MUX_CHAN_SZ 0x1000	/* size of a channel */
-+#define DE_MUX_VSU_REGS 0x20000		/* VSU */
-+#define DE_MUX_GSU1_REGS 0x30000	/* GSUs */
-+#define DE_MUX_GSU2_REGS 0x40000
-+#define DE_MUX_GSU3_REGS 0x50000
-+#define DE_MUX_FCE_REGS 0xa0000		/* FCE */
-+#define DE_MUX_BWS_REGS 0xa2000		/* BWS */
-+#define DE_MUX_LTI_REGS 0xa4000		/* LTI */
-+#define DE_MUX_PEAK_REGS 0xa6000	/* PEAK */
-+#define DE_MUX_ASE_REGS 0xa8000		/* ASE */
-+#define DE_MUX_FCC_REGS 0xaa000		/* FCC */
-+#define DE_MUX_DCSC_REGS 0xb0000 /* DCSC/SMBL */
-+
-+#define DE2_FORMAT_ARGB_8888 0
-+#define DE2_FORMAT_BGRA_8888 3
-+#define DE2_FORMAT_XRGB_8888 4
-+#define DE2_FORMAT_RGB_888 8
-+#define DE2_FORMAT_BGR_888 9
-+
-+/* coordinates and sizes */
-+#define XY(x, y) (((y) << 16) | (x))
-+#define WH(w, h) (((h - 1) << 16) | (w - 1))
-+
-+/*
-+ * LCDC register constants.
-+ */
-+#define SUN8I_TCON_GCTL_TCON_En			(1 << 31)
-+#define SUN8I_TCON_GINT0_TCON1_Vb_Int_En	(1 << 30)
-+#define SUN8I_TCON_GINT0_TCON1_Vb_Int_Flag	(1 << 14)
-+#define SUN8I_TCON0_CTL_TCON_En			(1 << 31)
-+#define SUN8I_TCON1_CTL_TCON_En			(1 << 31)
-+#define SUN8I_TCON1_CTL_Interlace_En		(1 << 20)
-+#define SUN8I_TCON1_CTL_Start_Delay_SHIFT	4
-+/*#define SUN8I_TCON1_CTL_Start_Delay_MASK	GENMASK(8, 4)*/
-+#define SUN8I_TCON1_IO_POL_IO0_inv		(1 << 24)
-+#define SUN8I_TCON1_IO_POL_IO1_inv		(1 << 25)
-+#define SUN8I_TCON1_IO_POL_IO2_inv		(1 << 26)
-+#define SUN8I_TCON_CEU_CTL_ceu_en		(1 << 31)
-+
-+#define SUNXI_LCDC_X(x)				(((x) - 1) << 16)
-+#define SUNXI_LCDC_Y(y)				(((y) - 1) << 0)
-+#define SUNXI_LCDC_TCON_VSYNC_MASK		(1 << 24)
-+#define SUNXI_LCDC_TCON_HSYNC_MASK		(1 << 25)
-+#define SUNXI_LCDC_CTRL_IO_MAP_MASK		(1 << 0)
-+#define SUNXI_LCDC_CTRL_IO_MAP_TCON0		(0 << 0)
-+#define SUNXI_LCDC_CTRL_IO_MAP_TCON1		(1 << 0)
-+#define SUNXI_LCDC_CTRL_TCON_ENABLE		(1 << 31)
-+#define SUNXI_LCDC_TCON1_CTRL_SRC_BLUE		(1 << 1)
-+#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
-+#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE	(1 << 20)
-+#define SUNXI_LCDC_TCON1_CTRL_ENABLE		(1 << 31)
-+#define SUNXI_LCDC_TCON1_TIMING_H_BP(n)		(((n) - 1) << 0)
-+#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
-+#define SUNXI_LCDC_TCON1_TIMING_V_BP(n)		(((n) - 1) << 0)
-+#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n)	((n) << 16)
-+
-+/*
-+ * HDMI register constants.
-+ */
-+#define SUNXI_HDMI_HPD_DETECT			(1 << 19)
-+
-+#define SUN8I_HMDI_DDC_CTRL_RESET		(1 << 0)
-+#define SUN8I_HMDI_DDC_ADDR_SLAVE_ADDR		(0x50 << 0)
-+#define SUN8I_HMDI_DDC_ADDR_SEG_ADDR		(0x30 << 0)
-+
-+
-+#endif /* _SUNXI_DISPLAY_H */
-diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
-index ed8cd9b..bcf9aa1 100644
---- a/arch/arm/mach-sunxi/clock_sun6i.c
-+++ b/arch/arm/mach-sunxi/clock_sun6i.c
-@@ -141,6 +141,17 @@ void clock_set_pll3(unsigned int clk)
- 	       &ccm->pll3_cfg);
- }
- 
-+void clock_set_pll3_factors(int m, int n)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+
-+	/* PLL3 rate = 24000000 * n / m */
-+	writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
-+	       CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m),
-+	       &ccm->pll3_cfg);
-+}
-+
- void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
- {
- 	struct sunxi_ccm_reg * const ccm =
-@@ -213,6 +224,23 @@ done:
- }
- #endif
- 
-+void clock_set_pll10(unsigned int clk)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+	const int m = 2; /* 12 MHz steps */
-+
-+	if (clk == 0) {
-+		clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);
-+		return;
-+	}
-+
-+	/* PLL10 rate = 24000000 * n / m */
-+	writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE |
-+	       CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m),
-+	       &ccm->pll10_cfg);
-+}
-+
- #ifdef CONFIG_MACH_SUN8I_A33
- void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
- {
-@@ -267,6 +295,7 @@ unsigned int clock_get_mipi_pll(void)
- 	return ((src / 1000) * n * k / m) * 1000;
- }
- 
-+#ifndef CONFIG_MACH_SUN8I
- void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
- {
- 	int pll = clock_get_pll6() * 2;
-@@ -278,3 +307,4 @@ void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
- 	writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
- 	       clk_cfg);
- }
-+#endif
-diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
-index c0ffeb3..77fdc8f 100644
---- a/board/sunxi/Kconfig
-+++ b/board/sunxi/Kconfig
-@@ -458,7 +458,7 @@ config AXP_GPIO
- 
- config VIDEO
- 	bool "Enable graphical uboot console on HDMI, LCD or VGA"
--	depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
-+	depends on !MACH_SUN8I_A83T && !MACH_SUN9I && !MACH_SUN50I
- 	default y
- 	---help---
- 	Say Y here to add support for using a cfb console on the HDMI, LCD
-@@ -467,7 +467,7 @@ config VIDEO
- 
- config VIDEO_HDMI
- 	bool "HDMI output support"
--	depends on VIDEO && !MACH_SUN8I
-+	depends on VIDEO
- 	default y
- 	---help---
- 	Say Y here to add support for outputting video over HDMI.
-diff --git a/drivers/video/Makefile b/drivers/video/Makefile
-index db34904..d05b745 100644
---- a/drivers/video/Makefile
-+++ b/drivers/video/Makefile
-@@ -52,6 +52,7 @@ obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
- obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
- obj-$(CONFIG_VIDEO_SM501) += sm501.o
- obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
-+obj-$(CONFIG_VIDEO_SUNXI_H3) += sun8i_display.o videomodes.o
- obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
- obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
- obj-$(CONFIG_VIDEO_VESA) += vesa.o
-diff --git a/drivers/video/sun8i_display.c b/drivers/video/sun8i_display.c
-new file mode 100644
-index 0000000..e596e4c
---- /dev/null
-+++ b/drivers/video/sun8i_display.c
-@@ -0,0 +1,928 @@
-+/*
-+ * Display driver for sunxi Allwinner SoCs with DE2.
-+ * 
-+ * Copyright (C) 2016 Jernej Skrabec <jernej.skrabec@siol.net>
-+ *
-+ * Based on sunxi_display.c:
-+ * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
-+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
-+ * 
-+ * Based on Linux DRM driver:
-+ * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
-+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
-+ *
-+ * Based on rk_hdmi.c:
-+ * Copyright (c) 2015 Google, Inc
-+ * Copyright 2014 Rockchip Inc.
-+ * 
-+ * SPDX-License-Identifier:	GPL-2.0+
-+ */
-+
-+#include <common.h>
-+
-+#include <asm/arch/clock.h>
-+#include <asm/arch/display2.h>
-+#include <asm/global_data.h>
-+#include <asm/io.h>
-+#include <errno.h>
-+#include <video_fb.h>
-+#include "videomodes.h"
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+enum sunxi_monitor {
-+	sunxi_monitor_none,
-+	sunxi_monitor_dvi,
-+	sunxi_monitor_hdmi,
-+};
-+#define SUNXI_MONITOR_LAST sunxi_monitor_hdmi
-+
-+struct sunxi_display {
-+	GraphicDevice graphic_device;
-+	enum sunxi_monitor monitor;
-+	unsigned int depth;
-+	unsigned int fb_addr;
-+	unsigned int fb_size;
-+} sunxi_display;
-+
-+#ifdef CONFIG_VIDEO_HDMI
-+
-+static void sun8i_hdmi_phy_init(void)
-+{
-+	unsigned long tmo;
-+	u32 tmp;
-+
-+	writel(0, SUN8I_HDMI_PHY_CTRL_REG);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(0));
-+	udelay(5);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(16));
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(1));
-+	udelay(10);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(2));
-+	udelay(5);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(3));
-+	udelay(40);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(19));
-+	udelay(100);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(18));
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, 7 << 4);
-+
-+	/* Note that Allwinner code doesn't fail in case of timeout  */
-+	tmo = timer_get_us() + 2000;
-+	while ((readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x80) == 0) {
-+		if (timer_get_us() > tmo) {
-+			printf("Warning: HDMI phy init timeout!\n");
-+			break;
-+		}
-+	}
-+
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, 0xf << 8);
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, BIT(7));
-+
-+	writel(0x39dc5040, SUN8I_HDMI_PHY_PLL_REG);
-+	writel(0x80084343, SUN8I_HDMI_PHY_CLK_REG);
-+	udelay(10000);
-+	writel(1, SUN8I_HDMI_PHY_UNK3_REG);
-+	setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(25));
-+	udelay(100000);
-+	tmp = (readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x1f800) >> 11;
-+	setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(31) | BIT(30));
-+	setbits_le32(SUN8I_HDMI_PHY_PLL_REG, tmp);
-+	writel(0x01FF0F7F, SUN8I_HDMI_PHY_CTRL_REG);
-+	writel(0x80639000, SUN8I_HDMI_PHY_UNK1_REG);
-+	writel(0x0F81C405, SUN8I_HDMI_PHY_UNK2_REG);
-+
-+	/* enable read access to HDMI controller*/
-+	writel(0x54524545, SUNXI_HDMI_BASE + 0x10010);
-+	
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8080);
-+
-+	udelay(1);
-+
-+	writeb(0x00, SUNXI_HDMI_BASE + 0xF01F);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8403);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x904C);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x904E);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0xD04C);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8250);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8A50);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8272);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x40C0);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x86F0);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x0EE3);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8EE2);
-+	writeb(0xf0, SUNXI_HDMI_BASE + 0xA049);
-+	writeb(0x1e, SUNXI_HDMI_BASE + 0xB045);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x00C1);
-+	writeb(0x03, SUNXI_HDMI_BASE + 0x00C1);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x00C0);
-+	writeb(0x10, SUNXI_HDMI_BASE + 0x40C1);
-+	writeb(0xfd, SUNXI_HDMI_BASE + 0x0081);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x0081);
-+	writeb(0xfd, SUNXI_HDMI_BASE + 0x0081);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x0010);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x0011);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8010);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8011);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x0013);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8012);
-+	writeb(0xff, SUNXI_HDMI_BASE + 0x8013);
-+}
-+
-+static int sun8i_hdmi_hpd_detect(int hpd_delay)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+	unsigned long tmo = timer_get_us() + hpd_delay * 1000;
-+	int status = 0;
-+
-+	/* Set pll3 to 297 MHz */
-+	clock_set_pll3(297000000);
-+
-+	/* Set hdmi parent to pll3 */
-+	clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
-+			CCM_HDMI_CTRL_PLL3);
-+
-+	/* Set ahb gating to pass */
-+	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
-+	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
-+	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
-+	setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
-+
-+	/* Clock on */
-+	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
-+
-+	sun8i_hdmi_phy_init();
-+
-+	while (timer_get_us() < tmo) {
-+		if (readl(SUN8I_HDMI_PHY_STATUS_REG) & SUNXI_HDMI_HPD_DETECT) {
-+			status = 1;
-+			break;
-+		}
-+	}
-+
-+	return status;
-+}
-+
-+static void sunxi_hdmi_shutdown(void)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+
-+	writel(0, SUN8I_HDMI_PHY_CTRL_REG);
-+	clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
-+	clrbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
-+	clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
-+	clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
-+	clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
-+	clock_set_pll3(0);
-+}
-+
-+static int sun8i_hdmi_ddc_wait_i2c_done(int msec)
-+{
-+	u32 val;
-+	ulong start;
-+
-+	start = get_timer(0);
-+	do {
-+		val = readb(SUN8I_HDMI_IH_I2CM_STAT0);
-+		writeb(val, SUN8I_HDMI_IH_I2CM_STAT0);
-+
-+		if (val & 0x2)
-+			return 0;
-+		if (val & 0x1)
-+			return -EIO;
-+
-+		udelay(100);
-+	} while (get_timer(start) < msec);
-+
-+	return 1;
-+}
-+
-+static int sunxi_hdmi_ddc_read(int block, u8 *buf)
-+{
-+	int shift = (block % 2) * 0x80;
-+	int trytime = 5;
-+	int edid_read_err = 0;
-+	u32 op = (block == 0) ? 1 : 2;
-+	int n;
-+
-+	writeb(block >> 1, SUN8I_HDMI_I2CM_SEGPTR);
-+
-+	while (trytime--) {
-+		edid_read_err = 0;
-+
-+		for (n = 0; n < HDMI_EDID_BLOCK_SIZE; n++) {
-+			writeb(shift + n, SUN8I_HDMI_I2CM_ADDRESS);
-+			writeb(op, SUN8I_HDMI_I2CM_OPERATION);
-+
-+			if (sun8i_hdmi_ddc_wait_i2c_done(10)) {
-+				edid_read_err = 1;
-+				break;
-+			}
-+
-+			*buf++ = readb(SUN8I_HDMI_I2CM_DATAI);
-+		}
-+
-+		if (!edid_read_err)
-+			break;
-+	}
-+
-+	return edid_read_err;
-+}
-+
-+static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
-+{
-+	int r, retries = 2;
-+
-+	do {
-+		r = sunxi_hdmi_ddc_read(block, buf);
-+		if (r)
-+			continue;
-+		r = edid_check_checksum(buf);
-+		if (r) {
-+			printf("EDID block %d: checksum error%s\n",
-+			       block, retries ? ", retrying" : "");
-+		}
-+	} while (r && retries--);
-+
-+	return r;
-+}
-+
-+static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
-+{
-+	struct edid1_info edid1;
-+	struct edid_cea861_info cea681[4];
-+	struct edid_detailed_timing *t =
-+		(struct edid_detailed_timing *)edid1.monitor_details.timing;
-+	int i, r, ext_blocks = 0;
-+
-+	/* Reset i2c controller */
-+	writeb(0, SUN8I_HDMI_I2CM_SOFTRSTZ);
-+
-+	writeb(0x05, SUN8I_HDMI_I2CM_DIV);
-+	writeb(0x08, SUN8I_HDMI_I2CM_INT);
-+	writeb(0xd8, SUN8I_HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
-+	writeb(0xfe, SUN8I_HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
-+	writeb(SUN8I_HMDI_DDC_ADDR_SLAVE_ADDR, SUN8I_HDMI_I2CM_SLAVE);
-+	writeb(SUN8I_HMDI_DDC_ADDR_SEG_ADDR, SUN8I_HDMI_I2CM_SEGADDR);
-+
-+	r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
-+	if (r == 0) {
-+		r = edid_check_info(&edid1);
-+		if (r) {
-+			printf("EDID: invalid EDID data\n");
-+			r = -EINVAL;
-+		}
-+	}
-+	if (r == 0) {
-+		ext_blocks = edid1.extension_flag;
-+		if (ext_blocks > 4)
-+			ext_blocks = 4;
-+		for (i = 0; i < ext_blocks; i++) {
-+			if (sunxi_hdmi_edid_get_block(1 + i,
-+						(u8 *)&cea681[i]) != 0) {
-+				ext_blocks = i;
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (r)
-+		return r;
-+
-+	/* We want version 1.3 or 1.2 with detailed timing info */
-+	if (edid1.version != 1 || (edid1.revision < 3 &&
-+			!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
-+		printf("EDID: unsupported version %d.%d\n",
-+		       edid1.version, edid1.revision);
-+		return -EINVAL;
-+	}
-+
-+	/* Take the first usable detailed timing */
-+	for (i = 0; i < 4; i++, t++) {
-+		r = video_edid_dtd_to_ctfb_res_modes(t, mode);
-+		if (r == 0)
-+			break;
-+	}
-+	if (i == 4) {
-+		printf("EDID: no usable detailed timing found\n");
-+		return -ENOENT;
-+	}
-+
-+	/* Check for basic audio support, if found enable hdmi output */
-+	sunxi_display.monitor = sunxi_monitor_dvi;
-+	for (i = 0; i < ext_blocks; i++) {
-+		if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
-+		    cea681[i].revision < 2)
-+			continue;
-+
-+		if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
-+			sunxi_display.monitor = sunxi_monitor_hdmi;
-+	}
-+
-+	return 0;
-+}
-+
-+#endif /* CONFIG_VIDEO_HDMI */
-+
-+/*
-+ * This is the entity that mixes and matches the different layers and inputs.
-+ * Allwinner calls it display engine, but here is called composer.
-+ */
-+static void sunxi_composer_init(void)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+
-+	clock_set_pll10(432000000);
-+	
-+	/* Set DE parent to pll10 */
-+	clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE_CTRL_PLL_MASK,
-+			CCM_DE_CTRL_PLL10);
-+
-+	/* Set ahb gating to pass */
-+	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
-+	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
-+
-+	/* Clock on */
-+	setbits_le32(&ccm->de_clk_cfg, CCM_DE_CTRL_GATE);
-+}
-+
-+static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
-+				    unsigned int address)
-+{
-+	struct de_glb * const de_glb_regs =
-+		(struct de_glb *)(DE_MUX0_BASE + DE_MUX_GLB_REGS);
-+	struct de_bld * const de_bld_regs =
-+		(struct de_bld *)(DE_MUX0_BASE + DE_MUX_BLD_REGS);
-+	struct de_ui * const de_ui_regs =
-+		(struct de_ui *)(DE_MUX0_BASE + DE_MUX_CHAN_REGS +
-+			DE_MUX_CHAN_SZ * 1);
-+	u32 size = WH(mode->xres, mode->yres);
-+	int channel, i;
-+	u32 data;
-+
-+	/* enable clock */
-+	setbits_le32(SUN8I_DE_RESET_REG, 1);
-+	setbits_le32(SUN8I_DE_GATE_REG, 1);
-+	setbits_le32(SUN8I_DE_MOD_REG, 1);
-+	
-+	clrbits_le32(SUN8I_DE_SEL_REG, 1);
-+
-+	writel(DE_MUX_GLB_CTL_rt_en, &de_glb_regs->ctl);
-+	writel(0, &de_glb_regs->status);
-+	writel(1, &de_glb_regs->dbuff);
-+	writel(size, &de_glb_regs->size);
-+
-+	for (channel = 0; channel < 4; channel++) {
-+		void *chan = DE_MUX0_BASE + DE_MUX_CHAN_REGS +
-+			DE_MUX_CHAN_SZ * channel;
-+		memset(chan, 0, channel == 0 ?
-+			sizeof(struct de_vi) : sizeof(struct de_ui));
-+	}
-+
-+	memset(de_bld_regs, 0, 0x44);
-+	writel(0x00000101, &de_bld_regs->fcolor_ctl);
-+
-+	writel(1, &de_bld_regs->route);
-+
-+	writel(0, &de_bld_regs->premultiply);
-+	writel(0xff000000, &de_bld_regs->bkcolor);
-+
-+	writel(0x03010301, &de_bld_regs->bld_mode[0]);
-+	writel(0x03010301, &de_bld_regs->bld_mode[1]);
-+	
-+	writel(size, &de_bld_regs->output_size);
-+	writel(mode->vmode & FB_VMODE_INTERLACED ? 2 : 0,
-+		&de_bld_regs->out_ctl);
-+	writel(0, &de_bld_regs->ck_ctl);
-+
-+	for (i = 0; i < 4; i++) {
-+		writel(0xff000000, &de_bld_regs->attr[i].fcolor);
-+		writel(size, &de_bld_regs->attr[i].insize);
-+	}
-+	
-+	writel(0, DE_MUX0_BASE + DE_MUX_VSU_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_GSU1_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_GSU2_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_GSU3_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_FCE_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_BWS_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_LTI_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_PEAK_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_ASE_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_FCC_REGS);
-+	writel(0, DE_MUX0_BASE + DE_MUX_DCSC_REGS);
-+
-+	data = UI_CFG_ATTR_en | (DE2_FORMAT_XRGB_8888 << UI_CFG_ATTR_fmt_SHIFT) |
-+		(1 << UI_CFG_ATTR_alpmod_SHIFT) | (0xff << UI_CFG_ATTR_alpha_SHIFT);
-+	writel(data, &de_ui_regs->cfg[0].attr);
-+	writel(size, &de_ui_regs->cfg[0].size);
-+	writel(0, &de_ui_regs->cfg[0].coord);
-+	writel(4 * mode->xres, &de_ui_regs->cfg[0].pitch);
-+	writel(address, &de_ui_regs->cfg[0].top_laddr);
-+	writel(size, &de_ui_regs->ovl_size);
-+}
-+
-+static void sunxi_composer_enable(void)
-+{
-+	struct de_glb * const de_glb_regs =
-+		(struct de_glb *)(DE_MUX0_BASE + DE_MUX_GLB_REGS);
-+
-+	writel(1, &de_glb_regs->dbuff);
-+}
-+
-+/*
-+ * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
-+ */
-+static void sunxi_lcdc_pll_set(int dotclock, int *clk_div)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+	int value, n, m, x = 0, diff;
-+	int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
-+
-+	if (dotclock <= 27000)
-+		x = 11;
-+	else if (dotclock <= 74250)
-+		x = 4;
-+	else if (dotclock <= 148500)
-+		x = 2;
-+	else if (dotclock <= 297000)
-+		x = 1;
-+
-+	/*
-+	 * Find the lowest divider resulting in a matching clock, if there
-+	 * is no match, pick the closest lower clock, as monitors tend to
-+	 * not sync to higher frequencies.
-+	 */
-+	for (m = 1; m <= 16; m++) {
-+		n = (m * x * dotclock) / 24000;
-+
-+		if ((n >= 1) && (n <= 128)) {
-+			value = (24000 * n) / m / x;
-+			diff = dotclock - value;
-+			if (diff < best_diff) {
-+				best_diff = diff;
-+				best_m = m;
-+				best_n = n;
-+			}
-+		}
-+	}
-+
-+	clock_set_pll3_factors(best_m, best_n);
-+	printf("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
-+		dotclock, (clock_get_pll3() / 1000) / x,
-+		best_n, best_m, x);
-+
-+	writel(CCM_TCON0_CTRL_GATE | CCM_TCON0_CTRL_M(x),
-+	       &ccm->tcon0_clk_cfg);
-+
-+	*clk_div = x;
-+}
-+
-+static void sunxi_lcdc_init(void)
-+{
-+	struct sunxi_ccm_reg * const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+	struct sun8i_lcdc_reg * const lcdc =
-+		(struct sun8i_lcdc_reg *)SUNXI_LCD0_BASE;
-+
-+	/* Reset off */
-+	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_TCON0);
-+
-+	/* Clock on */
-+	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TCON0);
-+	setbits_le32(&ccm->tcon0_clk_cfg, CCM_TCON0_CTRL_GATE);
-+
-+	/* Init lcdc */
-+	clrbits_le32(&lcdc->tcon0_ctl, SUN8I_TCON0_CTL_TCON_En); /* Disable tcon0 */
-+	clrbits_le32(&lcdc->gctl, SUN8I_TCON_GCTL_TCON_En); /* Disable tcon globally */
-+	writel(0, &lcdc->gint0); /* Disable all interrupts */
-+
-+	/* Set all io lines to tristate */
-+	writel(0x0fffffff, &lcdc->io_tri);
-+}
-+
-+static void sunxi_lcdc_enable(void)
-+{
-+	struct sun8i_lcdc_reg * const lcdc =
-+		(struct sun8i_lcdc_reg *)SUNXI_LCD0_BASE;
-+
-+	setbits_le32(&lcdc->gctl, SUN8I_TCON_GCTL_TCON_En);
-+}
-+
-+static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode, int tcon)
-+{
-+	int delay;
-+
-+	delay = mode->lower_margin + mode->vsync_len + mode->upper_margin;
-+	if (mode->vmode == FB_VMODE_INTERLACED)
-+		delay /= 2;
-+	if (tcon == 1)
-+		delay -= 2;
-+
-+	return (delay > 31) ? 31 : delay;
-+}
-+
-+#if defined CONFIG_VIDEO_HDMI
-+static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
-+				      int *clk_div)
-+{
-+	struct sun8i_lcdc_reg * const lcdc =
-+		(struct sun8i_lcdc_reg *)SUNXI_LCD0_BASE;
-+	int bp, clk_delay, total, yres;
-+
-+	setbits_le32(&lcdc->gctl, SUN8I_TCON_GCTL_TCON_En);
-+
-+	clk_delay = sunxi_lcdc_get_clk_delay(mode, 1);
-+	writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
-+	       ((mode->vmode == FB_VMODE_INTERLACED) ?
-+			SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
-+	       SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctl);
-+
-+	yres = mode->yres;
-+	if (mode->vmode == FB_VMODE_INTERLACED)
-+		yres /= 2;
-+	writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
-+	       &lcdc->basic0);
-+	writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
-+	       &lcdc->basic1);
-+	writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
-+	       &lcdc->basic2);
-+
-+	bp = mode->hsync_len + mode->left_margin;
-+	total = mode->xres + mode->right_margin + bp;
-+	writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
-+	       SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->basic3);
-+
-+	bp = mode->vsync_len + mode->upper_margin;
-+	total = mode->yres + mode->lower_margin + bp;
-+	if (mode->vmode == FB_VMODE_NONINTERLACED)
-+		total *= 2;
-+	writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
-+	       SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->basic4);
-+
-+	writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
-+	       &lcdc->basic5);
-+
-+	writel(0, &lcdc->ceu_ctl);
-+	writel(0, &lcdc->fill_ctl);
-+
-+	sunxi_lcdc_pll_set(mode->pixclock_khz, clk_div);
-+}
-+#endif /* CONFIG_VIDEO_HDMI */
-+
-+#ifdef CONFIG_VIDEO_HDMI
-+
-+static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
-+{
-+	u8 tmp;
-+
-+	if (mode->pixclock_khz <= 27000)
-+		tmp = 0x40; /* SD-modes, ITU601 colorspace */
-+	else
-+		tmp = 0x80; /* HD-modes, ITU709 colorspace */
-+
-+	if (mode->xres * 100 / mode->yres < 156)
-+		tmp |= 0x18;  /* 4 : 3 */
-+	else
-+		tmp |= 0x28; /* 16 : 9 */
-+
-+	setbits_8(SUNXI_HDMI_BASE + 0x0040, 0x08);
-+	writeb(0x60, SUNXI_HDMI_BASE + 0x4045);
-+	writeb(tmp, SUNXI_HDMI_BASE + 0xC044);
-+	writeb(0x88, SUNXI_HDMI_BASE + 0xC045);
-+}
-+
-+static int hdmi_phy_set(u32 divider)
-+{
-+	u32 tmp;
-+
-+	switch(divider)
-+	{
-+		case 1:
-+			writel(0x30dc5fc0, SUN8I_HDMI_PHY_PLL_REG);
-+			writel(0x800863C0, SUN8I_HDMI_PHY_CLK_REG);
-+			mdelay(10);
-+			writel(0x00000001, SUN8I_HDMI_PHY_UNK3_REG);
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(25));
-+			mdelay(200);
-+			tmp = (readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x1f800) >> 11;
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(31) | BIT(30));
-+			if (tmp < 0x3d)
-+				setbits_le32(SUN8I_HDMI_PHY_PLL_REG, tmp + 2);
-+			else
-+				setbits_le32(SUN8I_HDMI_PHY_PLL_REG, 0x3f);
-+			mdelay(100);
-+			writel(0x01FFFF7F, SUN8I_HDMI_PHY_CTRL_REG);
-+			writel(0x8063b000, SUN8I_HDMI_PHY_UNK1_REG);
-+			writel(0x0F8246B5, SUN8I_HDMI_PHY_UNK2_REG);
-+			break;
-+		case 2:
-+			writel(0x39dc5040, SUN8I_HDMI_PHY_PLL_REG);
-+			writel(0x80084381, SUN8I_HDMI_PHY_CLK_REG);
-+			mdelay(10);
-+			writel(0x00000001, SUN8I_HDMI_PHY_UNK3_REG);
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(25));
-+			mdelay(100);
-+			tmp = (readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x1f800) >> 11;
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(31) | BIT(30));
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, tmp);
-+			writel(0x01FFFF7F, SUN8I_HDMI_PHY_CTRL_REG);
-+			writel(0x8063a800, SUN8I_HDMI_PHY_UNK1_REG);
-+			writel(0x0F81C485, SUN8I_HDMI_PHY_UNK2_REG);
-+			break;
-+		case 4:
-+			writel(0x39dc5040, SUN8I_HDMI_PHY_PLL_REG);
-+			writel(0x80084343, SUN8I_HDMI_PHY_CLK_REG);
-+			mdelay(10);
-+			writel(0x00000001, SUN8I_HDMI_PHY_UNK3_REG);
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(25));
-+			mdelay(100);
-+			tmp = (readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x1f800) >> 11;
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(31) | BIT(30));
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, tmp);
-+			writel(0x01FFFF7F, SUN8I_HDMI_PHY_CTRL_REG);
-+			writel(0x8063b000, SUN8I_HDMI_PHY_UNK1_REG);
-+			writel(0x0F81C405, SUN8I_HDMI_PHY_UNK2_REG);
-+			break;
-+		case 11:
-+			writel(0x39dc5040, SUN8I_HDMI_PHY_PLL_REG);
-+			writel(0x8008430a, SUN8I_HDMI_PHY_CLK_REG);
-+			mdelay(10);
-+			writel(0x00000001, SUN8I_HDMI_PHY_UNK3_REG);
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(25));
-+			mdelay(100);
-+			tmp = (readl(SUN8I_HDMI_PHY_STATUS_REG) & 0x1f800) >> 11;
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, BIT(31) | BIT(30));
-+			setbits_le32(SUN8I_HDMI_PHY_PLL_REG, tmp);
-+			writel(0x01FFFF7F, SUN8I_HDMI_PHY_CTRL_REG);
-+			writel(0x8063b000, SUN8I_HDMI_PHY_UNK1_REG);
-+			writel(0x0F81C405, SUN8I_HDMI_PHY_UNK2_REG);
-+			break;
-+		default:
-+			return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
-+				int clk_div)
-+{
-+	u8 invidconf, v_blanking;
-+	u32 h_blanking;
-+
-+	if(hdmi_phy_set(clk_div) != 0) {
-+		printf("HDMI divider is invalid!\n");
-+		return;
-+	}
-+	
-+	invidconf = 0;
-+	if(mode->vmode & FB_VMODE_INTERLACED)
-+		invidconf |= 0x01;
-+	if(mode->sync & FB_SYNC_HOR_HIGH_ACT)
-+		invidconf |= 0x20;
-+	if(mode->sync & FB_SYNC_VERT_HIGH_ACT)
-+		invidconf |= 0x40;
-+
-+	h_blanking = mode->left_margin + mode->right_margin + mode->hsync_len;
-+	v_blanking = mode->upper_margin + mode->lower_margin + mode->vsync_len;
-+
-+	writeb(invidconf | 0x10, SUNXI_HDMI_BASE + 0x0040);
-+	writeb(((invidconf < 96) ? 0x03 : 0x00), SUNXI_HDMI_BASE + 0x10001);
-+
-+	writeb(mode->xres >> 8, SUNXI_HDMI_BASE + 0x8040);
-+	writeb(mode->xres, SUNXI_HDMI_BASE + 0x0041);
-+	writeb(mode->yres >> 8, SUNXI_HDMI_BASE + 0x8042);
-+	writeb(mode->yres, SUNXI_HDMI_BASE + 0x0043);
-+	writeb(mode->vsync_len, SUNXI_HDMI_BASE + 0x4043);
-+	writeb(h_blanking >> 8, SUNXI_HDMI_BASE + 0x0042);
-+	writeb(h_blanking, SUNXI_HDMI_BASE + 0x8041);
-+	writeb(mode->lower_margin, SUNXI_HDMI_BASE + 0x4042);
-+	writeb(mode->right_margin >> 8, SUNXI_HDMI_BASE + 0x4041);
-+	writeb(mode->right_margin, SUNXI_HDMI_BASE + 0x4040);
-+	writeb(mode->hsync_len >> 8, SUNXI_HDMI_BASE + 0xC041);
-+	writeb(mode->hsync_len, SUNXI_HDMI_BASE + 0xC040);
-+	writeb(v_blanking, SUNXI_HDMI_BASE + 0x8043);
-+
-+	writeb(0x0c, SUNXI_HDMI_BASE + 0x0045);
-+	writeb(0x20, SUNXI_HDMI_BASE + 0x8044);
-+	writeb(0x01, SUNXI_HDMI_BASE + 0x8045);
-+	writeb(0x0b, SUNXI_HDMI_BASE + 0x0046);
-+	writeb(0x16, SUNXI_HDMI_BASE + 0x0047);
-+	writeb(0x21, SUNXI_HDMI_BASE + 0x8046);
-+
-+	writeb(0x40, SUNXI_HDMI_BASE + 0x0401);
-+	writeb(0x07, SUNXI_HDMI_BASE + 0x8400);
-+
-+	// default value, written 0 by rk_hdmi
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8401);
-+
-+	writeb(0x47, SUNXI_HDMI_BASE + 0x0402);
-+	writeb(0x01, SUNXI_HDMI_BASE + 0x0800);
-+	writeb(0x07, SUNXI_HDMI_BASE + 0x0801);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8800);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8801);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x0802);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x0803);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8802);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x8803);
-+
-+	if (sunxi_display.monitor == sunxi_monitor_hdmi)
-+		sunxi_hdmi_setup_info_frames(mode);
-+
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x0082);
-+	writeb(0x00, SUNXI_HDMI_BASE + 0x0081);
-+}
-+
-+static void sunxi_hdmi_enable(void)
-+{
-+	setbits_le32(SUN8I_HDMI_PHY_CTRL_REG, 0xf << 12);
-+	printf("hdmi enabled\n");
-+}
-+
-+#endif /* CONFIG_VIDEO_HDMI */
-+ 
-+static void sunxi_engines_init(void)
-+{
-+	sunxi_composer_init();
-+	sunxi_lcdc_init();
-+}
-+ 
-+static void sunxi_mode_set(const struct ctfb_res_modes *mode,
-+			   unsigned int address)
-+{
-+	int __maybe_unused clk_div;
-+
-+	switch (sunxi_display.monitor) {
-+	case sunxi_monitor_none:
-+		break;
-+	case sunxi_monitor_dvi:
-+	case sunxi_monitor_hdmi:
-+#ifdef CONFIG_VIDEO_HDMI
-+		sunxi_composer_mode_set(mode, address);
-+		sunxi_lcdc_tcon0_mode_set(mode, &clk_div);
-+		sunxi_hdmi_mode_set(mode, clk_div);
-+		sunxi_composer_enable();
-+		sunxi_lcdc_enable();
-+		sunxi_hdmi_enable();
-+#endif
-+		break;
-+	}
-+}
-+
-+static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
-+{
-+	switch (monitor) {
-+	case sunxi_monitor_none:		return "none";
-+	case sunxi_monitor_dvi:			return "dvi";
-+	case sunxi_monitor_hdmi:		return "hdmi";
-+	}
-+	return NULL; /* never reached */
-+}
-+
-+ulong board_get_usable_ram_top(ulong total_size)
-+{
-+	return gd->ram_top - CONFIG_SUNXI_MAX_FB_SIZE;
-+}
-+
-+static bool sunxi_has_hdmi(void)
-+{
-+#ifdef CONFIG_VIDEO_HDMI
-+	return true;
-+#else
-+	return false;
-+#endif
-+}
-+
-+static enum sunxi_monitor sunxi_get_default_mon(bool allow_hdmi)
-+{
-+	if (allow_hdmi && sunxi_has_hdmi())
-+		return sunxi_monitor_dvi;
-+	else
-+		return sunxi_monitor_none;
-+}
-+
-+void *video_hw_init(void)
-+{
-+	static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
-+	const struct ctfb_res_modes *mode;
-+	struct ctfb_res_modes custom;
-+	const char *options;
-+#ifdef CONFIG_VIDEO_HDMI
-+	int ret, hpd, hpd_delay, edid;
-+#endif
-+	int i, overscan_offset, overscan_x, overscan_y;
-+	unsigned int fb_dma_addr;
-+	char mon[16];
-+
-+	memset(&sunxi_display, 0, sizeof(struct sunxi_display));
-+
-+	video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
-+				 &sunxi_display.depth, &options);
-+#ifdef CONFIG_VIDEO_HDMI
-+	hpd = video_get_option_int(options, "hpd", 1);
-+	hpd_delay = video_get_option_int(options, "hpd_delay", 500);
-+	edid = video_get_option_int(options, "edid", 1);
-+#endif
-+	overscan_x = video_get_option_int(options, "overscan_x", -1);
-+	overscan_y = video_get_option_int(options, "overscan_y", -1);
-+	sunxi_display.monitor = sunxi_get_default_mon(true);
-+	video_get_option_string(options, "monitor", mon, sizeof(mon),
-+				sunxi_get_mon_desc(sunxi_display.monitor));
-+	for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
-+		if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
-+			sunxi_display.monitor = i;
-+			break;
-+		}
-+	}
-+	if (i > SUNXI_MONITOR_LAST)
-+		printf("Unknown monitor: '%s', falling back to '%s'\n",
-+		       mon, sunxi_get_mon_desc(sunxi_display.monitor));
-+
-+#ifdef CONFIG_VIDEO_HDMI
-+	/* If HDMI/DVI is selected do HPD & EDID, and handle fallback */
-+	if (sunxi_display.monitor == sunxi_monitor_dvi ||
-+	    sunxi_display.monitor == sunxi_monitor_hdmi) {
-+		/* Always call hdp_detect, as it also enables clocks, etc. */
-+		ret = sun8i_hdmi_hpd_detect(hpd_delay);
-+		if (ret) {
-+			printf("HDMI connected: ");
-+			if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
-+				mode = &custom;
-+		} else if (hpd) {
-+			sunxi_hdmi_shutdown();
-+			sunxi_display.monitor = sunxi_get_default_mon(false);
-+		} /* else continue with hdmi/dvi without a cable connected */
-+	}
-+#endif
-+
-+	switch (sunxi_display.monitor) {
-+	case sunxi_monitor_none:
-+		return NULL;
-+	case sunxi_monitor_dvi:
-+	case sunxi_monitor_hdmi:
-+		if (!sunxi_has_hdmi()) {
-+			printf("HDMI/DVI not supported on this board\n");
-+			sunxi_display.monitor = sunxi_monitor_none;
-+			return NULL;
-+		}
-+		break;
-+	}
-+
-+	if (overscan_x == -1)
-+		overscan_x = 0;
-+	if (overscan_y == -1)
-+		overscan_y = 0;
-+
-+	sunxi_display.fb_size =
-+		(mode->xres * mode->yres * 4 + 0xfff) & ~0xfff;
-+	overscan_offset = (overscan_y * mode->xres + overscan_x) * 4;
-+	/* We want to keep the fb_base for simplefb page aligned, where as
-+	 * the sunxi dma engines will happily accept an unaligned address. */
-+	if (overscan_offset)
-+		sunxi_display.fb_size += 0x1000;
-+
-+	if (sunxi_display.fb_size > CONFIG_SUNXI_MAX_FB_SIZE) {
-+		printf("Error need %dkB for fb, but only %dkB is reserved\n",
-+		       sunxi_display.fb_size >> 10,
-+		       CONFIG_SUNXI_MAX_FB_SIZE >> 10);
-+		return NULL;
-+	}
-+
-+	printf("Setting up a %dx%d%s %s console (overscan %dx%d)\n",
-+	       mode->xres, mode->yres,
-+	       (mode->vmode == FB_VMODE_INTERLACED) ? "i" : "",
-+	       sunxi_get_mon_desc(sunxi_display.monitor),
-+	       overscan_x, overscan_y);
-+
-+	gd->fb_base = gd->bd->bi_dram[0].start +
-+		      gd->bd->bi_dram[0].size - sunxi_display.fb_size;
-+	sunxi_engines_init();
-+
-+	fb_dma_addr = gd->fb_base;
-+	sunxi_display.fb_addr = gd->fb_base;
-+	if (overscan_offset) {
-+		fb_dma_addr += 0x1000 - (overscan_offset & 0xfff);
-+		sunxi_display.fb_addr += (overscan_offset + 0xfff) & ~0xfff;
-+		memset((void *)gd->fb_base, 0, sunxi_display.fb_size);
-+		flush_cache(gd->fb_base, sunxi_display.fb_size);
-+	}
-+	sunxi_mode_set(mode, fb_dma_addr);
-+
-+	/*
-+	 * These are the only members of this structure that are used. All the
-+	 * others are driver specific. The pitch is stored in plnSizeX.
-+	 */
-+	graphic_device->frameAdrs = sunxi_display.fb_addr;
-+	graphic_device->gdfIndex = GDF_32BIT_X888RGB;
-+	graphic_device->gdfBytesPP = 4;
-+	graphic_device->winSizeX = mode->xres - 2 * overscan_x;
-+	graphic_device->winSizeY = mode->yres - 2 * overscan_y;
-+	graphic_device->plnSizeX = mode->xres * graphic_device->gdfBytesPP;
-+
-+	return graphic_device;
-+}
-diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
-index e0464df..c63c1bc 100644
---- a/include/configs/sunxi-common.h
-+++ b/include/configs/sunxi-common.h
-@@ -284,9 +284,13 @@ extern int soft_i2c_gpio_scl;
- #define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20)
- 
- /* Do we want to initialize a simple FB? */
-+#ifndef CONFIG_MACH_SUN8I_H3
- #define CONFIG_VIDEO_DT_SIMPLEFB
- 
- #define CONFIG_VIDEO_SUNXI
-+#else
-+#define CONFIG_VIDEO_SUNXI_H3
-+#endif
- 
- #define CONFIG_VIDEO_LOGO
- #define CONFIG_VIDEO_STD_TIMINGS
-diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
-index 11b5a22..cef476f 100644
---- a/scripts/config_whitelist.txt
-+++ b/scripts/config_whitelist.txt
-@@ -8270,6 +8270,7 @@ CONFIG_VIDEO_SM501_8BPP
- CONFIG_VIDEO_SM501_PCI
- CONFIG_VIDEO_STD_TIMINGS
- CONFIG_VIDEO_SUNXI
-+CONFIG_VIDEO_SUNXI_H3
- CONFIG_VIDEO_VCXK
- CONFIG_VID_FLS_ENV
- CONFIG_VM86
diff --git a/patch/u-boot/u-boot-dev/add-lime2-emmc.patch b/patch/u-boot/u-boot-dev/add-lime2-emmc.patch
deleted file mode 100644
index 3153ec03e..000000000
--- a/patch/u-boot/u-boot-dev/add-lime2-emmc.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
-new file mode 100644
-index 0000000..e41a880
---- /dev/null
-+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
-@@ -0,0 +1,30 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_SPL_I2C_SUPPORT=y
-+CONFIG_MACH_SUN7I=y
-+CONFIG_DRAM_CLK=384
-+CONFIG_MMC0_CD_PIN="PH1"
-+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-+CONFIG_USB0_VBUS_PIN="PC17"
-+CONFIG_USB0_VBUS_DET="PH5"
-+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2-emmc"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
-+CONFIG_SPL=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+CONFIG_CMD_DFU=y
-+CONFIG_CMD_USB_MASS_STORAGE=y
-+# CONFIG_CMD_FPGA is not set
-+CONFIG_DFU_RAM=y
-+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
-+CONFIG_ETH_DESIGNWARE=y
-+CONFIG_AXP_ALDO3_VOLT=2800
-+CONFIG_AXP_ALDO4_VOLT=2800
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_MUSB_GADGET=y
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DOWNLOAD=y
-+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
-+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
-+CONFIG_G_DNL_PRODUCT_NUM=0x1010
diff --git a/patch/u-boot/u-boot-dev/add-missing-h3-boards.patch b/patch/u-boot/u-boot-dev/add-missing-h3-boards.patch
deleted file mode 100644
index edec3f4a9..000000000
--- a/patch/u-boot/u-boot-dev/add-missing-h3-boards.patch
+++ /dev/null
@@ -1,119 +0,0 @@
-diff --git a/configs/FriendlyARM_NanoPi_M1_defconfig b/configs/FriendlyARM_NanoPi_M1_defconfig
-new file mode 100644
-index 0000000..5ba9f9e
---- /dev/null
-+++ b/configs/FriendlyARM_NanoPi_M1_defconfig
-@@ -0,0 +1,14 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_MACH_SUN8I_H3=y
-+CONFIG_DRAM_CLK=624
-+CONFIG_DRAM_ZQ=3881979
-+CONFIG_DRAM_ODT_EN=y
-+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_SPL=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_CMD_FPGA is not set
-+CONFIG_SUN8I_EMAC=y
-+CONFIG_USB_EHCI_HCD=y
-diff --git a/configs/FriendlyARM_NanoPi_NEO_defconfig b/configs/FriendlyARM_NanoPi_NEO_defconfig
-new file mode 100644
-index 0000000..4e7f0e4
---- /dev/null
-+++ b/configs/FriendlyARM_NanoPi_NEO_defconfig
-@@ -0,0 +1,15 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_MACH_SUN8I_H3=y
-+CONFIG_DRAM_CLK=408
-+CONFIG_DRAM_ZQ=3881979
-+CONFIG_DRAM_ODT_EN=y
-+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_SPL=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_CMD_FPGA is not set
-+CONFIG_SUN8I_EMAC=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_SYS_CLK_FREQ=480000000
-diff --git a/configs/Sinovoip_BPI_M2_plus_defconfig b/configs/Sinovoip_BPI_M2_plus_defconfig
-new file mode 100644
-index 0000000..5ba9f9e
---- /dev/null
-+++ b/configs/Sinovoip_BPI_M2_plus_defconfig
-@@ -0,0 +1,15 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_MACH_SUN8I_H3=y
-+CONFIG_DRAM_CLK=624
-+CONFIG_DRAM_ZQ=3881979
-+CONFIG_DRAM_ODT_EN=y
-+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_SPL=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_CMD_FPGA is not set
-+CONFIG_SUN8I_EMAC=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
---- a/configs/orangepi_2_defconfig
-+++ b/configs/orangepi_2_defconfig
-@@ -14,3 +14,4 @@
- CONFIG_SUN8I_EMAC=y
- CONFIG_SY8106A_POWER=y
- CONFIG_USB_EHCI_HCD=y
-+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
-new file mode 100755
-index 0000000..a62d565
---- /dev/null
-+++ b/configs/orangepi_zero_defconfig
-@@ -0,0 +1,22 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_MACH_SUN8I_H3=y
-+CONFIG_DRAM_CLK=408
-+CONFIG_DRAM_ZQ=3881979
-+CONFIG_DRAM_ODT_EN=y
-+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_SPI_FLASH=y
-+CONFIG_SPI_FLASH_WINBOND=y
-+CONFIG_SPL_SPI_FLASH_SUPPORT=y
-+CONFIG_SPL=y
-+CONFIG_SPL_SPI_SUNXI=y
-+CONFIG_SPI_BOOT=y
-+# CONFIG_SPL_SPI_SUPPORT is not set
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_CMD_FPGA is not set
-+CONFIG_SUN8I_EMAC=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_SYS_CLK_FREQ=480000000
-+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-diff --git a/configs/FriendlyARM_NanoPi_M1_Plus_defconfig b/configs/FriendlyARM_NanoPi_M1_Plus_defconfig
-new file mode 100644
-index 0000000..5ba9f9e
---- /dev/null
-+++ b/configs/FriendlyARM_NanoPi_M1_Plus_defconfig
-@@ -0,0 +1,15 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_MACH_SUN8I_H3=y
-+CONFIG_DRAM_CLK=576
-+CONFIG_DRAM_ZQ=3881979
-+CONFIG_DRAM_ODT_EN=y
-+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_SPL=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_CMD_FPGA is not set
-+CONFIG_SUN8I_EMAC=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-\ No newline at end of file
diff --git a/patch/u-boot/u-boot-dev/adjust-h3-dram-frequency.patch b/patch/u-boot/u-boot-dev/adjust-h3-dram-frequency.patch
deleted file mode 100644
index 1dacb2c37..000000000
--- a/patch/u-boot/u-boot-dev/adjust-h3-dram-frequency.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig
-index a72d506..2c49525 100644
---- a/configs/orangepi_lite_defconfig
-+++ b/configs/orangepi_lite_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN8I_H3=y
--CONFIG_DRAM_CLK=672
-+CONFIG_DRAM_CLK=624
- CONFIG_DRAM_ZQ=3881979
- CONFIG_DRAM_ODT_EN=y
- CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite"
-diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
-index 5a7aba1..3ba4009 100644
---- a/configs/orangepi_one_defconfig
-+++ b/configs/orangepi_one_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN8I_H3=y
--CONFIG_DRAM_CLK=672
-+CONFIG_DRAM_CLK=624
- CONFIG_DRAM_ZQ=3881979
- CONFIG_DRAM_ODT_EN=y
- CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
-diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
-index 2374f1d..579bc70 100644
---- a/configs/orangepi_plus2e_defconfig
-+++ b/configs/orangepi_plus2e_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN8I_H3=y
--CONFIG_DRAM_CLK=672
-+CONFIG_DRAM_CLK=624
- CONFIG_DRAM_ZQ=3881979
- CONFIG_DRAM_ODT_EN=y
- CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
-index f2ed941..e8219bb 100644
---- a/configs/orangepi_plus_defconfig
-+++ b/configs/orangepi_plus_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN8I_H3=y
--CONFIG_DRAM_CLK=672
-+CONFIG_DRAM_CLK=624
- CONFIG_DRAM_ZQ=3881979
- CONFIG_DRAM_ODT_EN=y
- CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/patch/u-boot/u-boot-dev/disable-usb-keyboards.patch b/patch/u-boot/u-boot-dev/disable-usb-keyboards.patch
deleted file mode 100644
index 42ec7b6c3..000000000
--- a/patch/u-boot/u-boot-dev/disable-usb-keyboards.patch
+++ /dev/null
@@ -1,12 +0,0 @@
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index e63309a..f443bc7 100644
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -659,7 +659,6 @@ config ARCH_SUNXI
- 	select SYS_NS16550
- 	select USB
- 	select USB_STORAGE
--	select USB_KEYBOARD
- 	select USE_TINY_PRINTF
- 
- config TARGET_TS4800
diff --git a/patch/u-boot/u-boot-dev/fix-h3-rev3-dram-calibration.patch.disabled b/patch/u-boot/u-boot-dev/fix-h3-rev3-dram-calibration.patch.disabled
deleted file mode 100644
index 54c51de2a..000000000
--- a/patch/u-boot/u-boot-dev/fix-h3-rev3-dram-calibration.patch.disabled
+++ /dev/null
@@ -1,106 +0,0 @@
-From f0b3ecefb7241c565b6400d2da11fc5c49b570ff Mon Sep 17 00:00:00 2001
-From: Jens Kuske <jenskuske@gmail.com>
-Date: Wed, 21 Sep 2016 16:08:43 +0200
-Subject: [PATCH] sunxi: Fix H3 DRAM impedance calibration on rev. A chips
-
-H3 seems to have a silicon bug breaking the impedance calibration.
-This is currently worked around in software by multiple steps
-combining the results to replace the wrong values.
-
-Revision A chips need a different workaround, which is present in
-the vendor bootloader too, but got overlooked in lack of
-information and affected boards till now.
-This commit adds a simplified version without correction factor,
-which would be 1.00 for all known boards anyway.
-
-Signed-off-by: Jens Kuske <jenskuske@gmail.com>
----
- arch/arm/mach-sunxi/dram_sun8i_h3.c | 67 +++++++++++++++++++++++++------------
- 1 file changed, 46 insertions(+), 21 deletions(-)
-
-diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c
-index 2020d75..b23a46c 100644
---- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
-+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
-@@ -217,35 +217,60 @@ static void mctl_zq_calibration(struct dram_para *para)
- 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
- 			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- 
--	int i;
--	u16 zq_val[6];
--	u8 val;
-+	if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
-+		(readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0)
-+	{
-+		u32 reg_val;
- 
--	writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
--
--	for (i = 0; i < 6; i++) {
--		u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
--
--		writel((zq << 20) | (zq << 16) | (zq << 12) |
--				(zq << 8) | (zq << 4) | (zq << 0),
--				&mctl_ctl->zqcr);
-+		clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
-+				CONFIG_DRAM_ZQ & 0xffff);
- 
- 		writel(PIR_CLRSR, &mctl_ctl->pir);
- 		mctl_phy_init(PIR_ZCAL);
- 
--		zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
--		writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
--
--		writel(PIR_CLRSR, &mctl_ctl->pir);
--		mctl_phy_init(PIR_ZCAL);
-+		reg_val = readl(&mctl_ctl->zqdr[0]);
-+		reg_val &= (0x1f << 16) | (0x1f << 0);
-+		reg_val |= reg_val << 8;
-+		writel(reg_val, &mctl_ctl->zqdr[0]);
- 
--		val = readl(&mctl_ctl->zqdr[0]) >> 24;
--		zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
-+		reg_val = readl(&mctl_ctl->zqdr[1]);
-+		reg_val &= (0x1f << 16) | (0x1f << 0);
-+		reg_val |= reg_val << 8;
-+		writel(reg_val, &mctl_ctl->zqdr[1]);
-+		writel(reg_val, &mctl_ctl->zqdr[2]);
- 	}
-+	else
-+	{
-+		int i;
-+		u16 zq_val[6];
-+		u8 val;
-+
-+		writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
-+
-+		for (i = 0; i < 6; i++) {
-+			u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
- 
--	writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
--	writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
--	writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
-+			writel((zq << 20) | (zq << 16) | (zq << 12) |
-+					(zq << 8) | (zq << 4) | (zq << 0),
-+					&mctl_ctl->zqcr);
-+
-+			writel(PIR_CLRSR, &mctl_ctl->pir);
-+			mctl_phy_init(PIR_ZCAL);
-+
-+			zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
-+			writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
-+
-+			writel(PIR_CLRSR, &mctl_ctl->pir);
-+			mctl_phy_init(PIR_ZCAL);
-+
-+			val = readl(&mctl_ctl->zqdr[0]) >> 24;
-+			zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
-+		}
-+
-+		writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
-+		writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
-+		writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
-+	}
- }
- 
- static void mctl_set_cr(struct dram_para *para)
diff --git a/patch/u-boot/u-boot-dev/h3-enable-power-led.patch b/patch/u-boot/u-boot-dev/h3-enable-power-led.patch
deleted file mode 100644
index aec4cccff..000000000
--- a/patch/u-boot/u-boot-dev/h3-enable-power-led.patch
+++ /dev/null
@@ -1,17 +0,0 @@
-diff --git a/board/sunxi/board.c b/board/sunxi/board.c
-index 3cf3614..89cf7f5 100644
---- a/board/sunxi/board.c
-+++ b/board/sunxi/board.c
-@@ -478,6 +478,11 @@ void sunxi_board_init(void)
- 	int power_failed = 0;
- 	unsigned long ramsize;
- 
-+#ifdef CONFIG_MACH_SUN8I_H3
-+	/* turn on power LED (PL10) on H3 boards */
-+	gpio_direction_output(SUNXI_GPL(10), 1);
-+#endif
-+
- #ifdef CONFIG_SY8106A_POWER
- 	power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
- #endif
-
diff --git a/patch/u-boot/u-boot-dev/u-boot-01-led-support-default-state.patch.disabled b/patch/u-boot/u-boot-dev/u-boot-01-led-support-default-state.patch.disabled
deleted file mode 100644
index 0251074d8..000000000
--- a/patch/u-boot/u-boot-dev/u-boot-01-led-support-default-state.patch.disabled
+++ /dev/null
@@ -1,178 +0,0 @@
-diff -Nur a/arch/arm/Kconfig leds/arch/arm/Kconfig
---- a/arch/arm/Kconfig	2016-09-12 16:05:51.000000000 +0200
-+++ leds/arch/arm/Kconfig	2016-09-21 19:17:56.246729135 +0200
-@@ -651,6 +651,8 @@
- 	select DM_KEYBOARD
- 	select DM_SERIAL
- 	select DM_USB
-+	select LED
-+	select LED_GPIO
- 	select OF_BOARD_SETUP
- 	select OF_CONTROL
- 	select OF_SEPARATE
-diff -Nur a/board/sunxi/board.c leds/board/sunxi/board.c
---- a/board/sunxi/board.c	2016-09-12 16:05:51.000000000 +0200
-+++ leds/board/sunxi/board.c	2016-09-21 19:14:16.236727224 +0200
-@@ -29,6 +29,7 @@
- #include <asm/io.h>
- #include <crc.h>
- #include <environment.h>
-+#include <led.h>
- #include <libfdt.h>
- #include <nand.h>
- #include <net.h>
-@@ -682,6 +683,12 @@
- {
- 	__maybe_unused int ret;
- 
-+#ifdef CONFIG_LED
-+	ret = led_set_default_states();
-+	if (ret)
-+		return ret;
-+#endif
-+
- 	setenv("fel_booted", NULL);
- 	setenv("fel_scriptaddr", NULL);
- 	/* determine if we are running in FEL mode */
-diff -Nur a/drivers/led/led_gpio.c leds/drivers/led/led_gpio.c
---- a/drivers/led/led_gpio.c	2016-09-12 16:05:51.000000000 +0200
-+++ leds/drivers/led/led_gpio.c	2016-09-21 19:14:16.236727224 +0200
-@@ -67,6 +67,7 @@
- 	     node = fdt_next_subnode(blob, node)) {
- 		struct led_uclass_plat *uc_plat;
- 		const char *label;
-+		const char *state;
- 
- 		label = fdt_getprop(blob, node, "label", NULL);
- 		if (!label) {
-@@ -74,6 +75,7 @@
- 			      fdt_get_name(blob, node, NULL));
- 			return -EINVAL;
- 		}
-+		state = fdt_getprop(blob, node, "default-state", NULL);
- 		ret = device_bind_driver_to_node(parent, "gpio_led",
- 						 fdt_get_name(blob, node, NULL),
- 						 node, &dev);
-@@ -81,6 +83,15 @@
- 			return ret;
- 		uc_plat = dev_get_uclass_platdata(dev);
- 		uc_plat->label = label;
-+		if (state) {
-+			if(!strcmp(state, "on"))
-+				uc_plat->default_state = LED_STATE_ON;
-+			else if(!strcmp(state, "keep"))
-+				uc_plat->default_state = LED_STATE_KEEP;
-+			else
-+				uc_plat->default_state = LED_STATE_OFF;
-+		} else
-+			uc_plat->default_state = LED_STATE_OFF;
- 	}
- 
- 	return 0;
-diff -Nur a/drivers/led/led-uclass.c leds/drivers/led/led-uclass.c
---- a/drivers/led/led-uclass.c	2016-09-12 16:05:51.000000000 +0200
-+++ leds/drivers/led/led-uclass.c	2016-09-21 19:14:16.236727224 +0200
-@@ -12,6 +12,21 @@
- #include <dm/root.h>
- #include <dm/uclass-internal.h>
- 
-+int led_autoset(struct udevice *dev)
-+{
-+	struct led_uclass_plat *uc_pdata;
-+	int ret = 0;
-+
-+	uc_pdata = dev_get_uclass_platdata(dev);
-+	if (!uc_pdata->label)
-+		return -EMEDIUMTYPE;
-+
-+	if (uc_pdata->default_state != LED_STATE_KEEP)
-+		ret = led_set_on(dev, uc_pdata->default_state == LED_STATE_ON);
-+
-+	return ret;
-+}
-+
- int led_get_by_label(const char *label, struct udevice **devp)
- {
- 	struct udevice *dev;
-@@ -32,6 +47,26 @@
- 	return -ENODEV;
- }
- 
-+int led_set_default_states(void)
-+{
-+	struct udevice *dev;
-+	struct uclass *uc;
-+	int ret;
-+
-+	ret = uclass_get(UCLASS_LED, &uc);
-+	if (ret)
-+		return ret;
-+	for (uclass_first_device(UCLASS_LED, &dev);
-+	     dev;
-+	     uclass_next_device(&dev)) {
-+		ret = led_autoset(dev);
-+		if (ret == -EMEDIUMTYPE || ret == -ENOSYS)
-+			ret = 0;
-+	}
-+
-+	return ret;
-+}
-+
- int led_set_on(struct udevice *dev, int on)
- {
- 	struct led_ops *ops = led_get_ops(dev);
-diff -Nur a/include/led.h leds/include/led.h
---- a/include/led.h	2016-09-12 16:05:51.000000000 +0200
-+++ leds/include/led.h	2016-09-21 19:14:16.236727224 +0200
-@@ -8,6 +8,14 @@
- #ifndef __LED_H
- #define __LED_H
- 
-+/* LED default states
-+ */
-+enum led_default_state {
-+	LED_STATE_OFF,
-+	LED_STATE_ON,
-+	LED_STATE_KEEP
-+};
-+
- /**
-  * struct led_uclass_plat - Platform data the uclass stores about each device
-  *
-@@ -15,6 +23,7 @@
-  */
- struct led_uclass_plat {
- 	const char *label;
-+	enum led_default_state default_state;
- };
- 
- struct led_ops {
-@@ -31,6 +40,14 @@
- #define led_get_ops(dev)	((struct led_ops *)(dev)->driver->ops)
- 
- /**
-+ * led_autoset() - set the state of an LED according to fdt
-+ *
-+ * @dev:	LED device to set
-+ * @return 0 if OK, -ve on error
-+ */
-+int led_autoset(struct udevice *dev);
-+
-+/**
-  * led_get_by_label() - Find an LED device by label
-  *
-  * @label:	LED label to look up
-@@ -40,6 +57,13 @@
- int led_get_by_label(const char *label, struct udevice **devp);
- 
- /**
-+ * led_set_default_states() - set the state of all LEDs according to fdt
-+ *
-+ * @return 0 if OK, -ve on error
-+ */
-+int led_set_default_states(void);
-+
-+/**
-  * led_set_on() - set the state of an LED
-  *
-  * @dev:	LED device to change
diff --git a/patch/u-boot/u-boot-next/a10_a20_dram-clk.patch b/patch/u-boot/u-boot-next/a10_a20_dram-clk.patch
deleted file mode 100644
index 0c17f5a43..000000000
--- a/patch/u-boot/u-boot-next/a10_a20_dram-clk.patch
+++ /dev/null
@@ -1,144 +0,0 @@
-diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
-index 8cb7ac7..8b6c1bd 100644
---- a/configs/A10-OLinuXino-Lime_defconfig
-+++ b/configs/A10-OLinuXino-Lime_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN4I=y
--CONFIG_DRAM_CLK=480
-+CONFIG_DRAM_CLK=384
- CONFIG_DRAM_EMR1=4
- CONFIG_SYS_CLK_FREQ=912000000
- CONFIG_MMC0_CD_PIN="PH1"
-diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
-index 4b9d722..0ed969f 100644
---- a/configs/Cubieboard2_defconfig
-+++ b/configs/Cubieboard2_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN7I=y
--CONFIG_DRAM_CLK=480
-+CONFIG_DRAM_CLK=432
- CONFIG_MMC0_CD_PIN="PH1"
- CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
- # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
-old mode 100644
-new mode 100755
-index c884115..1380aba
---- a/configs/Cubieboard_defconfig
-+++ b/configs/Cubieboard_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN4I=y
--CONFIG_DRAM_CLK=480
-+CONFIG_DRAM_CLK=432
- CONFIG_MMC0_CD_PIN="PH1"
- CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
- # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
-index c3f0421..d45e160 100644
---- a/configs/Linksprite_pcDuino3_defconfig
-+++ b/configs/Linksprite_pcDuino3_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN7I=y
--CONFIG_DRAM_CLK=480
-+CONFIG_DRAM_CLK=408
- CONFIG_DRAM_ZQ=122
- CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
- # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
-old mode 100644
-new mode 100755
-index d9b1bd6..21428c9
---- a/configs/Bananapi_defconfig
-+++ b/configs/Bananapi_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN7I=y
--CONFIG_DRAM_CLK=432
-+CONFIG_DRAM_CLK=384
- CONFIG_VIDEO_COMPOSITE=y
- CONFIG_GMAC_TX_DELAY=3
- CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
-diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
-old mode 100644
-new mode 100755
-index 496c20e..46cff9d
---- a/configs/Bananapro_defconfig
-+++ b/configs/Bananapro_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN7I=y
--CONFIG_DRAM_CLK=432
-+CONFIG_DRAM_CLK=384
- CONFIG_USB1_VBUS_PIN="PH0"
- CONFIG_USB2_VBUS_PIN="PH1"
- CONFIG_VIDEO_COMPOSITE=y
-diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
-old mode 100644
-new mode 100755
-index 4e25392..7e6437f
---- a/configs/Cubietruck_defconfig
-+++ b/configs/Cubietruck_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN7I=y
--CONFIG_DRAM_CLK=432
-+CONFIG_DRAM_CLK=384
- CONFIG_MMC0_CD_PIN="PH1"
- CONFIG_USB0_VBUS_PIN="PH17"
- CONFIG_USB0_VBUS_DET="PH22"
-diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
-old mode 100644
-new mode 100755
-index d2111c6..3cad09d
---- a/configs/Lamobo_R1_defconfig
-+++ b/configs/Lamobo_R1_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN7I=y
--CONFIG_DRAM_CLK=432
-+CONFIG_DRAM_CLK=384
- CONFIG_MMC0_CD_PIN="PH10"
- CONFIG_GMAC_TX_DELAY=4
- CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
-diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
-old mode 100644
-new mode 100755
-index 00c671b..ccf97db
---- a/configs/Orangepi_defconfig
-+++ b/configs/Orangepi_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN7I=y
--CONFIG_DRAM_CLK=432
-+CONFIG_DRAM_CLK=384
- CONFIG_USB1_VBUS_PIN="PH26"
- CONFIG_USB2_VBUS_PIN="PH22"
- CONFIG_VIDEO_VGA=y
-diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
-old mode 100644
-new mode 100755
-index a865255..84b4b39
---- a/configs/Orangepi_mini_defconfig
-+++ b/configs/Orangepi_mini_defconfig
-@@ -1,7 +1,7 @@
- CONFIG_ARM=y
- CONFIG_ARCH_SUNXI=y
- CONFIG_MACH_SUN7I=y
--CONFIG_DRAM_CLK=432
-+CONFIG_DRAM_CLK=384
- CONFIG_MMC0_CD_PIN="PH10"
- CONFIG_MMC3_CD_PIN="PH11"
- CONFIG_MMC_SUNXI_SLOT_EXTRA=3
diff --git a/patch/u-boot/u-boot-next/add-awsom-uboot.patch b/patch/u-boot/u-boot-next/add-awsom-uboot.patch
deleted file mode 100644
index 578d6df3d..000000000
--- a/patch/u-boot/u-boot-next/add-awsom-uboot.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-===================================================================
---- /dev/null
-+++ u-boot-2015.01/configs/Awsom_defconfig
-@@ -0,0 +1,23 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_MACH_SUN7I=y
-+CONFIG_DRAM_CLK=480
-+CONFIG_DRAM_ZQ=127
-+CONFIG_DRAM_EMR1=4
-+CONFIG_MMC0_CD_PIN="PB9"
-+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_SPL=y
-+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
-+CONFIG_HUSH_PARSER=y
-+CONFIG_CMD_BOOTZ=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_CMD_FPGA is not set
-+CONFIG_CMD_DHCP=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_I2C=y
-+CONFIG_DM_ETH=y
-+CONFIG_ETH_DESIGNWARE=y
-+CONFIG_DM_SERIAL=y
-+CONFIG_USB=y
-+CONFIG_DM_USB=y
diff --git a/patch/u-boot/u-boot-next/add-lime2-emmc.patch b/patch/u-boot/u-boot-next/add-lime2-emmc.patch
deleted file mode 100644
index 3153ec03e..000000000
--- a/patch/u-boot/u-boot-next/add-lime2-emmc.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
-new file mode 100644
-index 0000000..e41a880
---- /dev/null
-+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
-@@ -0,0 +1,30 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_SPL_I2C_SUPPORT=y
-+CONFIG_MACH_SUN7I=y
-+CONFIG_DRAM_CLK=384
-+CONFIG_MMC0_CD_PIN="PH1"
-+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-+CONFIG_USB0_VBUS_PIN="PC17"
-+CONFIG_USB0_VBUS_DET="PH5"
-+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2-emmc"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
-+CONFIG_SPL=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+CONFIG_CMD_DFU=y
-+CONFIG_CMD_USB_MASS_STORAGE=y
-+# CONFIG_CMD_FPGA is not set
-+CONFIG_DFU_RAM=y
-+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
-+CONFIG_ETH_DESIGNWARE=y
-+CONFIG_AXP_ALDO3_VOLT=2800
-+CONFIG_AXP_ALDO4_VOLT=2800
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_MUSB_GADGET=y
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DOWNLOAD=y
-+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
-+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
-+CONFIG_G_DNL_PRODUCT_NUM=0x1010
diff --git a/patch/u-boot/u-boot-next/disable-usb-keyboards.patch b/patch/u-boot/u-boot-next/disable-usb-keyboards.patch
deleted file mode 100644
index 42ec7b6c3..000000000
--- a/patch/u-boot/u-boot-next/disable-usb-keyboards.patch
+++ /dev/null
@@ -1,12 +0,0 @@
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index e63309a..f443bc7 100644
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -659,7 +659,6 @@ config ARCH_SUNXI
- 	select SYS_NS16550
- 	select USB
- 	select USB_STORAGE
--	select USB_KEYBOARD
- 	select USE_TINY_PRINTF
- 
- config TARGET_TS4800
diff --git a/patch/u-boot/u-boot-next/sunxi-boot-splash.patch.disabled b/patch/u-boot/u-boot-next/sunxi-boot-splash.patch.disabled
deleted file mode 100644
index 8aa3e2df8..000000000
--- a/patch/u-boot/u-boot-next/sunxi-boot-splash.patch.disabled
+++ /dev/null
@@ -1,42 +0,0 @@
-diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
-old mode 100644
-new mode 100755
-index 3a360ca4..0423c08
---- a/include/config_distro_bootcmd.h
-+++ b/include/config_distro_bootcmd.h
-@@ -186,6 +186,9 @@
- 	BOOTENV_SHARED_SCSI \
- 	BOOTENV_SHARED_IDE \
- 	"boot_prefixes=/ /boot/\0" \
-+	"splashpos=m,m\0" \
-+	"splashimage=66000000\0" \
-+	"loadsplash=ext4load  mmc 0 ${splashimage} /boot/boot.bmp || fatload  mmc 0 ${splashimage} boot.bmp; bmp d ${splashimage}\0" \
- 	"boot_scripts=boot.scr.uimg boot.scr\0" \
- 	"boot_script_dhcp=boot.scr.uimg\0" \
- 	BOOTENV_BOOT_TARGETS \
-@@ -243,7 +245,7 @@
- 		"done\0"
- 
- #ifndef CONFIG_BOOTCOMMAND
--#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
-+#define CONFIG_BOOTCOMMAND "run loadsplash; run distro_bootcmd"
- #endif
- 
- #endif  /* _CONFIG_CMD_DISTRO_BOOTCMD_H */
-diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
-old mode 100644
-new mode 100755
-index 2d6b815..33a7b86
---- a/include/configs/sunxi-common.h
-+++ b/include/configs/sunxi-common.h
-@@ -10,6 +10,10 @@
-  * SPDX-License-Identifier:	GPL-2.0+
-  */
- 
-+#define CONFIG_SPLASH_SCREEN
-+#define CONFIG_SPLASH_SCREEN_ALIGN
-+#define CONFIG_CMD_BMP
-+#define CONFIG_VIDEO_BMP_RLE8
- #ifndef _SUNXI_COMMON_CONFIG_H
- #define _SUNXI_COMMON_CONFIG_H
- 
diff --git a/patch/u-boot/u-boot-next/u-boot-02-support-cheap-mmc.patch.disabled b/patch/u-boot/u-boot-next/u-boot-02-support-cheap-mmc.patch.disabled
deleted file mode 100644
index 678dff164..000000000
--- a/patch/u-boot/u-boot-next/u-boot-02-support-cheap-mmc.patch.disabled
+++ /dev/null
@@ -1,12 +0,0 @@
-diff -Nur a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
---- a/drivers/mmc/sunxi_mmc.c	2016-02-25 10:30:30.000000000 +0800
-+++ b//drivers/mmc/sunxi_mmc.c	2016-02-25 10:46:07.723851155 +0800
-
-@@ -269,6 +269,6 @@	
-	unsigned i;
-	unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
-	unsigned byte_cnt = data->blocksize * data->blocks;
--	unsigned timeout_msecs = byte_cnt >> 8;
-+	unsigned timeout_msecs = byte_cnt >> 6;
-	if (timeout_msecs < 2000)
-		timeout_msecs = 2000;
\ No newline at end of file
diff --git a/patch/u-boot/u-boot-odroidc1-default/ext4-boot-improvements.patch b/patch/u-boot/u-boot-odroidc1/ext4-boot-improvements.patch
similarity index 100%
rename from patch/u-boot/u-boot-odroidc1-default/ext4-boot-improvements.patch
rename to patch/u-boot/u-boot-odroidc1/ext4-boot-improvements.patch
diff --git a/patch/u-boot/u-boot-odroidc2-default/clean-sdfuse.patch.disabled b/patch/u-boot/u-boot-odroidc2-default/clean-sdfuse.patch.disabled
deleted file mode 100644
index 6fa5bbe98..000000000
--- a/patch/u-boot/u-boot-odroidc2-default/clean-sdfuse.patch.disabled
+++ /dev/null
@@ -1,14 +0,0 @@
-diff --git a/Makefile b/Makefile
-index 27153d8..d37f61f 100644
---- a/Makefile
-+++ b/Makefile
-@@ -1470,7 +1470,8 @@ help:
- 
- # Dummies...
- PHONY += prepare scripts
--prepare: ;
-+prepare: 
-+	@rm -f $(FUSING_FOLDER)/u-boot.bin
- scripts: ;
- 
- endif #ifeq ($(config-targets),1)
diff --git a/patch/u-boot/u-boot-odroidc2-default/firmware-override-toolchain-version.patch.disabled b/patch/u-boot/u-boot-odroidc2-default/firmware-override-toolchain-version.patch.disabled
deleted file mode 100644
index fdc83616f..000000000
--- a/patch/u-boot/u-boot-odroidc2-default/firmware-override-toolchain-version.patch.disabled
+++ /dev/null
@@ -1,25 +0,0 @@
-diff --git a/arch/arm/cpu/armv8/gxb/firmware/scp_task/Makefile b/arch/arm/cpu/armv8/gxb/firmware/scp_task/Makefile
-index 865d142..80bb4c9 100644
---- a/arch/arm/cpu/armv8/gxb/firmware/scp_task/Makefile
-+++ b/arch/arm/cpu/armv8/gxb/firmware/scp_task/Makefile
-@@ -6,7 +6,7 @@ include $(buildtree)/include/autoconf.mk
- include $(buildtree)/.config
- 
- # Select ARMv7-m bare-metal toolchain
--CROSS_COMPILE=arm-none-eabi-
-+override CROSS_COMPILE=arm-none-eabi-
- ASM=$(CROSS_COMPILE)as
- CC=$(CROSS_COMPILE)gcc
- CPP=$(CROSS_COMPILE)cpp
-@@ -67,7 +67,10 @@ OBJS += lib/delay.o
- 
- OBJS := $(OBJS:%=$(obj)/%)
- 
--all : clean $(obj)/bl301.out $(obj)/bl301.bin
-+all :
-+	$(MAKE) clean
-+	$(MAKE) $(obj)/bl301.out
-+	$(MAKE) $(obj)/bl301.bin
- 
- $(obj)/bl301.bin: $(obj)/bl301.out
- 	@echo "	OBJCOPY $@"
diff --git a/patch/u-boot/u-boot-odroidc2-default/support-ext4-boot-part.patch b/patch/u-boot/u-boot-odroidc2/support-ext4-boot-part.patch
similarity index 100%
rename from patch/u-boot/u-boot-odroidc2-default/support-ext4-boot-part.patch
rename to patch/u-boot/u-boot-odroidc2/support-ext4-boot-part.patch
diff --git a/patch/u-boot/u-boot-odroidxu-next/odroid-xu4_defconfig.patch b/patch/u-boot/u-boot-odroidxu-next/odroid-xu4_defconfig.patch
deleted file mode 100644
index 784614e3a..000000000
--- a/patch/u-boot/u-boot-odroidxu-next/odroid-xu4_defconfig.patch
+++ /dev/null
@@ -1,687 +0,0 @@
-*** /dev/null	Thu Sep 22 05:30:40 2016
---- test/configs/odroid-xu4_defconfig	Thu Sep 22 06:46:01 2016
-***************
-*** 0 ****
---- 1,682 ----
-+ #
-+ # Automatically generated file; DO NOT EDIT.
-+ # U-Boot 2016.05 Configuration
-+ #
-+ CONFIG_CREATE_ARCH_SYMLINK=y
-+ CONFIG_HAVE_GENERIC_BOARD=y
-+ CONFIG_SYS_GENERIC_BOARD=y
-+ # CONFIG_ARC is not set
-+ CONFIG_ARM=y
-+ # CONFIG_AVR32 is not set
-+ # CONFIG_BLACKFIN is not set
-+ # CONFIG_M68K is not set
-+ # CONFIG_MICROBLAZE is not set
-+ # CONFIG_MIPS is not set
-+ # CONFIG_NDS32 is not set
-+ # CONFIG_NIOS2 is not set
-+ # CONFIG_OPENRISC is not set
-+ # CONFIG_PPC is not set
-+ # CONFIG_SANDBOX is not set
-+ # CONFIG_SH is not set
-+ # CONFIG_SPARC is not set
-+ # CONFIG_X86 is not set
-+ CONFIG_SYS_ARCH="arm"
-+ CONFIG_SYS_CPU="armv7"
-+ CONFIG_SYS_SOC="exynos"
-+ CONFIG_SYS_VENDOR="samsung"
-+ CONFIG_SYS_BOARD="smdk5420"
-+ CONFIG_SYS_CONFIG_NAME="odroid_xu3"
-+ 
-+ #
-+ # ARM architecture
-+ #
-+ CONFIG_HAS_VBAR=y
-+ CONFIG_HAS_THUMB2=y
-+ CONFIG_CPU_V7=y
-+ # CONFIG_SEMIHOSTING is not set
-+ # CONFIG_SYS_L2CACHE_OFF is not set
-+ # CONFIG_ARCH_AT91 is not set
-+ # CONFIG_TARGET_EDB93XX is not set
-+ # CONFIG_TARGET_VCMA9 is not set
-+ # CONFIG_TARGET_SMDK2410 is not set
-+ # CONFIG_TARGET_ASPENITE is not set
-+ # CONFIG_TARGET_GPLUGD is not set
-+ # CONFIG_ARCH_DAVINCI is not set
-+ # CONFIG_KIRKWOOD is not set
-+ # CONFIG_ARCH_MVEBU is not set
-+ # CONFIG_TARGET_DEVKIT3250 is not set
-+ # CONFIG_TARGET_WORK_92105 is not set
-+ # CONFIG_TARGET_MX25PDK is not set
-+ # CONFIG_TARGET_ZMX25 is not set
-+ # CONFIG_TARGET_APF27 is not set
-+ # CONFIG_TARGET_APX4DEVKIT is not set
-+ # CONFIG_TARGET_XFI3 is not set
-+ # CONFIG_TARGET_M28EVK is not set
-+ # CONFIG_TARGET_MX23EVK is not set
-+ # CONFIG_TARGET_MX28EVK is not set
-+ # CONFIG_TARGET_MX23_OLINUXINO is not set
-+ # CONFIG_TARGET_BG0900 is not set
-+ # CONFIG_TARGET_SANSA_FUZE_PLUS is not set
-+ # CONFIG_TARGET_SC_SPS_1 is not set
-+ # CONFIG_ORION5X is not set
-+ # CONFIG_TARGET_SPEAR300 is not set
-+ # CONFIG_TARGET_SPEAR310 is not set
-+ # CONFIG_TARGET_SPEAR320 is not set
-+ # CONFIG_TARGET_SPEAR600 is not set
-+ # CONFIG_TARGET_STV0991 is not set
-+ # CONFIG_TARGET_X600 is not set
-+ # CONFIG_TARGET_IMX31_PHYCORE is not set
-+ # CONFIG_TARGET_MX31ADS is not set
-+ # CONFIG_TARGET_MX31PDK is not set
-+ # CONFIG_TARGET_WOODBURN is not set
-+ # CONFIG_TARGET_WOODBURN_SD is not set
-+ # CONFIG_TARGET_FLEA3 is not set
-+ # CONFIG_TARGET_MX35PDK is not set
-+ # CONFIG_ARCH_BCM283X is not set
-+ # CONFIG_TARGET_VEXPRESS_CA15_TC2 is not set
-+ # CONFIG_TARGET_VEXPRESS_CA5X2 is not set
-+ # CONFIG_TARGET_VEXPRESS_CA9X4 is not set
-+ # CONFIG_TARGET_KWB is not set
-+ # CONFIG_TARGET_TSERIES is not set
-+ # CONFIG_TARGET_CM_T335 is not set
-+ # CONFIG_TARGET_PEPPER is not set
-+ # CONFIG_TARGET_AM335X_IGEP0033 is not set
-+ # CONFIG_TARGET_PCM051 is not set
-+ # CONFIG_TARGET_DRACO is not set
-+ # CONFIG_TARGET_THUBAN is not set
-+ # CONFIG_TARGET_RASTABAN is not set
-+ # CONFIG_TARGET_PXM2 is not set
-+ # CONFIG_TARGET_RUT is not set
-+ # CONFIG_TARGET_PENGWYN is not set
-+ # CONFIG_TARGET_AM335X_BALTOS is not set
-+ # CONFIG_TARGET_AM335X_EVM is not set
-+ # CONFIG_TARGET_AM335X_SL50 is not set
-+ # CONFIG_TARGET_AM43XX_EVM is not set
-+ # CONFIG_TARGET_BAV335X is not set
-+ # CONFIG_TARGET_TI814X_EVM is not set
-+ # CONFIG_TARGET_TI816X_EVM is not set
-+ # CONFIG_TARGET_BCM28155_AP is not set
-+ # CONFIG_TARGET_BCMCYGNUS is not set
-+ # CONFIG_TARGET_BCMNSP is not set
-+ CONFIG_ARCH_EXYNOS=y
-+ # CONFIG_ARCH_S5PC1XX is not set
-+ # CONFIG_ARCH_HIGHBANK is not set
-+ # CONFIG_ARCH_INTEGRATOR is not set
-+ # CONFIG_ARCH_KEYSTONE is not set
-+ # CONFIG_ARCH_MX7 is not set
-+ # CONFIG_ARCH_MX6 is not set
-+ # CONFIG_ARCH_MX5 is not set
-+ # CONFIG_TARGET_M53EVK is not set
-+ # CONFIG_TARGET_MX51EVK is not set
-+ # CONFIG_TARGET_MX53ARD is not set
-+ # CONFIG_TARGET_MX53EVK is not set
-+ # CONFIG_TARGET_MX53LOCO is not set
-+ # CONFIG_TARGET_MX53SMD is not set
-+ # CONFIG_OMAP34XX is not set
-+ # CONFIG_OMAP44XX is not set
-+ # CONFIG_OMAP54XX is not set
-+ # CONFIG_RMOBILE is not set
-+ # CONFIG_ARCH_SNAPDRAGON is not set
-+ # CONFIG_ARCH_SOCFPGA is not set
-+ # CONFIG_TARGET_CM_T43 is not set
-+ # CONFIG_ARCH_SUNXI is not set
-+ # CONFIG_TARGET_TS4800 is not set
-+ # CONFIG_TARGET_VF610TWR is not set
-+ # CONFIG_TARGET_COLIBRI_VF is not set
-+ # CONFIG_TARGET_PCM052 is not set
-+ # CONFIG_ARCH_ZYNQ is not set
-+ # CONFIG_ARCH_ZYNQMP is not set
-+ # CONFIG_TEGRA is not set
-+ # CONFIG_TARGET_VEXPRESS64_AEMV8A is not set
-+ # CONFIG_TARGET_VEXPRESS64_BASE_FVP is not set
-+ # CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM is not set
-+ # CONFIG_TARGET_VEXPRESS64_JUNO is not set
-+ # CONFIG_TARGET_LS2080A_EMU is not set
-+ # CONFIG_TARGET_LS2080A_SIMU is not set
-+ # CONFIG_TARGET_LS2080AQDS is not set
-+ # CONFIG_TARGET_LS2080ARDB is not set
-+ # CONFIG_TARGET_HIKEY is not set
-+ # CONFIG_TARGET_LS1021AQDS is not set
-+ # CONFIG_TARGET_LS1021ATWR is not set
-+ # CONFIG_TARGET_LS1043AQDS is not set
-+ # CONFIG_TARGET_LS1043ARDB is not set
-+ # CONFIG_TARGET_H2200 is not set
-+ # CONFIG_TARGET_ZIPITZ2 is not set
-+ # CONFIG_TARGET_COLIBRI_PXA270 is not set
-+ # CONFIG_ARCH_UNIPHIER is not set
-+ # CONFIG_STM32 is not set
-+ # CONFIG_ARCH_ROCKCHIP is not set
-+ # CONFIG_TARGET_THUNDERX_88XX is not set
-+ # CONFIG_TARGET_SMDKV310 is not set
-+ # CONFIG_TARGET_TRATS is not set
-+ # CONFIG_TARGET_S5PC210_UNIVERSAL is not set
-+ # CONFIG_TARGET_ORIGEN is not set
-+ # CONFIG_TARGET_TRATS2 is not set
-+ # CONFIG_TARGET_ODROID is not set
-+ CONFIG_TARGET_ODROID_XU3=y
-+ # CONFIG_TARGET_ARNDALE is not set
-+ # CONFIG_TARGET_SMDK5250 is not set
-+ # CONFIG_TARGET_SNOW is not set
-+ # CONFIG_TARGET_SPRING is not set
-+ # CONFIG_TARGET_SMDK5420 is not set
-+ # CONFIG_TARGET_PEACH_PI is not set
-+ # CONFIG_TARGET_PEACH_PIT is not set
-+ CONFIG_SYS_MALLOC_F_LEN=0x400
-+ CONFIG_SYS_MALLOC_F=y
-+ CONFIG_DM_SERIAL=y
-+ CONFIG_DM_SPI=y
-+ CONFIG_DM_SPI_FLASH=y
-+ CONFIG_DM_I2C=y
-+ CONFIG_DM_GPIO=y
-+ # CONFIG_ARMV7_LPAE is not set
-+ 
-+ #
-+ # ARM debug
-+ #
-+ # CONFIG_DEBUG_LL is not set
-+ CONFIG_DM_KEYBOARD=y
-+ CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
-+ # CONFIG_I8042_KEYB is not set
-+ 
-+ #
-+ # General setup
-+ #
-+ CONFIG_LOCALVERSION=""
-+ CONFIG_LOCALVERSION_AUTO=y
-+ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+ CONFIG_EXPERT=y
-+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+ 
-+ #
-+ # Boot images
-+ #
-+ CONFIG_FIT=y
-+ # CONFIG_FIT_VERBOSE is not set
-+ # CONFIG_FIT_SIGNATURE is not set
-+ CONFIG_FIT_BEST_MATCH=y
-+ # CONFIG_OF_BOARD_SETUP is not set
-+ # CONFIG_OF_SYSTEM_SETUP is not set
-+ # CONFIG_OF_STDOUT_VIA_ALIAS is not set
-+ CONFIG_SYS_EXTRA_OPTIONS=""
-+ # CONFIG_SPL_LOAD_FIT is not set
-+ 
-+ #
-+ # Boot timing
-+ #
-+ # CONFIG_BOOTSTAGE is not set
-+ CONFIG_BOOTSTAGE_USER_COUNT=20
-+ CONFIG_BOOTSTAGE_STASH_ADDR=0
-+ CONFIG_BOOTSTAGE_STASH_SIZE=4096
-+ # CONFIG_CONSOLE_RECORD is not set
-+ 
-+ #
-+ # Command line interface
-+ #
-+ CONFIG_CMDLINE=y
-+ CONFIG_HUSH_PARSER=y
-+ CONFIG_SYS_HUSH_PARSER=y
-+ CONFIG_SYS_PROMPT="ODROID-XU4 # "
-+ 
-+ #
-+ # Autoboot options
-+ #
-+ CONFIG_AUTOBOOT_KEYED=y
-+ CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, press <ESC> to stop\n"
-+ # CONFIG_AUTOBOOT_ENCRYPTION is not set
-+ CONFIG_AUTOBOOT_DELAY_STR=""
-+ CONFIG_AUTOBOOT_STOP_STR="\x1b"
-+ # CONFIG_AUTOBOOT_KEYED_CTRLC is not set
-+ 
-+ #
-+ # Commands
-+ #
-+ 
-+ #
-+ # Info commands
-+ #
-+ CONFIG_CMD_BDI=y
-+ CONFIG_CMD_CONSOLE=y
-+ # CONFIG_CMD_CPU is not set
-+ # CONFIG_CMD_LICENSE is not set
-+ 
-+ #
-+ # Boot commands
-+ #
-+ CONFIG_CMD_BOOTD=y
-+ CONFIG_CMD_BOOTM=y
-+ CONFIG_CMD_BOOTZ=y
-+ CONFIG_CMD_BOOTEFI=y
-+ CONFIG_CMD_ELF=y
-+ CONFIG_CMD_FDT=y
-+ CONFIG_CMD_GO=y
-+ CONFIG_CMD_RUN=y
-+ CONFIG_CMD_IMI=y
-+ # CONFIG_CMD_IMLS is not set
-+ CONFIG_CMD_XIMG=y
-+ 
-+ #
-+ # Environment commands
-+ #
-+ # CONFIG_CMD_ASKENV is not set
-+ CONFIG_CMD_EXPORTENV=y
-+ CONFIG_CMD_IMPORTENV=y
-+ CONFIG_CMD_EDITENV=y
-+ # CONFIG_CMD_GREPENV is not set
-+ CONFIG_CMD_SAVEENV=y
-+ CONFIG_CMD_ENV_EXISTS=y
-+ 
-+ #
-+ # Memory commands
-+ #
-+ CONFIG_CMD_MEMORY=y
-+ CONFIG_CMD_CRC32=y
-+ # CONFIG_LOOPW is not set
-+ # CONFIG_CMD_MEMTEST is not set
-+ # CONFIG_CMD_MX_CYCLIC is not set
-+ # CONFIG_CMD_MEMINFO is not set
-+ 
-+ #
-+ # Device access commands
-+ #
-+ CONFIG_CMD_DM=y
-+ # CONFIG_CMD_DEMO is not set
-+ CONFIG_CMD_LOADB=y
-+ CONFIG_CMD_LOADS=y
-+ CONFIG_CMD_FLASH=y
-+ # CONFIG_CMD_ARMFLASH is not set
-+ CONFIG_CMD_MMC=y
-+ # CONFIG_CMD_NAND is not set
-+ # CONFIG_CMD_SF is not set
-+ # CONFIG_CMD_SPI is not set
-+ CONFIG_CMD_I2C=y
-+ CONFIG_CMD_USB=y
-+ CONFIG_CMD_DFU=y
-+ CONFIG_CMD_USB_MASS_STORAGE=y
-+ CONFIG_CMD_FPGA=y
-+ CONFIG_CMD_GPIO=y
-+ 
-+ #
-+ # Shell scripting commands
-+ #
-+ CONFIG_CMD_ECHO=y
-+ CONFIG_CMD_ITEST=y
-+ CONFIG_CMD_SOURCE=y
-+ # CONFIG_CMD_SETEXPR is not set
-+ 
-+ #
-+ # Network commands
-+ #
-+ CONFIG_CMD_NET=y
-+ # CONFIG_CMD_TFTPPUT is not set
-+ # CONFIG_CMD_TFTPSRV is not set
-+ # CONFIG_CMD_RARP is not set
-+ CONFIG_CMD_DHCP=y
-+ CONFIG_CMD_NFS=y
-+ CONFIG_CMD_MII=y
-+ CONFIG_CMD_PING=y
-+ # CONFIG_CMD_CDP is not set
-+ # CONFIG_CMD_SNTP is not set
-+ # CONFIG_CMD_DNS is not set
-+ # CONFIG_CMD_LINK_LOCAL is not set
-+ 
-+ #
-+ # Misc commands
-+ #
-+ CONFIG_CMD_CACHE=y
-+ CONFIG_CMD_TIME=y
-+ CONFIG_CMD_MISC=y
-+ # CONFIG_CMD_TIMER is not set
-+ 
-+ #
-+ # Power commands
-+ #
-+ CONFIG_CMD_PMIC=y
-+ # CONFIG_CMD_REGULATOR is not set
-+ 
-+ #
-+ # Security commands
-+ #
-+ 
-+ #
-+ # Filesystem commands
-+ #
-+ CONFIG_CMD_EXT2=y
-+ CONFIG_CMD_EXT4=y
-+ CONFIG_CMD_EXT4_WRITE=y
-+ CONFIG_CMD_FAT=y
-+ CONFIG_CMD_FS_GENERIC=y
-+ CONFIG_SUPPORT_OF_CONTROL=y
-+ 
-+ #
-+ # Device Tree Control
-+ #
-+ CONFIG_OF_CONTROL=y
-+ CONFIG_OF_SEPARATE=y
-+ # CONFIG_OF_EMBED is not set
-+ CONFIG_NET=y
-+ # CONFIG_NET_RANDOM_ETHADDR is not set
-+ # CONFIG_NETCONSOLE is not set
-+ CONFIG_NET_TFTP_VARS=y
-+ 
-+ #
-+ # Device Drivers
-+ #
-+ 
-+ #
-+ # Generic Driver Options
-+ #
-+ CONFIG_DM=y
-+ CONFIG_DM_WARN=y
-+ CONFIG_DM_DEVICE_REMOVE=y
-+ CONFIG_DM_STDIO=y
-+ CONFIG_DM_SEQ_ALIAS=y
-+ # CONFIG_SPL_DM_SEQ_ALIAS is not set
-+ # CONFIG_REGMAP is not set
-+ # CONFIG_SPL_REGMAP is not set
-+ # CONFIG_DEVRES is not set
-+ CONFIG_SIMPLE_BUS=y
-+ CONFIG_OF_TRANSLATE=y
-+ CONFIG_ADC=y
-+ CONFIG_ADC_EXYNOS=y
-+ # CONFIG_ADC_SANDBOX is not set
-+ # CONFIG_BLK is not set
-+ CONFIG_DISK=y
-+ # CONFIG_BLOCK_CACHE is not set
-+ 
-+ #
-+ # Clock
-+ #
-+ # CONFIG_CLK is not set
-+ # CONFIG_CPU is not set
-+ 
-+ #
-+ # Hardware crypto devices
-+ #
-+ # CONFIG_FSL_CAAM is not set
-+ 
-+ #
-+ # Demo for driver model
-+ #
-+ # CONFIG_DM_DEMO is not set
-+ 
-+ #
-+ # DFU support
-+ #
-+ # CONFIG_DFU_TFTP is not set
-+ 
-+ #
-+ # DMA Support
-+ #
-+ # CONFIG_DMA is not set
-+ # CONFIG_TI_EDMA3 is not set
-+ 
-+ #
-+ # GPIO Support
-+ #
-+ # CONFIG_ALTERA_PIO is not set
-+ # CONFIG_DWAPB_GPIO is not set
-+ # CONFIG_ATMEL_PIO4 is not set
-+ # CONFIG_INTEL_BROADWELL_GPIO is not set
-+ # CONFIG_LPC32XX_GPIO is not set
-+ # CONFIG_MSM_GPIO is not set
-+ # CONFIG_ROCKCHIP_GPIO is not set
-+ # CONFIG_VYBRID_GPIO is not set
-+ 
-+ #
-+ # I2C support
-+ #
-+ CONFIG_DM_I2C_COMPAT=y
-+ # CONFIG_DM_I2C_GPIO is not set
-+ # CONFIG_SYS_I2C_INTEL is not set
-+ # CONFIG_SYS_I2C_ROCKCHIP is not set
-+ # CONFIG_I2C_MUX is not set
-+ # CONFIG_CROS_EC_KEYB is not set
-+ 
-+ #
-+ # LED Support
-+ #
-+ # CONFIG_LED is not set
-+ 
-+ #
-+ # Memory Controller drivers
-+ #
-+ 
-+ #
-+ # Multifunction device drivers
-+ #
-+ # CONFIG_MISC is not set
-+ # CONFIG_CROS_EC is not set
-+ # CONFIG_FSL_SEC_MON is not set
-+ # CONFIG_MXC_OCOTP is not set
-+ # CONFIG_PWRSEQ is not set
-+ # CONFIG_PCA9551_LED is not set
-+ # CONFIG_RESET is not set
-+ # CONFIG_WINBOND_W83627 is not set
-+ 
-+ #
-+ # MMC Host controller Support
-+ #
-+ # CONFIG_DM_MMC is not set
-+ 
-+ #
-+ # MTD Support
-+ #
-+ # CONFIG_MTD is not set
-+ 
-+ #
-+ # NAND Device Support
-+ #
-+ # CONFIG_NAND_DENALI is not set
-+ # CONFIG_NAND_VF610_NFC is not set
-+ # CONFIG_NAND_PXA3XX is not set
-+ # CONFIG_NAND_ARASAN is not set
-+ 
-+ #
-+ # Generic NAND options
-+ #
-+ 
-+ #
-+ # SPI Flash Support
-+ #
-+ # CONFIG_SPI_FLASH is not set
-+ # CONFIG_DM_ETH is not set
-+ # CONFIG_PHYLIB is not set
-+ # CONFIG_NETDEVICES is not set
-+ 
-+ #
-+ # PCI
-+ #
-+ # CONFIG_DM_PCI is not set
-+ 
-+ #
-+ # Pin controllers
-+ #
-+ # CONFIG_PINCTRL is not set
-+ 
-+ #
-+ # Power
-+ #
-+ CONFIG_DM_PMIC=y
-+ CONFIG_PMIC_CHILDREN=y
-+ CONFIG_SPL_PMIC_CHILDREN=y
-+ # CONFIG_PMIC_ACT8846 is not set
-+ # CONFIG_DM_PMIC_PFUZE100 is not set
-+ # CONFIG_DM_PMIC_MAX77686 is not set
-+ # CONFIG_PMIC_PM8916 is not set
-+ # CONFIG_PMIC_RK808 is not set
-+ CONFIG_PMIC_S2MPS11=y
-+ # CONFIG_DM_PMIC_SANDBOX is not set
-+ # CONFIG_PMIC_S5M8767 is not set
-+ # CONFIG_PMIC_TPS65090 is not set
-+ CONFIG_DM_REGULATOR=y
-+ # CONFIG_SPL_DM_REGULATOR is not set
-+ # CONFIG_DM_REGULATOR_FIXED is not set
-+ # CONFIG_DM_PWM is not set
-+ # CONFIG_RAM is not set
-+ 
-+ #
-+ # Remote Processor drivers
-+ #
-+ 
-+ #
-+ # Real Time Clock
-+ #
-+ # CONFIG_DM_RTC is not set
-+ 
-+ #
-+ # Serial drivers
-+ #
-+ CONFIG_REQUIRE_SERIAL_CONSOLE=y
-+ CONFIG_SERIAL_PRESENT=y
-+ CONFIG_SPL_SERIAL_PRESENT=y
-+ # CONFIG_DEBUG_UART is not set
-+ # CONFIG_DEBUG_UART_SKIP_INIT is not set
-+ # CONFIG_ALTERA_JTAG_UART is not set
-+ # CONFIG_ALTERA_UART is not set
-+ # CONFIG_FSL_LPUART is not set
-+ # CONFIG_SYS_NS16550 is not set
-+ # CONFIG_MSM_SERIAL is not set
-+ 
-+ #
-+ # Sound support
-+ #
-+ # CONFIG_SOUND is not set
-+ 
-+ #
-+ # SPI Support
-+ #
-+ # CONFIG_ALTERA_SPI is not set
-+ # CONFIG_CADENCE_QSPI is not set
-+ # CONFIG_DESIGNWARE_SPI is not set
-+ # CONFIG_EXYNOS_SPI is not set
-+ # CONFIG_FSL_DSPI is not set
-+ # CONFIG_FSL_QSPI is not set
-+ # CONFIG_ICH_SPI is not set
-+ # CONFIG_ROCKCHIP_SPI is not set
-+ # CONFIG_TEGRA114_SPI is not set
-+ # CONFIG_TEGRA20_SFLASH is not set
-+ # CONFIG_TEGRA20_SLINK is not set
-+ # CONFIG_TEGRA210_QSPI is not set
-+ # CONFIG_XILINX_SPI is not set
-+ # CONFIG_OMAP3_SPI is not set
-+ # CONFIG_FSL_ESPI is not set
-+ # CONFIG_TI_QSPI is not set
-+ 
-+ #
-+ # SPMI support
-+ #
-+ # CONFIG_SPMI is not set
-+ # CONFIG_DM_THERMAL is not set
-+ 
-+ #
-+ # Timer Support
-+ #
-+ # CONFIG_TIMER is not set
-+ 
-+ #
-+ # TPM support
-+ #
-+ CONFIG_USB=y
-+ CONFIG_DM_USB=y
-+ 
-+ #
-+ # USB Host Controller Drivers
-+ #
-+ # CONFIG_USB_XHCI_HCD is not set
-+ # CONFIG_USB_XHCI is not set
-+ # CONFIG_USB_OHCI_GENERIC is not set
-+ # CONFIG_USB_EHCI_HCD is not set
-+ # CONFIG_USB_EHCI is not set
-+ CONFIG_USB_DWC3=y
-+ # CONFIG_USB_DWC3_HOST is not set
-+ CONFIG_USB_DWC3_GADGET=y
-+ 
-+ #
-+ # Platform Glue Driver Support
-+ #
-+ # CONFIG_USB_DWC3_OMAP is not set
-+ 
-+ #
-+ # PHY Subsystem
-+ #
-+ # CONFIG_USB_DWC3_PHY_OMAP is not set
-+ CONFIG_USB_DWC3_PHY_SAMSUNG=y
-+ 
-+ #
-+ # MUSB Controller Driver
-+ #
-+ # CONFIG_USB_MUSB_HOST is not set
-+ # CONFIG_USB_MUSB_GADGET is not set
-+ 
-+ #
-+ # ULPI drivers
-+ #
-+ 
-+ #
-+ # USB peripherals
-+ #
-+ # CONFIG_USB_STORAGE is not set
-+ # CONFIG_USB_KEYBOARD is not set
-+ CONFIG_USB_GADGET=y
-+ # CONFIG_USB_GADGET_ATMEL_USBA is not set
-+ # CONFIG_USB_GADGET_DWC2_OTG is not set
-+ # CONFIG_CI_UDC is not set
-+ CONFIG_USB_GADGET_VBUS_DRAW=2
-+ CONFIG_USB_GADGET_DUALSPEED=y
-+ CONFIG_USB_GADGET_DOWNLOAD=y
-+ CONFIG_G_DNL_MANUFACTURER="Samsung"
-+ CONFIG_G_DNL_VENDOR_NUM=0x04e8
-+ CONFIG_G_DNL_PRODUCT_NUM=0x6601
-+ 
-+ #
-+ # Graphics support
-+ #
-+ # CONFIG_DM_VIDEO is not set
-+ 
-+ #
-+ # TrueType Fonts
-+ #
-+ # CONFIG_VIDEO_VESA is not set
-+ # CONFIG_VIDEO_LCD_ANX9804 is not set
-+ # CONFIG_VIDEO_LCD_SSD2828 is not set
-+ # CONFIG_VIDEO_MVEBU is not set
-+ # CONFIG_I2C_EDID is not set
-+ # CONFIG_DISPLAY is not set
-+ # CONFIG_VIDEO_TEGRA20 is not set
-+ # CONFIG_VIDEO_BRIDGE is not set
-+ # CONFIG_PHYS_TO_BUS is not set
-+ 
-+ #
-+ # File systems
-+ #
-+ 
-+ #
-+ # Library routines
-+ #
-+ # CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
-+ CONFIG_HAVE_PRIVATE_LIBGCC=y
-+ # CONFIG_USE_PRIVATE_LIBGCC is not set
-+ CONFIG_SYS_HZ=1000
-+ # CONFIG_USE_TINY_PRINTF is not set
-+ CONFIG_REGEX=y
-+ # CONFIG_LIB_RAND is not set
-+ # CONFIG_CMD_DHRYSTONE is not set
-+ # CONFIG_RSA is not set
-+ # CONFIG_TPM is not set
-+ 
-+ #
-+ # Hashing Support
-+ #
-+ # CONFIG_SHA1 is not set
-+ # CONFIG_SHA256 is not set
-+ # CONFIG_SHA_HW_ACCEL is not set
-+ 
-+ #
-+ # Compression Support
-+ #
-+ # CONFIG_LZ4 is not set
-+ CONFIG_ERRNO_STR=y
-+ CONFIG_OF_LIBFDT=y
-+ # CONFIG_SPL_OF_LIBFDT is not set
-+ CONFIG_EFI_LOADER=y
-+ # CONFIG_UNIT_TEST is not set
diff --git a/patch/u-boot/u-boot-odroidxu-default/enable-ext4.patch b/patch/u-boot/u-boot-odroidxu4-default/enable-ext4.patch
similarity index 100%
rename from patch/u-boot/u-boot-odroidxu-default/enable-ext4.patch
rename to patch/u-boot/u-boot-odroidxu4-default/enable-ext4.patch
diff --git a/patch/u-boot/u-boot-odroidxu-default/ext4-boot-improvements.patch b/patch/u-boot/u-boot-odroidxu4-default/ext4-boot-improvements.patch
similarity index 100%
rename from patch/u-boot/u-boot-odroidxu-default/ext4-boot-improvements.patch
rename to patch/u-boot/u-boot-odroidxu4-default/ext4-boot-improvements.patch
diff --git a/patch/u-boot/u-boot-odroidxu-default/ext4-fixes-pr-28.patch b/patch/u-boot/u-boot-odroidxu4-default/ext4-fixes-pr-28.patch
similarity index 100%
rename from patch/u-boot/u-boot-odroidxu-default/ext4-fixes-pr-28.patch
rename to patch/u-boot/u-boot-odroidxu4-default/ext4-fixes-pr-28.patch
diff --git a/patch/u-boot/u-boot-odroidxu-next/xu4_blobs.patch b/patch/u-boot/u-boot-odroidxu4-next/xu4_blobs.patch
similarity index 100%
rename from patch/u-boot/u-boot-odroidxu-next/xu4_blobs.patch
rename to patch/u-boot/u-boot-odroidxu4-next/xu4_blobs.patch
diff --git a/patch/u-boot/u-boot-odroidxu-next/xu4_sd_fusing.patch b/patch/u-boot/u-boot-odroidxu4-next/xu4_sd_fusing.patch
similarity index 100%
rename from patch/u-boot/u-boot-odroidxu-next/xu4_sd_fusing.patch
rename to patch/u-boot/u-boot-odroidxu4-next/xu4_sd_fusing.patch
diff --git a/patch/u-boot/u-boot-roseapple-default/ext4-boot-support.patch b/patch/u-boot/u-boot-roseapple/ext4-boot-support.patch
similarity index 100%
rename from patch/u-boot/u-boot-roseapple-default/ext4-boot-support.patch
rename to patch/u-boot/u-boot-roseapple/ext4-boot-support.patch
diff --git a/patch/u-boot/u-boot-s500-default/ext4-boot-support.patch b/patch/u-boot/u-boot-s500/ext4-boot-support.patch
similarity index 100%
rename from patch/u-boot/u-boot-s500-default/ext4-boot-support.patch
rename to patch/u-boot/u-boot-s500/ext4-boot-support.patch
diff --git a/patch/u-boot/u-boot-default/a10_a20_dram-clk.patch b/patch/u-boot/u-boot-sunxi/a10_a20_dram-clk.patch
similarity index 100%
rename from patch/u-boot/u-boot-default/a10_a20_dram-clk.patch
rename to patch/u-boot/u-boot-sunxi/a10_a20_dram-clk.patch
diff --git a/patch/u-boot/u-boot-default/add-awsom-uboot.patch b/patch/u-boot/u-boot-sunxi/add-awsom-uboot.patch
similarity index 100%
rename from patch/u-boot/u-boot-default/add-awsom-uboot.patch
rename to patch/u-boot/u-boot-sunxi/add-awsom-uboot.patch
diff --git a/patch/u-boot/u-boot-default/add-lime2-emmc.patch b/patch/u-boot/u-boot-sunxi/add-lime2-emmc.patch
similarity index 100%
rename from patch/u-boot/u-boot-default/add-lime2-emmc.patch
rename to patch/u-boot/u-boot-sunxi/add-lime2-emmc.patch
diff --git a/patch/u-boot/u-boot-default/add-missing-h3-boards.patch b/patch/u-boot/u-boot-sunxi/add-missing-h3-boards.patch
similarity index 100%
rename from patch/u-boot/u-boot-default/add-missing-h3-boards.patch
rename to patch/u-boot/u-boot-sunxi/add-missing-h3-boards.patch
diff --git a/patch/u-boot/u-boot-default/adjust-h3-dram-frequency.patch b/patch/u-boot/u-boot-sunxi/adjust-h3-dram-frequency.patch
similarity index 100%
rename from patch/u-boot/u-boot-default/adjust-h3-dram-frequency.patch
rename to patch/u-boot/u-boot-sunxi/adjust-h3-dram-frequency.patch
diff --git a/patch/u-boot/u-boot-default/cubieboard1.patch b/patch/u-boot/u-boot-sunxi/cubieboard1.patch
similarity index 93%
rename from patch/u-boot/u-boot-default/cubieboard1.patch
rename to patch/u-boot/u-boot-sunxi/cubieboard1.patch
index 21961b82a..a9888c655 100644
--- a/patch/u-boot/u-boot-default/cubieboard1.patch
+++ b/patch/u-boot/u-boot-sunxi/cubieboard1.patch
@@ -10,5 +10,5 @@ index c884115..a45fbb0
  # CONFIG_CMD_FPGA is not set
 +CONFIG_CMD_GPIO=y
 +CONFIG_AXP_ALDO3_VOLT=2800
-+CONFIG_AXP_ALDO4_VOLT=2800  
++CONFIG_AXP_ALDO4_VOLT=2800
  CONFIG_USB_EHCI_HCD=y
diff --git a/patch/u-boot/u-boot-default/disable-usb-keyboards.patch b/patch/u-boot/u-boot-sunxi/disable-usb-keyboards.patch
similarity index 100%
rename from patch/u-boot/u-boot-default/disable-usb-keyboards.patch
rename to patch/u-boot/u-boot-sunxi/disable-usb-keyboards.patch
diff --git a/patch/u-boot/u-boot-default/fix-h3-rev3-dram-calibration.patch.disabled b/patch/u-boot/u-boot-sunxi/fix-h3-rev3-dram-calibration.patch.disabled
similarity index 100%
rename from patch/u-boot/u-boot-default/fix-h3-rev3-dram-calibration.patch.disabled
rename to patch/u-boot/u-boot-sunxi/fix-h3-rev3-dram-calibration.patch.disabled
diff --git a/patch/u-boot/u-boot-default/h3-enable-power-led.patch b/patch/u-boot/u-boot-sunxi/h3-enable-power-led.patch
similarity index 100%
rename from patch/u-boot/u-boot-default/h3-enable-power-led.patch
rename to patch/u-boot/u-boot-sunxi/h3-enable-power-led.patch
diff --git a/patch/u-boot/u-boot-default/sunxi-boot-splash.patch b/patch/u-boot/u-boot-sunxi/sunxi-boot-splash.patch
similarity index 100%
rename from patch/u-boot/u-boot-default/sunxi-boot-splash.patch
rename to patch/u-boot/u-boot-sunxi/sunxi-boot-splash.patch
diff --git a/patch/u-boot/u-boot-default/u-boot-01-led-support-default-state.patch.disabled b/patch/u-boot/u-boot-sunxi/u-boot-01-led-support-default-state.patch.disabled
similarity index 100%
rename from patch/u-boot/u-boot-default/u-boot-01-led-support-default-state.patch.disabled
rename to patch/u-boot/u-boot-sunxi/u-boot-01-led-support-default-state.patch.disabled
diff --git a/patch/u-boot/u-boot-default/u-boot-02-support-cheap-mmc.patch.disabled b/patch/u-boot/u-boot-sunxi/u-boot-02-support-cheap-mmc.patch.disabled
similarity index 100%
rename from patch/u-boot/u-boot-default/u-boot-02-support-cheap-mmc.patch.disabled
rename to patch/u-boot/u-boot-sunxi/u-boot-02-support-cheap-mmc.patch.disabled
diff --git a/patch/u-boot/u-boot-dev/u-boot-set-safe-axi_apb-clock-dividers.patch b/patch/u-boot/u-boot-sunxi/u-boot-set-safe-axi_apb-clock-dividers.patch
similarity index 100%
rename from patch/u-boot/u-boot-dev/u-boot-set-safe-axi_apb-clock-dividers.patch
rename to patch/u-boot/u-boot-sunxi/u-boot-set-safe-axi_apb-clock-dividers.patch
diff --git a/patch/u-boot/u-boot-udoo-default/neo-2015.04-u-boot.patch b/patch/u-boot/u-boot-udoo/neo-2015.04-u-boot.patch
similarity index 100%
rename from patch/u-boot/u-boot-udoo-default/neo-2015.04-u-boot.patch
rename to patch/u-boot/u-boot-udoo/neo-2015.04-u-boot.patch
diff --git a/patch/u-boot/u-boot-udoo-default/udoo-2015-u-boot.patch b/patch/u-boot/u-boot-udoo/udoo-2015-u-boot.patch
similarity index 100%
rename from patch/u-boot/u-boot-udoo-default/udoo-2015-u-boot.patch
rename to patch/u-boot/u-boot-udoo/udoo-2015-u-boot.patch