Merge branch 'master' into desktop

This commit is contained in:
Igor Pecovnik 2020-12-17 01:31:13 +01:00
commit e5bf887678
20 changed files with 9198 additions and 49 deletions

View file

@ -1,6 +1,6 @@
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 5.9.14 Kernel Configuration
# Linux/arm 5.9.15 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
CONFIG_CC_IS_GCC=y
@ -819,7 +819,6 @@ CONFIG_ZPOOL=y
CONFIG_ZBUD=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_PGTABLE_MAPPING is not set
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_IDLE_PAGE_TRACKING=y
@ -2746,11 +2745,15 @@ CONFIG_JOYSTICK_IFORCE_USB=m
# CONFIG_JOYSTICK_STINGER is not set
# CONFIG_JOYSTICK_TWIDJOY is not set
# CONFIG_JOYSTICK_ZHENHUA is not set
CONFIG_JOYSTICK_DB9=m
CONFIG_JOYSTICK_GAMECON=m
CONFIG_JOYSTICK_TURBOGRAFX=m
# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_WALKERA0701=m
# CONFIG_JOYSTICK_PSXPAD_SPI is not set
# CONFIG_JOYSTICK_PXRC is not set
# CONFIG_JOYSTICK_FSIA6B is not set

View file

@ -1,13 +1,13 @@
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 5.4.78 Kernel Configuration
# Linux/arm 5.4.84 Kernel Configuration
#
#
# Compiler: arm-none-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025
# Compiler: arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0
#
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=90201
CONFIG_GCC_VERSION=80300
CONFIG_CLANG_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_HAS_ASM_GOTO=y
@ -802,7 +802,6 @@ CONFIG_ZPOOL=y
CONFIG_ZBUD=y
CONFIG_Z3FOLD=m
CONFIG_ZSMALLOC=m
# CONFIG_PGTABLE_MAPPING is not set
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_IDLE_PAGE_TRACKING=y
@ -2776,11 +2775,15 @@ CONFIG_JOYSTICK_IFORCE_USB=m
# CONFIG_JOYSTICK_STINGER is not set
# CONFIG_JOYSTICK_TWIDJOY is not set
# CONFIG_JOYSTICK_ZHENHUA is not set
CONFIG_JOYSTICK_DB9=m
CONFIG_JOYSTICK_GAMECON=m
CONFIG_JOYSTICK_TURBOGRAFX=m
# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_WALKERA0701=m
# CONFIG_JOYSTICK_PSXPAD_SPI is not set
# CONFIG_JOYSTICK_PXRC is not set
# CONFIG_JOYSTICK_FSIA6B is not set

View file

@ -1,6 +1,6 @@
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 5.9.14 Kernel Configuration
# Linux/arm64 5.9.15 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
CONFIG_CC_IS_GCC=y
@ -860,7 +860,6 @@ CONFIG_ZPOOL=y
CONFIG_ZBUD=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_PGTABLE_MAPPING is not set
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set

View file

@ -1,13 +1,13 @@
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 5.4.78 Kernel Configuration
# Linux/arm64 5.4.84 Kernel Configuration
#
#
# Compiler: aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025
# Compiler: aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0
#
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=90201
CONFIG_GCC_VERSION=80300
CONFIG_CLANG_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_HAS_ASM_GOTO=y
@ -428,8 +428,6 @@ CONFIG_ARM64_SVE=y
CONFIG_ARM64_MODULE_PLTS=y
# CONFIG_ARM64_PSEUDO_NMI is not set
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features
#
@ -879,7 +877,6 @@ CONFIG_ZPOOL=y
CONFIG_ZBUD=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
# CONFIG_PGTABLE_MAPPING is not set
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set

View file

@ -408,7 +408,7 @@ format_nand()
show_nand_warning
dialog --title "$title" --backtitle "$backtitle" --infobox "\nFormating ... up to one minute." 5 40
dialog --title "$title" --backtitle "$backtitle" --infobox "\nFormatting ... up to one minute." 5 40
if [[ $DEVICE_TYPE = a20 ]]; then
(echo y;) | sunxi-nand-part -f a20 /dev/nand 65536 'bootloader 65536' 'linux 0' >> $logfile 2>&1
else

File diff suppressed because it is too large Load diff

View file

@ -2,12 +2,10 @@ diff --git a/scripts/package/builddeb b/scripts/package/builddeb
index 33cd2c3a..888a83d9 100755
--- a/scripts/package/builddeb
+++ b/scripts/package/builddeb
@@ -408,7 +408,8 @@ fi
@@ -323,6 +323,7 @@ fi
# Build kernel header package
(cd $srctree; find . -name Makefile\* -o -name Kconfig\* -o -name \*.pl) > "$objtree/debian/hdrsrcfiles"
-(cd $srctree; find arch/$SRCARCH/include include scripts -type f) >> "$objtree/debian/hdrsrcfiles"
+(cd $srctree; find arch/*/include include scripts -type f) >> "$objtree/debian/hdrsrcfiles"
(cd $srctree; find arch/*/include include scripts -type f -o -type l) >> "$objtree/debian/hdrsrcfiles"
+(cd $srctree; find security/*/include -type f) >> "$objtree/debian/hdrsrcfiles"
(cd $srctree; find arch/$SRCARCH -name module.lds -o -name Kbuild.platforms -o -name Platform) >> "$objtree/debian/hdrsrcfiles"
(cd $srctree; find $(find arch/$SRCARCH -name include -o -name scripts -type d) -type f) >> "$objtree/debian/hdrsrcfiles"

View file

@ -2,21 +2,23 @@ diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchi
index adfa8211..2c3a023a 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -15,7 +15,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
@@ -15,7 +15,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3399-nanopi-m4v2.dtb \
rk3399-nanopi4-rev22.dtb \
rk3399-kobol-helios64.dtb \
- rk3399-firefly.dtb
+ rk3399-firefly.dtb \
+ rk3399-roc-pc.dtb
+ rk3399-roc-pc.dtb \
+ rk3399-roc-pc-mezzanine.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3328-nanopi-r2-rev00.dtb
@@ -119,6 +120,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin-r0.dtb
@@ -119,6 +120,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin-r0.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin-r1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-mid-818-android-6.0.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-mid-818-android.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960-ab.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rv1-android.dtb
@ -46,6 +48,14 @@ index 00000000..cc922411
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts
new file mode 120000
index 00000000..0f6a3467
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts
@@ -0,0 +1 @@
+rk3399-roc-pc.dts
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mipi.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mipi.dts
new file mode 100644
index 00000000..b3145e99
@ -407,7 +417,7 @@ index 00000000..f871f0c5
+ compatible = "gpio-leds";
+ power {
+ label = "firefly:blue:power";
+ linux,default-trigger = "ir-power-click";
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";pinctrl-0 = <&led_power>;

View file

@ -0,0 +1,24 @@
From 3f90a9ef2e8d7e647572b2f2f2f54dce20c654c5 Mon Sep 17 00:00:00 2001
From: ashthespy <ashthespy@gmail.com>
Date: Mon, 3 Feb 2020 21:29:44 +0100
Subject: [PATCH 23/23] ASoC: rockchip: i2s: add compatible for rk3308
---
sound/soc/rockchip/rockchip_i2s.c | 1 +
1 files changed, 1 insertions(+)
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
index e6125ebfe5a9..dcee123b0939 100644
--- a/sound/soc/rockchip/rockchip_i2s.c
+++ b/sound/soc/rockchip/rockchip_i2s.c
@@ -598,6 +598,7 @@ static const struct of_device_id rockchip_i2s_match[] = {
{ .compatible = "rockchip,rk3066-i2s", },
{ .compatible = "rockchip,rk3128-i2s", },
{ .compatible = "rockchip,rk3188-i2s", },
+ { .compatible = "rockchip,rk3308-i2s", },
{ .compatible = "rockchip,rk3288-i2s", },
{ .compatible = "rockchip,rk3308-i2s", },
{ .compatible = "rockchip,rk3328-i2s", },
--
2.25.1

View file

@ -0,0 +1,23 @@
--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts 2020-08-30 17:11:49.162572017 +0300
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts 2020-08-30 17:12:00.122550893 +0300
@@ -12,7 +12,7 @@
compatible = "radxa,rockpis", "rockchip,rk3308";
chosen {
- stdout-path = "serial0:1500000n8";
+ stdout-path = "serial2:1500000n8";
};
leds {
@@ -326,6 +326,10 @@
status = "okay";
};
+&uart2 {
+ status = "okay";
+};
+
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_xfer &uart4_rts &uart4_cts>;

View file

@ -0,0 +1,95 @@
This patch adds usb2-phy support for RK3308 SoCs and amend phy Documentation.
Signed-off-by: Akash Gajjar <akash@xxxxxxxxxxxx>
---
.../bindings/phy/phy-rockchip-inno-usb2.txt | 1 +
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 44 +++++++++++++++++++
2 files changed, 45 insertions(+)
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml 2020-12-01 17:38:51.952047047 +0200
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml 2020-12-01 17:39:09.880064488 +0200
@@ -14,6 +14,7 @@
enum:
- rockchip,px30-usb2phy
- rockchip,rk3228-usb2phy
+ - rockchip,rk3308-usb2phy
- rockchip,rk3328-usb2phy
- rockchip,rk3366-usb2phy
- rockchip,rk3399-usb2phy
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1425,6 +1468,7 @@ static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
static const struct of_device_id rockchip_usb2phy_dt_match[] = {
{ .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
+ { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
--
2.17.1
Add the ehci/ochi usb node support for the RK3308 soc.
Signed-off-by: Akash Gajjar <akash@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 49 ++++++++++++++++++++++++
1 file changed, 49 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi 2020-12-01 17:42:28.328250544 +0200
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi 2020-12-01 17:45:19.464400997 +0200
@@ -586,6 +586,55 @@
status = "disabled";
};
+ usb2phy_grf: syscon@ff008000 {
+ compatible = "rockchip,rk3308-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xff008000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2-phy@100 {
+ compatible = "rockchip,rk3308-usb2phy";
+ reg = <0x100 0x10>;
+ clocks = <&cru SCLK_USBPHY_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&cru USB480M>;
+ assigned-clock-parents = <&u2phy>;
+ clock-output-names = "usb480m_phy";
+ status = "disabled";
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
+ };
+
+ usb_host_ehci: usb@ff440000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff440000 0x0 0x10000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb@ff450000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff450000 0x0 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
sdmmc: mmc@ff480000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff480000 0x0 0x4000>;

View file

@ -0,0 +1,23 @@
--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts 2020-12-01 17:53:08.008768652 +0200
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts 2020-12-01 17:54:29.728826515 +0200
@@ -335,3 +335,20 @@
pinctrl-0 = <&uart4_xfer &uart4_rts &uart4_cts>;
status = "okay";
};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+ };
+};
+
+&usb_host_ehci {
+ status = "okay";
+};
+
+&usb_host_ohci{
+ status = "okay";
+};

View file

@ -0,0 +1,74 @@
From a9a60c0bccd0c2b9d35594934eae5e25b4a00b53 Mon Sep 17 00:00:00 2001
From: tonymac32 <tonymckahan@gmail.com>
Date: Wed, 16 Dec 2020 01:32:03 -0500
Subject: [PATCH] rk3399-add-2ghz-opp-overlay
Signed-off-by: tonymac32 <tonymckahan@gmail.com>
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 1 +
.../rockchip/overlay/README.rockchip-overlays | 5 ++++
.../overlay/rockchip-rk3399-opp-2ghz.dts | 24 +++++++++++++++++++
3 files changed, 30 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3399-opp-2ghz.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 0fce5206d..9bc4942bd 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -3,6 +3,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-i2c7.dtbo \
rockchip-i2c8.dtbo \
rockchip-pcie-gen2.dtbo \
+ rockchip-rk3399-opp-2ghz.dtbo \
rockchip-spi-jedec-nor.dtbo \
rockchip-spi-spidev.dtbo \
rockchip-uart4.dtbo \
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 48ca48fc3..ce0b84e00 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -29,6 +29,11 @@ I2C8 pins (SCL, SDA): GPIO1-C5, GPIO1-C4
Enables PCIe Gen2 link speed on RK3399.
WARNING! Not officially supported by Rockchip!!!
+### rk3399-opp-2ghz
+
+Adds the 2GHz big and 1.5 GHz LITTLE opps for overclocking
+WARNING! Not officially supported by Rockchip!!!
+
### spi-jedec-nor
Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3399-opp-2ghz.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3399-opp-2ghz.dts
new file mode 100644
index 000000000..1d7584b60
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3399-opp-2ghz.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+/ {
+ compatible = "rockchip,rk3399";
+ fragment@0 {
+ target-path = "/opp-table0";
+ __overlay__ {
+ opp06 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1200000>;
+ };
+ };
+ };
+
+ fragment@1 {
+ target-path = "/opp-table1";
+ __overlay__ {
+ opp08 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <1300000>;
+ };
+ };
+ };
+};
--
Created with Armbian build tools https://github.com/armbian/build

View file

@ -1,26 +0,0 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
index d6f1095..30f353c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
@@ -33,6 +33,10 @@
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1125000>;
};
+ opp06 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1200000>;
+ };
};
cluster1_opp: opp-table1 {
@@ -72,6 +76,10 @@
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1200000>;
};
+ opp08 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <1300000>;
+ };
};
gpu_opp_table: opp-table2 {

View file

@ -0,0 +1,23 @@
--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts 2020-08-30 17:11:49.162572017 +0300
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts 2020-08-30 17:12:00.122550893 +0300
@@ -12,7 +12,7 @@
compatible = "radxa,rockpis", "rockchip,rk3308";
chosen {
- stdout-path = "serial0:1500000n8";
+ stdout-path = "serial2:1500000n8";
};
leds {
@@ -326,6 +326,10 @@
status = "okay";
};
+&uart2 {
+ status = "okay";
+};
+
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_xfer &uart4_rts &uart4_cts>;

View file

@ -0,0 +1,95 @@
This patch adds usb2-phy support for RK3308 SoCs and amend phy Documentation.
Signed-off-by: Akash Gajjar <akash@xxxxxxxxxxxx>
---
.../bindings/phy/phy-rockchip-inno-usb2.txt | 1 +
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 44 +++++++++++++++++++
2 files changed, 45 insertions(+)
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml 2020-12-01 17:38:51.952047047 +0200
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml 2020-12-01 17:39:09.880064488 +0200
@@ -14,6 +14,7 @@
enum:
- rockchip,px30-usb2phy
- rockchip,rk3228-usb2phy
+ - rockchip,rk3308-usb2phy
- rockchip,rk3328-usb2phy
- rockchip,rk3366-usb2phy
- rockchip,rk3399-usb2phy
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1425,6 +1468,7 @@ static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
static const struct of_device_id rockchip_usb2phy_dt_match[] = {
{ .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
+ { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
--
2.17.1
Add the ehci/ochi usb node support for the RK3308 soc.
Signed-off-by: Akash Gajjar <akash@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 49 ++++++++++++++++++++++++
1 file changed, 49 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi 2020-12-01 17:42:28.328250544 +0200
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi 2020-12-01 17:45:19.464400997 +0200
@@ -586,6 +586,55 @@
status = "disabled";
};
+ usb2phy_grf: syscon@ff008000 {
+ compatible = "rockchip,rk3308-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xff008000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2-phy@100 {
+ compatible = "rockchip,rk3308-usb2phy";
+ reg = <0x100 0x10>;
+ clocks = <&cru SCLK_USBPHY_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&cru USB480M>;
+ assigned-clock-parents = <&u2phy>;
+ clock-output-names = "usb480m_phy";
+ status = "disabled";
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
+ };
+
+ usb_host_ehci: usb@ff440000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff440000 0x0 0x10000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb@ff450000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff450000 0x0 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
sdmmc: mmc@ff480000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff480000 0x0 0x4000>;

View file

@ -0,0 +1,23 @@
--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts 2020-12-01 17:53:08.008768652 +0200
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts 2020-12-01 17:54:29.728826515 +0200
@@ -335,3 +335,20 @@
pinctrl-0 = <&uart4_xfer &uart4_rts &uart4_cts>;
status = "okay";
};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+ };
+};
+
+&usb_host_ehci {
+ status = "okay";
+};
+
+&usb_host_ohci{
+ status = "okay";
+};

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