From e6415aba29e3897f92a68f885c88784ea3a37f39 Mon Sep 17 00:00:00 2001 From: zador-blood-stained Date: Tue, 5 Sep 2017 23:27:06 +0300 Subject: [PATCH] Add dwmac-sun8i support to sunxi-next --- .../readd-dwmac-sun8i-DT-bindings.patch | 301 ++++++++++++++++++ .../readd-dwmac-sun8i-compatibles.patch | 31 ++ .../sunxi-next/readd-dwmac-sun8i-docs.patch | 103 ++++++ 3 files changed, 435 insertions(+) create mode 100644 patch/kernel/sunxi-next/readd-dwmac-sun8i-DT-bindings.patch create mode 100644 patch/kernel/sunxi-next/readd-dwmac-sun8i-compatibles.patch create mode 100644 patch/kernel/sunxi-next/readd-dwmac-sun8i-docs.patch diff --git a/patch/kernel/sunxi-next/readd-dwmac-sun8i-DT-bindings.patch b/patch/kernel/sunxi-next/readd-dwmac-sun8i-DT-bindings.patch new file mode 100644 index 000000000..e63499886 --- /dev/null +++ b/patch/kernel/sunxi-next/readd-dwmac-sun8i-DT-bindings.patch @@ -0,0 +1,301 @@ +From 9b5c2c835ee29d5dce19b1cffe42cc2b47b6ac01 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Sun, 3 Sep 2017 23:53:15 +0800 +Subject: [PATCH] Revert "arm: dts: sunxi: Revert EMAC changes" + +This reverts commit fe45174b72aead678da581bab9e9a37c9b26a070. + +Signed-off-by: Icenowy Zheng +--- + arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 ++++++++ + arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +++++++++++++++++ + arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++++++ + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++++++ + arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++++++ + arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +++++ + arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 +++++++ + arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++++++++++++++++++ + arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 ++++++++++++++ + arch/arm/boot/dts/sunxi-h3-h5.dtsi | 26 +++++++++++++++++++++++ + 10 files changed, 128 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +index b1502df7b5092..6713d0f2b3f4d 100644 +--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts ++++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +@@ -56,6 +56,8 @@ + + aliases { + serial0 = &uart0; ++ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ ++ ethernet0 = &emac; + ethernet1 = &xr819; + }; + +@@ -102,6 +104,13 @@ + status = "okay"; + }; + ++&emac { ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ + &mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>; +diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +index a337af1de3224..d756ff8251160 100644 +--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts ++++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +@@ -52,6 +52,7 @@ + compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; + + aliases { ++ ethernet0 = &emac; + serial0 = &uart0; + serial1 = &uart1; + }; +@@ -114,12 +115,30 @@ + status = "okay"; + }; + ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ + &ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; + }; + ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ }; ++}; ++ + &mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; +diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +index 8d2cc6e9a03fa..78f6c24952dd1 100644 +--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts ++++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +@@ -46,3 +46,10 @@ + model = "FriendlyARM NanoPi NEO"; + compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; + }; ++ ++&emac { ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +index 8ff71b1bb45b1..17cdeae19c6f0 100644 +--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts ++++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +@@ -54,6 +54,7 @@ + aliases { + serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ ++ ethernet0 = &emac; + ethernet1 = &rtl8189; + }; + +@@ -117,6 +118,13 @@ + status = "okay"; + }; + ++&emac { ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ + &ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; +diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +index 5fea430e0eb10..6880268e8b87b 100644 +--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts ++++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +@@ -52,6 +52,7 @@ + compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; + + aliases { ++ ethernet0 = &emac; + serial0 = &uart0; + }; + +@@ -97,6 +98,13 @@ + status = "okay"; + }; + ++&emac { ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ + &mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; +diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +index 8b93f5c781a70..a10281b455f50 100644 +--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts ++++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +@@ -53,6 +53,11 @@ + }; + }; + ++&emac { ++ /* LEDs changed to active high on the plus */ ++ /delete-property/ allwinner,leds-active-low; ++}; ++ + &mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; +diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +index 1a044b17d6c61..998b60f8d295e 100644 +--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts ++++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +@@ -52,6 +52,7 @@ + compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; + + aliases { ++ ethernet0 = &emac; + serial0 = &uart0; + }; + +@@ -113,6 +114,13 @@ + status = "okay"; + }; + ++&emac { ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ + &ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; +diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +index 828ae7a526d92..331ed683ac62c 100644 +--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts ++++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +@@ -47,6 +47,10 @@ + model = "Xunlong Orange Pi Plus / Plus 2"; + compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + ++ aliases { ++ ethernet0 = &emac; ++ }; ++ + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; +@@ -74,6 +78,24 @@ + status = "okay"; + }; + ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ }; ++}; ++ + &mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; +diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +index 97920b12a9445..80026f3caafc8 100644 +--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts ++++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +@@ -61,3 +61,19 @@ + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; + }; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; +diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +index 11240a8313c26..d38282b9e5d44 100644 +--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi ++++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +@@ -391,6 +391,32 @@ + clocks = <&osc24M>; + }; + ++ emac: ethernet@1c30000 { ++ compatible = "allwinner,sun8i-h3-emac"; ++ syscon = <&syscon>; ++ reg = <0x01c30000 0x10000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ resets = <&ccu RST_BUS_EMAC>; ++ reset-names = "stmmaceth"; ++ clocks = <&ccu CLK_BUS_EMAC>; ++ clock-names = "stmmaceth"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ mdio: mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ int_mii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ clocks = <&ccu CLK_BUS_EPHY>; ++ resets = <&ccu RST_BUS_EPHY>; ++ }; ++ }; ++ }; ++ + spi0: spi@01c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; diff --git a/patch/kernel/sunxi-next/readd-dwmac-sun8i-compatibles.patch b/patch/kernel/sunxi-next/readd-dwmac-sun8i-compatibles.patch new file mode 100644 index 000000000..7398b68d8 --- /dev/null +++ b/patch/kernel/sunxi-next/readd-dwmac-sun8i-compatibles.patch @@ -0,0 +1,31 @@ +From c2245f2ff7a5b41b9d5916097fbace8067e9ee65 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Sun, 3 Sep 2017 17:29:56 +0800 +Subject: [PATCH] Revert "net: stmmac: sun8i: Remove the compatibles" + +This reverts commit ad4540cc5aa3dccb8e1e12458d57f8c40fae5a1c. + +Signed-off-by: Icenowy Zheng +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +index 39c2122a4f269..fffd6d5fc907b 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +@@ -979,6 +979,14 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) + } + + static const struct of_device_id sun8i_dwmac_match[] = { ++ { .compatible = "allwinner,sun8i-h3-emac", ++ .data = &emac_variant_h3 }, ++ { .compatible = "allwinner,sun8i-v3s-emac", ++ .data = &emac_variant_v3s }, ++ { .compatible = "allwinner,sun8i-a83t-emac", ++ .data = &emac_variant_a83t }, ++ { .compatible = "allwinner,sun50i-a64-emac", ++ .data = &emac_variant_a64 }, + { } + }; + MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); diff --git a/patch/kernel/sunxi-next/readd-dwmac-sun8i-docs.patch b/patch/kernel/sunxi-next/readd-dwmac-sun8i-docs.patch new file mode 100644 index 000000000..674438983 --- /dev/null +++ b/patch/kernel/sunxi-next/readd-dwmac-sun8i-docs.patch @@ -0,0 +1,103 @@ +From 1328bc8f683f2e6496e1371ab42d994db8c2278e Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Sun, 3 Sep 2017 17:30:35 +0800 +Subject: [PATCH] Revert "dt-bindings: net: Revert sun8i dwmac binding" + +This reverts commit 8aa33ec2f4812d1ee96f4c02ba013f5b9c514343. + +Signed-off-by: Icenowy Zheng +--- + .../devicetree/bindings/net/dwmac-sun8i.txt | 84 ++++++++++++++++++++++ + 1 file changed, 84 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt + +diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +new file mode 100644 +index 0000000000000..725f3b1878861 +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +@@ -0,0 +1,84 @@ ++* Allwinner sun8i GMAC ethernet controller ++ ++This device is a platform glue layer for stmmac. ++Please see stmmac.txt for the other unchanged properties. ++ ++Required properties: ++- compatible: should be one of the following string: ++ "allwinner,sun8i-a83t-emac" ++ "allwinner,sun8i-h3-emac" ++ "allwinner,sun8i-v3s-emac" ++ "allwinner,sun50i-a64-emac" ++- reg: address and length of the register for the device. ++- interrupts: interrupt for the device ++- interrupt-names: should be "macirq" ++- clocks: A phandle to the reference clock for this device ++- clock-names: should be "stmmaceth" ++- resets: A phandle to the reset control for this device ++- reset-names: should be "stmmaceth" ++- phy-mode: See ethernet.txt ++- phy-handle: See ethernet.txt ++- #address-cells: shall be 1 ++- #size-cells: shall be 0 ++- syscon: A phandle to the syscon of the SoC with one of the following ++ compatible string: ++ - allwinner,sun8i-h3-system-controller ++ - allwinner,sun8i-v3s-system-controller ++ - allwinner,sun50i-a64-system-controller ++ - allwinner,sun8i-a83t-system-controller ++ ++Optional properties: ++- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0) ++- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0) ++Both delay properties need to be a multiple of 100. They control the delay for ++external PHY. ++ ++Optional properties for the following compatibles: ++ - "allwinner,sun8i-h3-emac", ++ - "allwinner,sun8i-v3s-emac": ++- allwinner,leds-active-low: EPHY LEDs are active low ++ ++Required child node of emac: ++- mdio bus node: should be named mdio ++ ++Required properties of the mdio node: ++- #address-cells: shall be 1 ++- #size-cells: shall be 0 ++ ++The device node referenced by "phy" or "phy-handle" should be a child node ++of the mdio node. See phy.txt for the generic PHY bindings. ++ ++Required properties of the phy node with the following compatibles: ++ - "allwinner,sun8i-h3-emac", ++ - "allwinner,sun8i-v3s-emac": ++- clocks: a phandle to the reference clock for the EPHY ++- resets: a phandle to the reset control for the EPHY ++ ++Example: ++ ++emac: ethernet@1c0b000 { ++ compatible = "allwinner,sun8i-h3-emac"; ++ syscon = <&syscon>; ++ reg = <0x01c0b000 0x104>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ resets = <&ccu RST_BUS_EMAC>; ++ reset-names = "stmmaceth"; ++ clocks = <&ccu CLK_BUS_EMAC>; ++ clock-names = "stmmaceth"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ mdio: mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ int_mii_phy: ethernet-phy@1 { ++ reg = <1>; ++ clocks = <&ccu CLK_BUS_EPHY>; ++ resets = <&ccu RST_BUS_EPHY>; ++ }; ++ }; ++};