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Add pcie reset to u-boot dev

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This commit is contained in:
count-doku 2020-01-02 12:38:26 +01:00
parent 32940dfe3b
commit ebbc0bffc7
2 changed files with 98 additions and 0 deletions
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49
patch/u-boot/u-boot-mvebu-dev/board_clearfogbase/do_pcie_reset_during_init.patch Normal file
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@ -0,0 +1,49 @@
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index f644547..f6e8ad5 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -10,6 +10,7 @@
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
+#include <asm-generic/gpio.h>
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
@@ -120,6 +121,36 @@ int board_init(void)
setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
mdelay(10);
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc pcie0_reset,
+ pcie1_reset;
+ int res;
+
+ /* Toogle PERST# on miniPCIe1 (CON2) and miniPCIe0 (CON3) */
+ res = dm_gpio_lookup_name("gpio@20_1", &pcie0_reset);
+ if (!res) {
+ res = dm_gpio_request(&pcie0_reset, "pcie0-reset");
+ if (!res)
+ dm_gpio_set_dir_flags(&pcie0_reset,GPIOD_IS_OUT |
+ GPIOD_ACTIVE_LOW);
+ }
+
+ res = dm_gpio_lookup_name("gpio@20_2", &pcie1_reset);
+ if (!res) {
+ res = dm_gpio_request(&pcie1_reset, "pcie1-reset");
+ if (!res)
+ dm_gpio_set_dir_flags(&pcie1_reset,GPIOD_IS_OUT |
+ GPIOD_ACTIVE_LOW);
+ }
+
+ dm_gpio_set_value(&pcie0_reset, 1);
+ dm_gpio_set_value(&pcie1_reset, 1);
+ mdelay(100);
+ dm_gpio_set_value(&pcie0_reset, 0);
+ dm_gpio_set_value(&pcie1_reset, 0);
+ mdelay(100);
+#endif
+
return 0;
}

49
patch/u-boot/u-boot-mvebu-dev/board_clearfogpro/do_pcie_reset_during_init.patch Normal file
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@ -0,0 +1,49 @@
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index f644547..f6e8ad5 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -10,6 +10,7 @@
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
+#include <asm-generic/gpio.h>
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
@@ -120,6 +121,36 @@ int board_init(void)
setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
mdelay(10);
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc pcie0_reset,
+ pcie1_reset;
+ int res;
+
+ /* Toogle PERST# on miniPCIe1 (CON2) and miniPCIe0 (CON3) */
+ res = dm_gpio_lookup_name("gpio@20_1", &pcie0_reset);
+ if (!res) {
+ res = dm_gpio_request(&pcie0_reset, "pcie0-reset");
+ if (!res)
+ dm_gpio_set_dir_flags(&pcie0_reset,GPIOD_IS_OUT |
+ GPIOD_ACTIVE_LOW);
+ }
+
+ res = dm_gpio_lookup_name("gpio@20_2", &pcie1_reset);
+ if (!res) {
+ res = dm_gpio_request(&pcie1_reset, "pcie1-reset");
+ if (!res)
+ dm_gpio_set_dir_flags(&pcie1_reset,GPIOD_IS_OUT |
+ GPIOD_ACTIVE_LOW);
+ }
+
+ dm_gpio_set_value(&pcie0_reset, 1);
+ dm_gpio_set_value(&pcie1_reset, 1);
+ mdelay(100);
+ dm_gpio_set_value(&pcie0_reset, 0);
+ dm_gpio_set_value(&pcie1_reset, 0);
+ mdelay(100);
+#endif
+
return 0;
}