GitHub-Mirror/build
2
0
Fork 0
mirror of https://github.com/Fishwaldo/build.git synced 2025-07-10 23:19:01 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

[RK3399] DEV kernel bumped to 4.19.RC4, adjusted kernel config, set u-boot to v2018.09, fix serial console output, default boot console is now HDMI, tested on FA Nanopc T4; default kernel bumped to 4.4.160 and re-add patch which address some issues

Browse source
This commit is contained in:
Igor Pecovnik 2018-10-10 17:25:28 +02:00
parent 28ac7a3683
commit f07ddda5fc
6 changed files with 3687 additions and 549 deletions
Download patch file Download diff file Expand all files Collapse all files

3101
patch/kernel/rk3399-default/04-patch-4.4.159-160.patch Normal file
View file

File diff suppressed because it is too large Load diff

98
patch/kernel/rk3399-default/friendly-arm-hangs-without.patch.disabled → patch/kernel/rk3399-default/friendly-arm-hangs-without.patch
View file

@ -1,5 +1,5 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
index 7cff5d61..d2e1334b 100644
index c2a6bedb..cdfcf0a5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
@@ -67,24 +67,6 @@
@ -27,36 +27,12 @@ index 7cff5d61..d2e1334b 100644
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
@@ -475,14 +457,8 @@
status = "okay";
};
-&uart4 {
- status = "okay";
-};
-
&vopb {
status = "okay";
- assigned-clocks = <&cru DCLK_VOP0_DIV>;
- assigned-clock-parents = <&cru PLL_VPLL>;
};
&vopb_mmu {
@@ -491,8 +467,6 @@
&vopl {
status = "okay";
- assigned-clocks = <&cru DCLK_VOP1_DIV>;
- assigned-clock-parents = <&cru PLL_CPLL>;
};
&vopl_mmu {
@@ -511,18 +485,13 @@
@@ -507,16 +489,12 @@
//allocator = <0>;
};
-&rga {
- status = "okay";
- status = "disabled";
-};
-
&display_subsystem {
@ -67,23 +43,13 @@ index 7cff5d61..d2e1334b 100644
- status = "okay";
+ status = "disabled";
force-hpd;
- /delete-property/ pinctrl-0;
/delete-property/ pinctrl-0;
ports {
port@1 {
@@ -535,45 +504,28 @@
};
};
-&edp_in_vopb {
+&edp_in_vopl {
status = "disabled";
};
@@ -537,29 +515,22 @@
&route_edp {
status = "okay";
- logo,mode = "center";
- connect = <&vopl_out_edp>;
};
&cdn_dp {
@ -93,14 +59,6 @@ index 7cff5d61..d2e1334b 100644
phys = <&tcphy0_dp>;
};
-&dp_in_vopl {
- status = "disabled";
-};
-
-&hdmi_in_vopl {
- status = "disabled";
-};
-
&hdmi {
- /* remove the hdmi_i2c_xfer */
- pinctrl-0 = <&hdmi_cec>;
@ -115,27 +73,12 @@ index 7cff5d61..d2e1334b 100644
-};
-
-&route_hdmi {
- status = "disabled";
- status = "okay";
- logo,mode = "center";
- connect = <&vopb_out_hdmi>;
};
&cif_isp0 {
@@ -848,13 +800,11 @@
compatible = "omnivision,ov13850-v4l2-i2c-subdev";
reg = <0x10>;
device_type = "v4l2-i2c-subdev";
-
clocks = <&cru SCLK_CIF_OUT>;
clock-names = "clk_cif_out";
pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep";
pinctrl-0 = <&cam0_default_pins>;
pinctrl-1 = <&cam0_sleep_pins>;
-
rockchip,pd-gpio = <&gpio2 28 GPIO_ACTIVE_LOW>;
rockchip,rst-gpio = <&gpio2 27 GPIO_ACTIVE_LOW>;
@@ -939,11 +889,6 @@
@@ -932,11 +903,6 @@
#sound-dai-cells = <0>;
};
@ -147,27 +90,24 @@ index 7cff5d61..d2e1334b 100644
&i2s2 {
#sound-dai-cells = <0>;
status = "okay";
@@ -968,9 +913,16 @@
@@ -961,9 +927,16 @@
};
&pcie0 {
- status = "okay";
- ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+ assigned-clock-rates = <100000000>;
+ status = "okay";
+ ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ max-link-speed = <2>;
+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+ assigned-clock-rates = <100000000>;
status = "okay";
ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ max-link-speed = <2>;
};
&pwm_bl {
@@ -1154,14 +1106,6 @@
@@ -1147,14 +1120,6 @@
};
&pinctrl {