From f48b01a9b02c4d84c965ea0ffa84eecc77908b27 Mon Sep 17 00:00:00 2001 From: Thomas McKahan Date: Sun, 25 Nov 2018 23:38:39 -0500 Subject: [PATCH] [ tinkerboard ] Bump Dev to 4.19, update patchset - Boots, Bluetooth, Reboot OK - Audio missing - spidev error (I think it's been here a while) - disabled both DWC2 patches, added 1008-rockchip-dwc2-usb-partial-power-down.patch from @Miouyouyou - Review/test, boards USB hotplug works on boot for Tinker - If other circumstances (if any) aren't addressed this way, obviously re-enable. @paolosabatino - Plugging in an old U3 USB stick made the scsi CD-ROM driver go insane. Not a modern problem. - Strange error on IRQ 56/57: [ 1.477928] WARNING: CPU: 1 PID: 1 at kernel/irq/manage.c:559 __enable_irq+0x54/0x7c [ 1.477935] Unbalanced enable for IRQ 57 [ 1.477940] Modules linked in: [ 1.477958] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.19.4-rockchip #25 [ 1.477965] Hardware name: Rockchip (Device Tree) [ 1.477995] [] (unwind_backtrace) from [] (show_stack+0x20/0x24) [ 1.478016] [] (show_stack) from [] (dump_stack+0x80/0x94) [ 1.478037] [] (dump_stack) from [] (__warn+0xf0/0x108) [ 1.478055] [] (__warn) from [] (warn_slowpath_fmt+0x58/0x74) [ 1.478075] [] (warn_slowpath_fmt) from [] (__enable_irq+0x54/0x7c) [ 1.478094] [] (__enable_irq) from [] (enable_irq+0x54/0xa0) [ 1.478113] [] (enable_irq) from [] (vop_unbind+0x24/0x54) [ 1.478130] [] (vop_unbind) from [] (component_unbind+0x40/0x78) [ 1.478145] [] (component_unbind) from [] (component_bind_all+0x1f0/0x238) [ 1.478158] [] (component_bind_all) from [] (rockchip_drm_bind+0xac/0x1e4) [ 1.478173] [] (rockchip_drm_bind) from [] (try_to_bring_up_master+0x15c/0x198) [ 1.478187] [] (try_to_bring_up_master) from [] (component_master_add_with_match+0xdc/0x110) [ 1.478201] [] (component_master_add_with_match) from [] (rockchip_drm_platform_probe+0x1f4/0x2ec) [ 1.478217] [] (rockchip_drm_platform_probe) from [] (platform_drv_probe+0x58/0xa8) [ 1.478234] [] (platform_drv_probe) from [] (really_probe+0x1e0/0x2cc) [ 1.478253] [] (really_probe) from [] (driver_probe_device+0x70/0x18c) [ 1.478270] [] (driver_probe_device) from [] (__driver_attach+0xe0/0xe4) [ 1.478286] [] (__driver_attach) from [] (bus_for_each_dev+0x84/0xc4) [ 1.478303] [] (bus_for_each_dev) from [] (driver_attach+0x2c/0x30) [ 1.478320] [] (driver_attach) from [] (bus_add_driver+0x19c/0x220) [ 1.478336] [] (bus_add_driver) from [] (driver_register+0x8c/0x124) [ 1.478352] [] (driver_register) from [] (__platform_driver_register+0x50/0x58) [ 1.478369] [] (__platform_driver_register) from [] (rockchip_drm_init+0x74/0x90) [ 1.478388] [] (rockchip_drm_init) from [] (do_one_initcall+0x64/0x288) [ 1.478410] [] (do_one_initcall) from [] (kernel_init_freeable+0x360/0x3fc) [ 1.478428] [] (kernel_init_freeable) from [] (kernel_init+0x18/0x120) [ 1.478442] [] (kernel_init) from [] (ret_from_fork+0x14/0x2c) [ 1.478450] Exception stack(0xee975fb0 to 0xee975ff8) [ 1.478461] 5fa0: 00000000 00000000 00000000 00000000 [ 1.478475] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 1.478486] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 1.478502] ---[ end trace 390e2ce79ed4d5fa ]--- [ 1.478567] ------------[ cut here ]------------ [ 1.478585] WARNING: CPU: 1 PID: 1 at kernel/irq/manage.c:559 __enable_irq+0x54/0x7c [ 1.478592] Unbalanced enable for IRQ 56 [ 1.478596] Modules linked in: [ 1.478614] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G W 4.19.4-rockchip #25 [ 1.478620] Hardware name: Rockchip (Device Tree) [ 1.478640] [] (unwind_backtrace) from [] (show_stack+0x20/0x24) [ 1.478656] [] (show_stack) from [] (dump_stack+0x80/0x94) [ 1.478674] [] (dump_stack) from [] (__warn+0xf0/0x108) [ 1.478691] [] (__warn) from [] (warn_slowpath_fmt+0x58/0x74) [ 1.478710] [] (warn_slowpath_fmt) from [] (__enable_irq+0x54/0x7c) [ 1.478728] [] (__enable_irq) from [] (enable_irq+0x54/0xa0) [ 1.478745] [] (enable_irq) from [] (vop_unbind+0x24/0x54) [ 1.478760] [] (vop_unbind) from [] (component_unbind+0x40/0x78) [ 1.478774] [] (component_unbind) from [] (component_bind_all+0x1f0/0x238) [ 1.478788] [] (component_bind_all) from [] (rockchip_drm_bind+0xac/0x1e4) [ 1.478802] [] (rockchip_drm_bind) from [] (try_to_bring_up_master+0x15c/0x198) [ 1.478817] [] (try_to_bring_up_master) from [] (component_master_add_with_match+0xdc/0x110) [ 1.478831] [] (component_master_add_with_match) from [] (rockchip_drm_platform_probe+0x1f4/0x2ec) [ 1.478845] [] (rockchip_drm_platform_probe) from [] (platform_drv_probe+0x58/0xa8) [ 1.478862] [] (platform_drv_probe) from [] (really_probe+0x1e0/0x2cc) [ 1.478880] [] (really_probe) from [] (driver_probe_device+0x70/0x18c) [ 1.478897] [] (driver_probe_device) from [] (__driver_attach+0xe0/0xe4) [ 1.478913] [] (__driver_attach) from [] (bus_for_each_dev+0x84/0xc4) [ 1.478929] [] (bus_for_each_dev) from [] (driver_attach+0x2c/0x30) [ 1.478946] [] (driver_attach) from [] (bus_add_driver+0x19c/0x220) [ 1.478962] [] (bus_add_driver) from [] (driver_register+0x8c/0x124) [ 1.478978] [] (driver_register) from [] (__platform_driver_register+0x50/0x58) [ 1.478993] [] (__platform_driver_register) from [] (rockchip_drm_init+0x74/0x90) [ 1.479010] [] (rockchip_drm_init) from [] (do_one_initcall+0x64/0x288) [ 1.479028] [] (do_one_initcall) from [] (kernel_init_freeable+0x360/0x3fc) [ 1.479045] [] (kernel_init_freeable) from [] (kernel_init+0x18/0x120) [ 1.479059] [] (kernel_init) from [] (ret_from_fork+0x14/0x2c) [ 1.479066] Exception stack(0xee975fb0 to 0xee975ff8) [ 1.479077] 5fa0: 00000000 00000000 00000000 00000000 [ 1.479090] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 1.479101] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 1.479109] ---[ end trace 390e2ce79ed4d5fb ]--- --- config/sources/rockchip.conf | 2 +- ...rockchip-dwc2-usb-partial-power-down.patch | 44 ++ ...88-support-for-dedicating-NPLL-to-a-.patch | 228 ++++++++++ ...chip-better-clock-selection-logic-an.patch | 424 ++++++++++++++++++ .../1100-media-Add-JPEG_RAW-format.patch | 63 +++ ...ontrols-for-JPEG-quantization-tables.patch | 153 +++++++ ...288-Adding-cells-addresses-and-size.patch} | 0 ...288-Adding-missing-EDP-power-domain.patch} | 0 ...k3288-Adding-missing-VOPB-registers.patch} | 0 ...rk3288-Fixed-the-SPDIF-node-address.patch} | 0 ...8-tinker-Enabling-SDIO-Wireless-and.patch} | 0 ...inker-Setup-the-Bluetooth-UART-pins.patch} | 0 ...8-tinker-Improving-the-CPU-max-volt.patch} | 0 ...8-tinker-Setting-up-the-SD-regulato.patch} | 0 ...8-tinker-Defined-the-I2C-interfaces.patch} | 0 ...8-tinker-Defining-the-SPI-interface.patch} | 0 ...nker-Add-the-MIPI-DSI-node.patch.disabled} | 0 ...88-tinker-Defining-SDMMC-properties.patch} | 0 ...DTSI-rk3288-Define-the-VPU-services.patch} | 0 ...8-miqi-Enable-the-Video-encoding-MM.patch} | 0 ...nker-Enable-the-Video-encoding-MMU-.patch} | 0 ...irefly-Enable-the-Video-encoding-MM.patch} | 0 ...eyron-Enable-the-Video-encoding-MMU.patch} | 0 ...3288-Renamed-the-VPU-services-clocks.patch | 39 ++ ...rk3288-Set-the-VPU-MMU-power-domains.patch | 56 +++ ...027-ARM-DTS-rk3288-miqi-enable-sound.patch | 46 -- ...-service-as-defined-in-the-V4L2-driv.patch | 43 ++ ...king-up-in-rk3288-platform.patch.disabled} | 0 ... general-aufs4.18-20180820.patch.disabled} | 0 ...r_down-on-rockchip-devices.patch.disabled} | 0 ...rtl8188eu-kconfig-makefile.patch.disabled} | 0 ... => wifi-2002-02-rtl8188eu.patch.disabled} | 0 32 files changed, 1051 insertions(+), 47 deletions(-) create mode 100644 patch/kernel/rockchip-dev/1008-rockchip-dwc2-usb-partial-power-down.patch create mode 100644 patch/kernel/rockchip-dev/1009-drivers-clk-rk3288-support-for-dedicating-NPLL-to-a-.patch create mode 100644 patch/kernel/rockchip-dev/1010-drm-dw_hdmi-rockchip-better-clock-selection-logic-an.patch create mode 100644 patch/kernel/rockchip-dev/1100-media-Add-JPEG_RAW-format.patch create mode 100644 patch/kernel/rockchip-dev/1101-media-Add-controls-for-JPEG-quantization-tables.patch rename patch/kernel/rockchip-dev/{2010-ARM-DTSI-rk3288-Adding-cells-addresses-and-size.patch => 2009-ARM-DTSI-rk3288-Adding-cells-addresses-and-size.patch} (100%) rename patch/kernel/rockchip-dev/{2011-ARM-DTSI-rk3288-Adding-missing-EDP-power-domain.patch => 2010-ARM-DTSI-rk3288-Adding-missing-EDP-power-domain.patch} (100%) rename patch/kernel/rockchip-dev/{2013-ARM-DTSI-rk3288-Adding-missing-VOPB-registers.patch => 2011-ARM-DTSI-rk3288-Adding-missing-VOPB-registers.patch} (100%) rename patch/kernel/rockchip-dev/{2014-ARM-DTSI-rk3288-Fixed-the-SPDIF-node-address.patch => 2012-ARM-DTSI-rk3288-Fixed-the-SPDIF-node-address.patch} (100%) rename patch/kernel/rockchip-dev/{2015-ARM-DTS-rk3288-tinker-Enabling-SDIO-Wireless-and.patch => 2013-ARM-DTS-rk3288-tinker-Enabling-SDIO-Wireless-and.patch} (100%) rename patch/kernel/rockchip-dev/{3001-dts-tinker-bluetooth.patch => 2014-ARM-DTS-rk3288-tinker-Setup-the-Bluetooth-UART-pins.patch} (100%) rename patch/kernel/rockchip-dev/{2016-ARM-DTS-rk3288-tinker-Improving-the-CPU-max-volt.patch => 2015-ARM-DTS-rk3288-tinker-Improving-the-CPU-max-volt.patch} (100%) rename patch/kernel/rockchip-dev/{2017-ARM-DTS-rk3288-tinker-Setting-up-the-SD-regulato.patch => 2016-ARM-DTS-rk3288-tinker-Setting-up-the-SD-regulato.patch} (100%) rename patch/kernel/rockchip-dev/{2018-ARM-DTS-rk3288-tinker-Defined-the-I2C-interfaces.patch => 2017-ARM-DTS-rk3288-tinker-Defined-the-I2C-interfaces.patch} (100%) rename patch/kernel/rockchip-dev/{2020-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch => 2018-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch} (100%) rename patch/kernel/rockchip-dev/{2019-ARM-DTS-rk3288-tinker-Add-the-MIPI-DSI-node.patch => 2019-ARM-DTS-rk3288-tinker-Add-the-MIPI-DSI-node.patch.disabled} (100%) rename patch/kernel/rockchip-dev/{2021-ARM-DTS-rk3288-tinker-Defining-SDMMC-properties.patch => 2019-ARM-DTS-rk3288-tinker-Defining-SDMMC-properties.patch} (100%) rename patch/kernel/rockchip-dev/{2022-ARM-DTSI-rk3288-Define-the-VPU-services.patch => 2020-ARM-DTSI-rk3288-Define-the-VPU-services.patch} (100%) rename patch/kernel/rockchip-dev/{2023-ARM-DTS-rk3288-miqi-Enable-the-Video-encoding-MM.patch => 2021-ARM-DTS-rk3288-miqi-Enable-the-Video-encoding-MM.patch} (100%) rename patch/kernel/rockchip-dev/{2024-ARM-DTS-rk3288-tinker-Enable-the-Video-encoding-MMU-.patch => 2022-ARM-DTS-rk3288-tinker-Enable-the-Video-encoding-MMU-.patch} (100%) rename patch/kernel/rockchip-dev/{2025-ARM-DTSI-rk3288-firefly-Enable-the-Video-encoding-MM.patch => 2023-ARM-DTSI-rk3288-firefly-Enable-the-Video-encoding-MM.patch} (100%) rename patch/kernel/rockchip-dev/{2026-ARM-DTSI-rk3288-veyron-Enable-the-Video-encoding-MMU.patch => 2024-ARM-DTSI-rk3288-veyron-Enable-the-Video-encoding-MMU.patch} (100%) create mode 100644 patch/kernel/rockchip-dev/2025-ARM-DTSI-rk3288-Renamed-the-VPU-services-clocks.patch create mode 100644 patch/kernel/rockchip-dev/2026-ARM-DTSI-rk3288-Set-the-VPU-MMU-power-domains.patch delete mode 100644 patch/kernel/rockchip-dev/2027-ARM-DTS-rk3288-miqi-enable-sound.patch create mode 100644 patch/kernel/rockchip-dev/2027-ARM-dtsi-The-VPU-service-as-defined-in-the-V4L2-driv.patch rename patch/kernel/rockchip-dev/{assert-phy-reset-when-waking-up-in-rk3288-platform.patch => assert-phy-reset-when-waking-up-in-rk3288-platform.patch.disabled} (100%) rename patch/kernel/rockchip-dev/{general-aufs4.18-20180820.patch => general-aufs4.18-20180820.patch.disabled} (100%) rename patch/kernel/rockchip-dev/{usb-dwc2-disable-power_down-on-rockchip-devices.patch => usb-dwc2-disable-power_down-on-rockchip-devices.patch.disabled} (100%) rename patch/kernel/rockchip-dev/{wifi-2001-01-rtl8188eu-kconfig-makefile.patch => wifi-2001-01-rtl8188eu-kconfig-makefile.patch.disabled} (100%) rename patch/kernel/rockchip-dev/{wifi-2002-02-rtl8188eu.patch => wifi-2002-02-rtl8188eu.patch.disabled} (100%) diff --git a/config/sources/rockchip.conf b/config/sources/rockchip.conf index 3989fa9a5..e762d9f71 100644 --- a/config/sources/rockchip.conf +++ b/config/sources/rockchip.conf @@ -37,7 +37,7 @@ case $BRANCH in dev) KERNELSOURCE=$MAINLINE_KERNEL_SOURCE - KERNELBRANCH='branch:linux-4.18.y' + KERNELBRANCH='branch:linux-4.19.y' KERNELDIR=$MAINLINE_KERNEL_DIR KERNEL_USE_GCC='> 7.0' diff --git a/patch/kernel/rockchip-dev/1008-rockchip-dwc2-usb-partial-power-down.patch b/patch/kernel/rockchip-dev/1008-rockchip-dwc2-usb-partial-power-down.patch new file mode 100644 index 000000000..0f0f85573 --- /dev/null +++ b/patch/kernel/rockchip-dev/1008-rockchip-dwc2-usb-partial-power-down.patch @@ -0,0 +1,44 @@ +From 04fbf78e4e569bf872f1ffcb0a6f9b89569dc913 Mon Sep 17 00:00:00 2001 +From: Hal Emmerich +Date: Thu, 19 Jul 2018 21:48:08 -0500 +Subject: [PATCH] usb: dwc2: disable power_down on rockchip devices + + The bug would let the usb controller enter partial power down, + which was formally known as hibernate, upon boot if nothing was plugged + in to the port. Partial power down couldn't be exited properly, so any + usb devices plugged in after boot would not be usable. + + Before the name change, params.hibernation was false by default, so + _dwc2_hcd_suspend() would skip entering hibernation. With the + rename, _dwc2_hcd_suspend() was changed to use params.power_down + to decide whether or not to enter partial power down. + + Since params.power_down is non-zero by default, it needs to be set + to 0 for rockchip devices to restore functionality. + + This bug was reported in the linux-usb thread: + REGRESSION: usb: dwc2: USB device not seen after boot + + The commit that caused this regression is: + 6d23ee9caa6790aea047f9aca7f3c03cb8d96eb6 + +Signed-off-by: Hal Emmerich +--- + drivers/usb/dwc2/params.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c +index f03e418..492607a 100644 +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -82,6 +82,7 @@ static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) + p->host_perio_tx_fifo_size = 256; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << + GAHBCFG_HBSTLEN_SHIFT; ++ p->power_down = 0; + } + + static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) +-- +2.11.0 + diff --git a/patch/kernel/rockchip-dev/1009-drivers-clk-rk3288-support-for-dedicating-NPLL-to-a-.patch b/patch/kernel/rockchip-dev/1009-drivers-clk-rk3288-support-for-dedicating-NPLL-to-a-.patch new file mode 100644 index 000000000..11aa9525b --- /dev/null +++ b/patch/kernel/rockchip-dev/1009-drivers-clk-rk3288-support-for-dedicating-NPLL-to-a-.patch @@ -0,0 +1,228 @@ +From bc16cd0aa3cdaaff27b9bf2d3282ccfff81d8784 Mon Sep 17 00:00:00 2001 +From: "Miouyouyou (Myy)" +Date: Sat, 29 Sep 2018 02:56:32 +0200 +Subject: [PATCH 5/6] drivers: clk-rk3288: support for dedicating NPLL to a VOP + +This patch is taken from Urja Rannikko ( @urjaman ) patchset here : +https://github.com/urjaman/arch-c201/blob/master/linux-c201/0020-RK3288-HDMI-clock-hacks-combined.patch +https://www.spinics.net/lists/arm-kernel/msg673156.html + +I'm not really sure what this does exactly. It basically sets the +parent clock of the newly added clocks, if the newly added property +"rockchip,npll-for-vop" is detected and set. + +I have no clear idea how HDMI Neuronal PLL (and PLL in general) work, +so I cannot comment on what it's doing and if it's a good idea in +general. + +The only thing I know from this patchset is that it works and have +resolved some purple line issue at the left of my HDMI screen, when +connected to MiQi or Tinkerboard devices. + +Signed-off-by: Miouyouyou (Myy) +--- + drivers/clk/rockchip/clk-rk3288.c | 98 ++++++++++++++++++++++++++++++++------- + drivers/clk/rockchip/clk.h | 3 ++ + 2 files changed, 85 insertions(+), 16 deletions(-) + +diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c +index fd2058f7d..b5b56169d 100644 +--- a/drivers/clk/rockchip/clk-rk3288.c ++++ b/drivers/clk/rockchip/clk-rk3288.c +@@ -83,22 +83,43 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { + RK3066_PLL_RATE( 768000000, 1, 64, 2), + RK3066_PLL_RATE( 742500000, 8, 495, 2), + RK3066_PLL_RATE( 696000000, 1, 58, 2), ++ RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1), + RK3066_PLL_RATE( 600000000, 1, 50, 2), + RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), + RK3066_PLL_RATE( 552000000, 1, 46, 2), + RK3066_PLL_RATE( 504000000, 1, 84, 4), + RK3066_PLL_RATE( 500000000, 3, 125, 2), + RK3066_PLL_RATE( 456000000, 1, 76, 4), ++ RK3066_PLL_RATE( 428000000, 1, 107, 6), + RK3066_PLL_RATE( 408000000, 1, 68, 4), + RK3066_PLL_RATE( 400000000, 3, 100, 2), ++ RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1), + RK3066_PLL_RATE( 384000000, 2, 128, 4), + RK3066_PLL_RATE( 360000000, 1, 60, 4), ++ RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1), ++ RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1), + RK3066_PLL_RATE( 312000000, 1, 52, 4), +- RK3066_PLL_RATE( 300000000, 1, 50, 4), +- RK3066_PLL_RATE( 297000000, 2, 198, 8), ++ RK3066_PLL_RATE_NB( 308000000, 1, 154, 12, 1), ++ RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1), ++ RK3066_PLL_RATE( 300000000, 1, 75, 6), ++ RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1), ++ RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1), ++ RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1), ++ RK3066_PLL_RATE( 273600000, 1, 114, 10), ++ RK3066_PLL_RATE_NB( 273000000, 1, 182, 16, 1), ++ RK3066_PLL_RATE_NB( 270000000, 1, 180, 16, 1), ++ RK3066_PLL_RATE_NB( 266250000, 2, 355, 16, 1), ++ RK3066_PLL_RATE_NB( 256500000, 1, 171, 16, 1), + RK3066_PLL_RATE( 252000000, 1, 84, 8), +- RK3066_PLL_RATE( 216000000, 1, 72, 8), +- RK3066_PLL_RATE( 148500000, 2, 99, 8), ++ RK3066_PLL_RATE_NB( 250500000, 1, 167, 16, 1), ++ RK3066_PLL_RATE_NB( 243428571, 1, 142, 14, 1), ++ RK3066_PLL_RATE( 238000000, 1, 119, 12), ++ RK3066_PLL_RATE_NB( 219750000, 2, 293, 16, 1), ++ RK3066_PLL_RATE_NB( 216000000, 1, 144, 16, 1), ++ RK3066_PLL_RATE_NB( 213000000, 1, 142, 16, 1), ++ RK3066_PLL_RATE( 195428571, 1, 114, 14), ++ RK3066_PLL_RATE( 160000000, 1, 80, 12), ++ RK3066_PLL_RATE( 157500000, 1, 105, 16), + RK3066_PLL_RATE( 126000000, 1, 84, 16), + RK3066_PLL_RATE( 48000000, 1, 64, 32), + { /* sentinel */ }, +@@ -194,10 +215,14 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; + PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; + + PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; +-PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; +-PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; ++PNAME_ED(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; ++ ++PNAME_ED(mux_pll_src_cgn_pll_nonvop_p) = { "cpll", "gpll", "npll" }; ++PNAME_ED(mux_pll_src_cgn_pll_vop0_p) = { "cpll", "gpll", "npll" }; ++PNAME_ED(mux_pll_src_cgn_pll_vop1_p) = { "cpll", "gpll", "npll" }; ++ + PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usbphy480m_src" }; +-PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" }; ++PNAME_ED(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" }; + + PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" }; + PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" }; +@@ -443,24 +468,24 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { + RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3288_CLKGATE_CON(3), 4, GFLAGS), + +- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0, ++ COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cgn_pll_vop0_p, 0, + RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS, + RK3288_CLKGATE_CON(3), 1, GFLAGS), +- COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0, ++ COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cgn_pll_vop1_p, 0, + RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS, + RK3288_CLKGATE_CON(3), 3, GFLAGS), + + COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0, + RK3288_CLKSEL_CON(28), 15, 1, MFLAGS, + RK3288_CLKGATE_CON(3), 12, GFLAGS), +- COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0, ++ COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cgn_pll_nonvop_p, 0, + RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3288_CLKGATE_CON(3), 13, GFLAGS), + +- COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0, ++ COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cgn_pll_nonvop_p, 0, + RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3288_CLKGATE_CON(3), 14, GFLAGS), +- COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0, ++ COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cgn_pll_nonvop_p, 0, + RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3288_CLKGATE_CON(3), 15, GFLAGS), + +@@ -469,16 +494,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { + GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0, + RK3288_CLKGATE_CON(5), 11, GFLAGS), + +- COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0, ++ COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cgn_pll_nonvop_p, 0, + RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3288_CLKGATE_CON(13), 13, GFLAGS), + DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0, + RK3288_CLKSEL_CON(40), 12, 2, DFLAGS), + +- COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0, ++ COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cgn_pll_nonvop_p, 0, + RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3288_CLKGATE_CON(13), 14, GFLAGS), +- COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0, ++ COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cgn_pll_nonvop_p, 0, + RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3288_CLKGATE_CON(13), 15, GFLAGS), + +@@ -552,7 +577,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { + COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0, + RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3288_CLKGATE_CON(4), 11, GFLAGS), +- COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0, ++ COMPOSITE(0, "sclk_tsp", mux_pll_src_cgn_pll_nonvop_p, 0, + RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3288_CLKGATE_CON(4), 10, GFLAGS), + +@@ -912,6 +937,7 @@ static void __init rk3288_clk_init(struct device_node *np) + { + struct rockchip_clk_provider *ctx; + struct clk *clk; ++ s32 npll_vop = -1; + + rk3288_cru_base = of_iomap(np, 0); + if (!rk3288_cru_base) { +@@ -919,6 +945,46 @@ static void __init rk3288_clk_init(struct device_node *np) + return; + } + ++ if (!of_property_read_s32(np, "rockchip,npll-for-vop", &npll_vop)) { ++ if ((npll_vop < -1) || (npll_vop > 1)) { ++ pr_warn("%s: invalid VOP to dedicate NPLL to: %d\n", ++ __func__, npll_vop); ++ } else if (npll_vop >= 0) { ++ unsigned int vop_clk_id; ++ const char ** npll_names; ++ const char ** non_npll_names; ++ int i; ++ ++ /* Firstly, not-VOP needs to not use npll */ ++ mux_pll_src_npll_cpll_gpll_p[0] = "dummy_npll"; ++ mux_pll_src_cgn_pll_nonvop_p[2] = "dummy_npll"; ++ mux_pll_src_cpll_gll_usb_npll_p[3] = "dummy_npll"; ++ ++ /* Then the npll VOP needs to only use npll, and the other one not use npll. */ ++ if (npll_vop) { ++ vop_clk_id = DCLK_VOP1; ++ npll_names = mux_pll_src_cgn_pll_vop1_p; ++ non_npll_names = mux_pll_src_cgn_pll_vop0_p; ++ } else { ++ vop_clk_id = DCLK_VOP0; ++ npll_names = mux_pll_src_cgn_pll_vop0_p; ++ non_npll_names = mux_pll_src_cgn_pll_vop1_p; ++ } ++ npll_names[0] = "dummy_cpll"; ++ npll_names[1] = "dummy_gpll"; ++ non_npll_names[2] = "dummy_npll"; ++ ++ /* Lastly the npll-dedicated-VOP needs to be able to control npll. */ ++ for (i = 0; i < ARRAY_SIZE(rk3288_clk_branches); i++) { ++ if (rk3288_clk_branches[i].id == vop_clk_id) { ++ rk3288_clk_branches[i].flags |= CLK_SET_RATE_PARENT; ++ break; ++ } ++ } ++ pr_debug("%s: npll dedicated for VOP %d\n", __func__, npll_vop); ++ } ++ } ++ + ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); +diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h +index 6b53fff4c..dbda9d281 100644 +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -382,6 +382,9 @@ struct clk *rockchip_clk_register_muxgrf(const char *name, + + #define PNAME(x) static const char *const x[] __initconst + ++/* For when you want to be able to modify the pointers. */ ++#define PNAME_ED(x) static const char * x[] __initdata ++ + enum rockchip_clk_branch_type { + branch_composite, + branch_mux, +-- +2.16.4 + diff --git a/patch/kernel/rockchip-dev/1010-drm-dw_hdmi-rockchip-better-clock-selection-logic-an.patch b/patch/kernel/rockchip-dev/1010-drm-dw_hdmi-rockchip-better-clock-selection-logic-an.patch new file mode 100644 index 000000000..ea9b62231 --- /dev/null +++ b/patch/kernel/rockchip-dev/1010-drm-dw_hdmi-rockchip-better-clock-selection-logic-an.patch @@ -0,0 +1,424 @@ +From 6c86916e81fa18394d9b57b4af44f9948e100e96 Mon Sep 17 00:00:00 2001 +From: "Miouyouyou (Myy)" +Date: Sat, 29 Sep 2018 03:02:10 +0200 +Subject: [PATCH 6/6] drm: dw_hdmi-rockchip: better clock selection logic and + dts-based rate list + +This patch is taken from Urja Rannikko ( @urjaman ) patchset here : +https://github.com/urjaman/arch-c201/blob/master/linux-c201/0020-RK3288-HDMI-clock-hacks-combined.patch +https://www.spinics.net/lists/arm-kernel/msg673156.html + +The original description was : + This contains traces of the following commits from the ChromeOS 3.14 + tree, which improve RF/EMI performance and detach the clock selection + logic from the HDMI PHY configurations, plus support for configuring + the allowed clock rates via device tree as they are dependent on + PLL configuration and maybe even the PCB layout and other hardware things, + eg. interference to wifi or such (EMI). + + Rates that were allowed previous to this patch are added as the fallback + list if no dts configuration exists. + + CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Adjust rockchip_mpll_cfg for 146.25 + CHROMIUM: drm: rockchip/dw_hdmi-rockchip: expand the informal mpll config + CHROMIUM: drm: rockchip/dw_hdmi-rockchip: add slop to more tables + CHROMIUM: drm: rockchip/dw_hdmi-rockchip: redo rockchip hdmi to allow slop + CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Use auto-generated tables + CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Fixup the clock to be what we expect + CHROMIUM: drm/rockchip: hdmi: adjust cklvl & txlvl for RF/EMI + CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Set cur_ctr to 0 always + CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Decrease slop + +https://www.spinics.net/lists/arm-kernel/msg673163.html + +This is the patch that takes into account the new property +"rockchip,hdmi-rates-hz" that allows the definition of the HDMI +frequencies in the DTS file. +This also change a lot of HDMI frequencies definition, so that +*will* require some extensive testing. + +Still, if it works fine, this should make tinkering the HDMI +frequencies easier, in case you have a very special HDMI screen. + +Signed-off-by: Miouyouyou (Myy) +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 269 ++++++++++++++++++---------- + 1 file changed, 175 insertions(+), 94 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index 11309a2a4..740b0aeea 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -49,122 +49,141 @@ struct rockchip_hdmi { + struct clk *vpll_clk; + struct clk *grf_clk; + struct dw_hdmi *hdmi; ++ u32* rates; ++ u32 rates_cnt; + }; + ++#define CLK_SLOP(clk) ((clk) / 1000) ++#define CLK_PLUS_SLOP(clk) ((clk) + CLK_SLOP(clk)) ++ + #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x) + ++/* These were the rates allowed by the driver before rates list in device tree, ++ * so keep them around as a fallback */ ++static const u32 dw_hdmi_fallback_rates[] = { ++ 27000000, ++ 36000000, ++ 40000000, ++ 54000000, ++ 65000000, ++ 66000000, ++ 74250000, ++ 83500000, ++ 106500000, ++ 108000000, ++ 146250000, ++ 148500000 ++}; ++ + static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { + { +- 27000000, { +- { 0x00b3, 0x0000}, +- { 0x2153, 0x0000}, +- { 0x40f3, 0x0000} ++ 30666000, { ++ { 0x00b3, 0x0000 }, ++ { 0x2153, 0x0000 }, ++ { 0x40f3, 0x0000 }, ++ }, ++ }, { ++ 36800000, { ++ { 0x00b3, 0x0000 }, ++ { 0x2153, 0x0000 }, ++ { 0x40a2, 0x0001 }, + }, +- }, { +- 36000000, { +- { 0x00b3, 0x0000}, +- { 0x2153, 0x0000}, +- { 0x40f3, 0x0000} ++ }, { ++ 46000000, { ++ { 0x00b3, 0x0000 }, ++ { 0x2142, 0x0001 }, ++ { 0x40a2, 0x0001 }, + }, +- }, { +- 40000000, { +- { 0x00b3, 0x0000}, +- { 0x2153, 0x0000}, +- { 0x40f3, 0x0000} ++ }, { ++ 61333000, { ++ { 0x0072, 0x0001 }, ++ { 0x2142, 0x0001 }, ++ { 0x40a2, 0x0001 }, + }, +- }, { +- 54000000, { +- { 0x0072, 0x0001}, +- { 0x2142, 0x0001}, +- { 0x40a2, 0x0001}, ++ }, { ++ 73600000, { ++ { 0x0072, 0x0001 }, ++ { 0x2142, 0x0001 }, ++ { 0x4061, 0x0002 }, + }, +- }, { +- 65000000, { +- { 0x0072, 0x0001}, +- { 0x2142, 0x0001}, +- { 0x40a2, 0x0001}, ++ }, { ++ 92000000, { ++ { 0x0072, 0x0001 }, ++ { 0x2145, 0x0002 }, ++ { 0x4061, 0x0002 }, + }, +- }, { +- 66000000, { +- { 0x013e, 0x0003}, +- { 0x217e, 0x0002}, +- { 0x4061, 0x0002} ++ }, { ++ 122666000, { ++ { 0x0051, 0x0002 }, ++ { 0x2145, 0x0002 }, ++ { 0x4061, 0x0002 }, + }, +- }, { +- 74250000, { +- { 0x0072, 0x0001}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} ++ }, { ++ 147200000, { ++ { 0x0051, 0x0002 }, ++ { 0x2145, 0x0002 }, ++ { 0x4064, 0x0003 }, + }, +- }, { +- 83500000, { +- { 0x0072, 0x0001}, ++ }, { ++ 184000000, { ++ { 0x0051, 0x0002 }, ++ { 0x214c, 0x0003 }, ++ { 0x4064, 0x0003 }, + }, +- }, { +- 108000000, { +- { 0x0051, 0x0002}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} ++ }, { ++ 226666000, { ++ { 0x0040, 0x0003 }, ++ { 0x214c, 0x0003 }, ++ { 0x4064, 0x0003 }, + }, +- }, { +- 106500000, { +- { 0x0051, 0x0002}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} ++ }, { ++ 272000000, { ++ { 0x0040, 0x0003 }, ++ { 0x214c, 0x0003 }, ++ { 0x5a64, 0x0003 }, + }, +- }, { +- 146250000, { +- { 0x0051, 0x0002}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} ++ }, { ++ 340000000, { ++ { 0x0040, 0x0003 }, ++ { 0x3b4c, 0x0003 }, ++ { 0x5a64, 0x0003 }, + }, +- }, { +- 148500000, { +- { 0x0051, 0x0003}, +- { 0x214c, 0x0003}, +- { 0x4064, 0x0003} ++ }, { ++ 600000000, { ++ { 0x1a40, 0x0003 }, ++ { 0x3b4c, 0x0003 }, ++ { 0x5a64, 0x0003 }, + }, +- }, { ++ }, { + ~0UL, { +- { 0x00a0, 0x000a }, +- { 0x2001, 0x000f }, +- { 0x4002, 0x000f }, ++ { 0x0000, 0x0000 }, ++ { 0x0000, 0x0000 }, ++ { 0x0000, 0x0000 }, + }, + } + }; + + static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { +- /* pixelclk bpp8 bpp10 bpp12 */ ++ /* pixelclk bpp8 bpp10 bpp12 */ + { +- 40000000, { 0x0018, 0x0018, 0x0018 }, +- }, { +- 65000000, { 0x0028, 0x0028, 0x0028 }, +- }, { +- 66000000, { 0x0038, 0x0038, 0x0038 }, +- }, { +- 74250000, { 0x0028, 0x0038, 0x0038 }, +- }, { +- 83500000, { 0x0028, 0x0038, 0x0038 }, +- }, { +- 146250000, { 0x0038, 0x0038, 0x0038 }, +- }, { +- 148500000, { 0x0000, 0x0038, 0x0038 }, +- }, { +- ~0UL, { 0x0000, 0x0000, 0x0000}, +- } ++ 600000000, { 0x0000, 0x0000, 0x0000 }, ++ }, { ++ ~0UL, { 0x0000, 0x0000, 0x0000 }, ++ }, + }; + + static const struct dw_hdmi_phy_config rockchip_phy_config[] = { + /*pixelclk symbol term vlev*/ +- { 74250000, 0x8009, 0x0004, 0x0272}, +- { 148500000, 0x802b, 0x0004, 0x028d}, +- { 297000000, 0x8039, 0x0005, 0x028d}, +- { ~0UL, 0x0000, 0x0000, 0x0000} ++ { CLK_PLUS_SLOP(74250000), 0x8009, 0x0004, 0x0272}, ++ { CLK_PLUS_SLOP(165000000), 0x802b, 0x0004, 0x0209}, ++ { CLK_PLUS_SLOP(297000000), 0x8039, 0x0005, 0x028d}, ++ { ~0UL, 0x0000, 0x0000, 0x0000} + }; + + static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) + { + struct device_node *np = hdmi->dev->of_node; ++ int rates_cnt; + + hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); + if (IS_ERR(hdmi->regmap)) { +@@ -192,26 +211,55 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) + return PTR_ERR(hdmi->grf_clk); + } + ++ if ((rates_cnt = of_property_count_u32_elems(np, "rockchip,hdmi-rates-hz")) > 0) { ++ int rv; ++ u32 *rates = devm_kmalloc_array(hdmi->dev, rates_cnt, sizeof(u32), GFP_KERNEL); ++ if (!rates) ++ return -ENOMEM; ++ rv = of_property_read_u32_array(np, "rockchip,hdmi-rates-hz", rates, rates_cnt); ++ if (rv) ++ return rv; ++ hdmi->rates = rates; ++ hdmi->rates_cnt = rates_cnt; ++ } else { ++ rates_cnt = ARRAY_SIZE(dw_hdmi_fallback_rates); ++ hdmi->rates = devm_kmalloc_array(hdmi->dev, rates_cnt, sizeof(u32), GFP_KERNEL); ++ if (!hdmi->rates) ++ return -ENOMEM; ++ memcpy(hdmi->rates, dw_hdmi_fallback_rates, rates_cnt * sizeof(u32)); ++ hdmi->rates_cnt = rates_cnt; ++ } ++ ++ + return 0; + } + + static enum drm_mode_status +-dw_hdmi_rockchip_mode_valid(struct drm_connector *connector, ++dw_hdmi_rockchip_encoder_mode_valid(struct drm_encoder *encoder, + const struct drm_display_mode *mode) + { +- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; ++ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + int pclk = mode->clock * 1000; +- bool valid = false; ++ int num_rates = hdmi->rates_cnt; + int i; + +- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { +- if (pclk == mpll_cfg[i].mpixelclock) { +- valid = true; +- break; +- } ++ /* ++ * Pixel clocks we support are always < 2GHz and so fit in an ++ * int. We should make sure source rate does too so we don't get ++ * overflow when we multiply by 1000. ++ */ ++ if (mode->clock > INT_MAX / 1000) ++ return MODE_BAD; ++ ++ for (i = 0; i < num_rates; i++) { ++ int slop = CLK_SLOP(pclk); ++ ++ if ((pclk >= hdmi->rates[i] - slop) && ++ (pclk <= hdmi->rates[i] + slop)) ++ return MODE_OK; + } + +- return (valid) ? MODE_OK : MODE_BAD; ++ return MODE_BAD; + } + + static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = { +@@ -227,7 +275,39 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) + { +- return true; ++ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); ++ int pclk = adj_mode->clock * 1000; ++ int best_diff = INT_MAX; ++ int best_clock = 0; ++ int slop; ++ int i; ++ ++ /* Pick the best clock */ ++ for (i = 0; i < hdmi->rates_cnt; i++) { ++ int diff = hdmi->rates[i] - pclk; ++ ++ if (diff < 0) ++ diff = -diff; ++ if (diff < best_diff) { ++ best_diff = diff; ++ best_clock = hdmi->rates[i]; ++ ++ /* Bail early if we're exact */ ++ if (best_diff == 0) ++ return true; ++ } ++ } ++ ++ /* Double check that it's OK */ ++ slop = CLK_SLOP(pclk); ++ if ((pclk >= best_clock - slop) && (pclk <= best_clock + slop)) { ++ adj_mode->clock = DIV_ROUND_UP(best_clock, 1000); ++ return true; ++ } ++ ++ /* Shoudn't be here; we should have said rate wasn't valid */ ++ dev_warn(hdmi->dev, "tried to set invalid rate %d\n", adj_mode->clock); ++ return false; + } + + static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, +@@ -280,6 +360,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, + } + + static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { ++ .mode_valid = dw_hdmi_rockchip_encoder_mode_valid, + .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, + .mode_set = dw_hdmi_rockchip_encoder_mode_set, + .enable = dw_hdmi_rockchip_encoder_enable, +@@ -294,7 +375,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = { + }; + + static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { +- .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, +@@ -308,7 +388,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { + }; + + static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { +- .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, +@@ -387,6 +466,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + */ + if (IS_ERR(hdmi->hdmi)) { + ret = PTR_ERR(hdmi->hdmi); ++ devm_kfree(hdmi->dev, hdmi->rates); + drm_encoder_cleanup(encoder); + clk_disable_unprepare(hdmi->vpll_clk); + } +@@ -399,6 +479,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, + { + struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); + ++ devm_kfree(hdmi->dev, hdmi->rates); + dw_hdmi_unbind(hdmi->hdmi); + clk_disable_unprepare(hdmi->vpll_clk); + } +-- +2.16.4 + diff --git a/patch/kernel/rockchip-dev/1100-media-Add-JPEG_RAW-format.patch b/patch/kernel/rockchip-dev/1100-media-Add-JPEG_RAW-format.patch new file mode 100644 index 000000000..e29ad9085 --- /dev/null +++ b/patch/kernel/rockchip-dev/1100-media-Add-JPEG_RAW-format.patch @@ -0,0 +1,63 @@ +From 1680a655127a62e74cbcfb84782e04a9c55dcf81 Mon Sep 17 00:00:00 2001 +From: Shunqian Zheng +Date: Wed, 5 Sep 2018 19:00:09 -0300 +Subject: [PATCH 3/6] media: Add JPEG_RAW format + +Add V4L2_PIX_FMT_JPEG_RAW format that does not contain +JPEG header in the output frame. + +Signed-off-by: Shunqian Zheng +Signed-off-by: Ezequiel Garcia +--- + Documentation/media/uapi/v4l/pixfmt-compressed.rst | 9 +++++++++ + drivers/media/v4l2-core/v4l2-ioctl.c | 1 + + include/uapi/linux/videodev2.h | 1 + + 3 files changed, 11 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +index d382e7a5..4dffe400 100644 +--- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst ++++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +@@ -23,6 +23,15 @@ Compressed Formats + - 'JPEG' + - TBD. See also :ref:`VIDIOC_G_JPEGCOMP `, + :ref:`VIDIOC_S_JPEGCOMP `. ++ * .. _V4L2-PIX-FMT-JPEG-RAW: ++ ++ - ``V4L2_PIX_FMT_JPEG_RAW`` ++ - 'Raw JPEG' ++ - Raw JPEG bitstream, containing a compressed payload. This format ++ contains an image scan, i.e. without any metadata or headers. ++ The user is expected to set the needed metadata such as ++ quantization and entropy encoding tables, via ``V4L2_CID_JPEG`` ++ controls, see :ref:`jpeg-control-id`. + * .. _V4L2-PIX-FMT-MPEG: + + - ``V4L2_PIX_FMT_MPEG`` +diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c +index 54afc9c7..0dcd95f4 100644 +--- a/drivers/media/v4l2-core/v4l2-ioctl.c ++++ b/drivers/media/v4l2-core/v4l2-ioctl.c +@@ -1301,6 +1301,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) + /* Max description length mask: descr = "0123456789012345678901234567890" */ + case V4L2_PIX_FMT_MJPEG: descr = "Motion-JPEG"; break; + case V4L2_PIX_FMT_JPEG: descr = "JFIF JPEG"; break; ++ case V4L2_PIX_FMT_JPEG_RAW: descr = "Raw JPEG"; break; + case V4L2_PIX_FMT_DV: descr = "1394"; break; + case V4L2_PIX_FMT_MPEG: descr = "MPEG-1/2/4"; break; + case V4L2_PIX_FMT_H264: descr = "H.264"; break; +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index 5d1a3685..f271048c 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -627,6 +627,7 @@ struct v4l2_pix_format { + /* compressed formats */ + #define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG */ + #define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG */ ++#define V4L2_PIX_FMT_JPEG_RAW v4l2_fourcc('J', 'P', 'G', 'R') /* JFIF JPEG RAW without headers */ + #define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') /* 1394 */ + #define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 Multiplexed */ + #define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */ +-- +2.16.4 + diff --git a/patch/kernel/rockchip-dev/1101-media-Add-controls-for-JPEG-quantization-tables.patch b/patch/kernel/rockchip-dev/1101-media-Add-controls-for-JPEG-quantization-tables.patch new file mode 100644 index 000000000..7838c9b13 --- /dev/null +++ b/patch/kernel/rockchip-dev/1101-media-Add-controls-for-JPEG-quantization-tables.patch @@ -0,0 +1,153 @@ +From 82da876c36ccc7791d5b20e7ee8b50379f7b19aa Mon Sep 17 00:00:00 2001 +From: Shunqian Zheng +Date: Wed, 5 Sep 2018 19:00:10 -0300 +Subject: [PATCH 4/6] media: Add controls for JPEG quantization tables + +Add V4L2_CID_JPEG_QUANTIZATION compound control to allow userspace +configure the JPEG quantization tables. + +Signed-off-by: Shunqian Zheng +Signed-off-by: Ezequiel Garcia +--- + Documentation/media/uapi/v4l/extended-controls.rst | 31 ++++++++++++++++++++++ + Documentation/media/videodev2.h.rst.exceptions | 1 + + drivers/media/v4l2-core/v4l2-ctrls.c | 10 +++++++ + include/uapi/linux/v4l2-controls.h | 12 +++++++++ + include/uapi/linux/videodev2.h | 1 + + 5 files changed, 55 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/extended-controls.rst b/Documentation/media/uapi/v4l/extended-controls.rst +index 9f7312bf..1335d27d 100644 +--- a/Documentation/media/uapi/v4l/extended-controls.rst ++++ b/Documentation/media/uapi/v4l/extended-controls.rst +@@ -3354,7 +3354,38 @@ JPEG Control IDs + Specify which JPEG markers are included in compressed stream. This + control is valid only for encoders. + ++.. _jpeg-quant-tables-control: + ++``V4L2_CID_JPEG_QUANTIZATION (struct)`` ++ Specifies the luma and chroma quantization matrices for encoding ++ or decoding a V4L2_PIX_FMT_JPEG_RAW format buffer. The :ref:`itu-t81` ++ specification allows 8-bit quantization coefficients for ++ baseline profile images, and 8-bit or 16-bit for extended profile ++ images. Supporting or not 16-bit precision coefficients is driver-specific. ++ Coefficients must be set in JPEG zigzag scan order. ++ ++ ++.. c:type:: struct v4l2_ctrl_jpeg_quantization ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_jpeg_quantization ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``precision`` ++ - Specifies the coefficient precision. User shall set 0 ++ for 8-bit, and 1 for 16-bit. ++ ++ * - __u16 ++ - ``luma_quantization_matrix[64]`` ++ - Sets the luma quantization table. ++ ++ * - __u16 ++ - ``chroma_quantization_matrix[64]`` ++ - Sets the chroma quantization table. + + .. flat-table:: + :header-rows: 0 +diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions +index ca9f0edc..a0a38e92 100644 +--- a/Documentation/media/videodev2.h.rst.exceptions ++++ b/Documentation/media/videodev2.h.rst.exceptions +@@ -129,6 +129,7 @@ replace symbol V4L2_CTRL_TYPE_STRING :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_U16 :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_U32 :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_U8 :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_JPEG_QUANTIZATION :c:type:`v4l2_ctrl_type` + + # V4L2 capability defines + replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index 599c1cbf..305bd7a9 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -999,6 +999,7 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_JPEG_RESTART_INTERVAL: return "Restart Interval"; + case V4L2_CID_JPEG_COMPRESSION_QUALITY: return "Compression Quality"; + case V4L2_CID_JPEG_ACTIVE_MARKER: return "Active Markers"; ++ case V4L2_CID_JPEG_QUANTIZATION: return "JPEG Quantization Tables"; + + /* Image source controls */ + /* Keep the order of the 'case's the same as in v4l2-controls.h! */ +@@ -1286,6 +1287,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_DETECT_MD_REGION_GRID: + *type = V4L2_CTRL_TYPE_U8; + break; ++ case V4L2_CID_JPEG_QUANTIZATION: ++ *type = V4L2_CTRL_TYPE_JPEG_QUANTIZATION; ++ break; + case V4L2_CID_DETECT_MD_THRESHOLD_GRID: + *type = V4L2_CTRL_TYPE_U16; + break; +@@ -1612,6 +1616,9 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, + return -ERANGE; + return 0; + ++ case V4L2_CTRL_TYPE_JPEG_QUANTIZATION: ++ return 0; ++ + default: + return -EINVAL; + } +@@ -2133,6 +2140,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, + case V4L2_CTRL_TYPE_U32: + elem_size = sizeof(u32); + break; ++ case V4L2_CTRL_TYPE_JPEG_QUANTIZATION: ++ elem_size = sizeof(struct v4l2_ctrl_jpeg_quantization); ++ break; + default: + if (type < V4L2_CTRL_COMPOUND_TYPES) + elem_size = sizeof(s32); +diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h +index e4ee10ee..856b3325 100644 +--- a/include/uapi/linux/v4l2-controls.h ++++ b/include/uapi/linux/v4l2-controls.h +@@ -987,6 +987,18 @@ enum v4l2_jpeg_chroma_subsampling { + #define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) + #define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) + ++#define V4L2_CID_JPEG_QUANTIZATION (V4L2_CID_JPEG_CLASS_BASE + 5) ++struct v4l2_ctrl_jpeg_quantization { ++ /* ITU-T.81 specifies two quantization coefficient precisions: ++ * 8-bit for baseline profile, ++ * 8-bit or 16-bit for extended profile. ++ * ++ * User shall set "precision" to 0 for 8-bit and 1 for 16-bit. ++ */ ++ __u8 precision; ++ __u16 luma_quantization_matrix[64]; ++ __u16 chroma_quantization_matrix[64]; ++}; + + /* Image source controls */ + #define V4L2_CID_IMAGE_SOURCE_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900) +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index f271048c..e998d074 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -1630,6 +1630,7 @@ enum v4l2_ctrl_type { + V4L2_CTRL_TYPE_U8 = 0x0100, + V4L2_CTRL_TYPE_U16 = 0x0101, + V4L2_CTRL_TYPE_U32 = 0x0102, ++ V4L2_CTRL_TYPE_JPEG_QUANTIZATION = 0x0103, + }; + + /* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ +-- +2.16.4 + diff --git a/patch/kernel/rockchip-dev/2010-ARM-DTSI-rk3288-Adding-cells-addresses-and-size.patch b/patch/kernel/rockchip-dev/2009-ARM-DTSI-rk3288-Adding-cells-addresses-and-size.patch similarity index 100% rename from patch/kernel/rockchip-dev/2010-ARM-DTSI-rk3288-Adding-cells-addresses-and-size.patch rename to patch/kernel/rockchip-dev/2009-ARM-DTSI-rk3288-Adding-cells-addresses-and-size.patch diff --git a/patch/kernel/rockchip-dev/2011-ARM-DTSI-rk3288-Adding-missing-EDP-power-domain.patch b/patch/kernel/rockchip-dev/2010-ARM-DTSI-rk3288-Adding-missing-EDP-power-domain.patch similarity index 100% rename from patch/kernel/rockchip-dev/2011-ARM-DTSI-rk3288-Adding-missing-EDP-power-domain.patch rename to patch/kernel/rockchip-dev/2010-ARM-DTSI-rk3288-Adding-missing-EDP-power-domain.patch diff --git a/patch/kernel/rockchip-dev/2013-ARM-DTSI-rk3288-Adding-missing-VOPB-registers.patch b/patch/kernel/rockchip-dev/2011-ARM-DTSI-rk3288-Adding-missing-VOPB-registers.patch similarity index 100% rename from patch/kernel/rockchip-dev/2013-ARM-DTSI-rk3288-Adding-missing-VOPB-registers.patch rename to patch/kernel/rockchip-dev/2011-ARM-DTSI-rk3288-Adding-missing-VOPB-registers.patch diff --git a/patch/kernel/rockchip-dev/2014-ARM-DTSI-rk3288-Fixed-the-SPDIF-node-address.patch b/patch/kernel/rockchip-dev/2012-ARM-DTSI-rk3288-Fixed-the-SPDIF-node-address.patch similarity index 100% rename from patch/kernel/rockchip-dev/2014-ARM-DTSI-rk3288-Fixed-the-SPDIF-node-address.patch rename to patch/kernel/rockchip-dev/2012-ARM-DTSI-rk3288-Fixed-the-SPDIF-node-address.patch diff --git a/patch/kernel/rockchip-dev/2015-ARM-DTS-rk3288-tinker-Enabling-SDIO-Wireless-and.patch b/patch/kernel/rockchip-dev/2013-ARM-DTS-rk3288-tinker-Enabling-SDIO-Wireless-and.patch similarity index 100% rename from patch/kernel/rockchip-dev/2015-ARM-DTS-rk3288-tinker-Enabling-SDIO-Wireless-and.patch rename to patch/kernel/rockchip-dev/2013-ARM-DTS-rk3288-tinker-Enabling-SDIO-Wireless-and.patch diff --git a/patch/kernel/rockchip-dev/3001-dts-tinker-bluetooth.patch b/patch/kernel/rockchip-dev/2014-ARM-DTS-rk3288-tinker-Setup-the-Bluetooth-UART-pins.patch similarity index 100% rename from patch/kernel/rockchip-dev/3001-dts-tinker-bluetooth.patch rename to patch/kernel/rockchip-dev/2014-ARM-DTS-rk3288-tinker-Setup-the-Bluetooth-UART-pins.patch diff --git a/patch/kernel/rockchip-dev/2016-ARM-DTS-rk3288-tinker-Improving-the-CPU-max-volt.patch b/patch/kernel/rockchip-dev/2015-ARM-DTS-rk3288-tinker-Improving-the-CPU-max-volt.patch similarity index 100% rename from patch/kernel/rockchip-dev/2016-ARM-DTS-rk3288-tinker-Improving-the-CPU-max-volt.patch rename to patch/kernel/rockchip-dev/2015-ARM-DTS-rk3288-tinker-Improving-the-CPU-max-volt.patch diff --git a/patch/kernel/rockchip-dev/2017-ARM-DTS-rk3288-tinker-Setting-up-the-SD-regulato.patch b/patch/kernel/rockchip-dev/2016-ARM-DTS-rk3288-tinker-Setting-up-the-SD-regulato.patch similarity index 100% rename from patch/kernel/rockchip-dev/2017-ARM-DTS-rk3288-tinker-Setting-up-the-SD-regulato.patch rename to patch/kernel/rockchip-dev/2016-ARM-DTS-rk3288-tinker-Setting-up-the-SD-regulato.patch diff --git a/patch/kernel/rockchip-dev/2018-ARM-DTS-rk3288-tinker-Defined-the-I2C-interfaces.patch b/patch/kernel/rockchip-dev/2017-ARM-DTS-rk3288-tinker-Defined-the-I2C-interfaces.patch similarity index 100% rename from patch/kernel/rockchip-dev/2018-ARM-DTS-rk3288-tinker-Defined-the-I2C-interfaces.patch rename to patch/kernel/rockchip-dev/2017-ARM-DTS-rk3288-tinker-Defined-the-I2C-interfaces.patch diff --git a/patch/kernel/rockchip-dev/2020-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch b/patch/kernel/rockchip-dev/2018-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch similarity index 100% rename from patch/kernel/rockchip-dev/2020-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch rename to patch/kernel/rockchip-dev/2018-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch diff --git a/patch/kernel/rockchip-dev/2019-ARM-DTS-rk3288-tinker-Add-the-MIPI-DSI-node.patch b/patch/kernel/rockchip-dev/2019-ARM-DTS-rk3288-tinker-Add-the-MIPI-DSI-node.patch.disabled similarity index 100% rename from patch/kernel/rockchip-dev/2019-ARM-DTS-rk3288-tinker-Add-the-MIPI-DSI-node.patch rename to patch/kernel/rockchip-dev/2019-ARM-DTS-rk3288-tinker-Add-the-MIPI-DSI-node.patch.disabled diff --git a/patch/kernel/rockchip-dev/2021-ARM-DTS-rk3288-tinker-Defining-SDMMC-properties.patch b/patch/kernel/rockchip-dev/2019-ARM-DTS-rk3288-tinker-Defining-SDMMC-properties.patch similarity index 100% rename from patch/kernel/rockchip-dev/2021-ARM-DTS-rk3288-tinker-Defining-SDMMC-properties.patch rename to patch/kernel/rockchip-dev/2019-ARM-DTS-rk3288-tinker-Defining-SDMMC-properties.patch diff --git a/patch/kernel/rockchip-dev/2022-ARM-DTSI-rk3288-Define-the-VPU-services.patch b/patch/kernel/rockchip-dev/2020-ARM-DTSI-rk3288-Define-the-VPU-services.patch similarity index 100% rename from patch/kernel/rockchip-dev/2022-ARM-DTSI-rk3288-Define-the-VPU-services.patch rename to patch/kernel/rockchip-dev/2020-ARM-DTSI-rk3288-Define-the-VPU-services.patch diff --git a/patch/kernel/rockchip-dev/2023-ARM-DTS-rk3288-miqi-Enable-the-Video-encoding-MM.patch b/patch/kernel/rockchip-dev/2021-ARM-DTS-rk3288-miqi-Enable-the-Video-encoding-MM.patch similarity index 100% rename from patch/kernel/rockchip-dev/2023-ARM-DTS-rk3288-miqi-Enable-the-Video-encoding-MM.patch rename to patch/kernel/rockchip-dev/2021-ARM-DTS-rk3288-miqi-Enable-the-Video-encoding-MM.patch diff --git a/patch/kernel/rockchip-dev/2024-ARM-DTS-rk3288-tinker-Enable-the-Video-encoding-MMU-.patch b/patch/kernel/rockchip-dev/2022-ARM-DTS-rk3288-tinker-Enable-the-Video-encoding-MMU-.patch similarity index 100% rename from patch/kernel/rockchip-dev/2024-ARM-DTS-rk3288-tinker-Enable-the-Video-encoding-MMU-.patch rename to patch/kernel/rockchip-dev/2022-ARM-DTS-rk3288-tinker-Enable-the-Video-encoding-MMU-.patch diff --git a/patch/kernel/rockchip-dev/2025-ARM-DTSI-rk3288-firefly-Enable-the-Video-encoding-MM.patch b/patch/kernel/rockchip-dev/2023-ARM-DTSI-rk3288-firefly-Enable-the-Video-encoding-MM.patch similarity index 100% rename from patch/kernel/rockchip-dev/2025-ARM-DTSI-rk3288-firefly-Enable-the-Video-encoding-MM.patch rename to patch/kernel/rockchip-dev/2023-ARM-DTSI-rk3288-firefly-Enable-the-Video-encoding-MM.patch diff --git a/patch/kernel/rockchip-dev/2026-ARM-DTSI-rk3288-veyron-Enable-the-Video-encoding-MMU.patch b/patch/kernel/rockchip-dev/2024-ARM-DTSI-rk3288-veyron-Enable-the-Video-encoding-MMU.patch similarity index 100% rename from patch/kernel/rockchip-dev/2026-ARM-DTSI-rk3288-veyron-Enable-the-Video-encoding-MMU.patch rename to patch/kernel/rockchip-dev/2024-ARM-DTSI-rk3288-veyron-Enable-the-Video-encoding-MMU.patch diff --git a/patch/kernel/rockchip-dev/2025-ARM-DTSI-rk3288-Renamed-the-VPU-services-clocks.patch b/patch/kernel/rockchip-dev/2025-ARM-DTSI-rk3288-Renamed-the-VPU-services-clocks.patch new file mode 100644 index 000000000..9dd8fbfae --- /dev/null +++ b/patch/kernel/rockchip-dev/2025-ARM-DTSI-rk3288-Renamed-the-VPU-services-clocks.patch @@ -0,0 +1,39 @@ +From 29ef524e8890bbfd24602a61e14234259df92349 Mon Sep 17 00:00:00 2001 +From: "Miouyouyou (Myy)" +Date: Mon, 25 Jun 2018 17:05:37 +0200 +Subject: [PATCH 25/26] ARM: DTSI: rk3288: Renamed the VPU services clocks + +In order to conform to the naming scheme used in the whole DTSI. + +Signed-off-by: Miouyouyou (Myy) +--- + arch/arm/boot/dts/rk3288.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 796609e3..45ec4e89 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1242,7 +1242,7 @@ + ; + interrupt-names = "irq_enc", "irq_dec"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; +- clock-names = "aclk_vcodec", "hclk_vcodec"; ++ clock-names = "aclk", "iface"; + power-domains = <&power RK3288_PD_VIDEO>; + rockchip,grf = <&grf>; + resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>; +@@ -1277,8 +1277,8 @@ + <&cru SCLK_HEVC_CORE>, + <&cru SCLK_HEVC_CABAC>; + clock-names = +- "aclk_vcodec", +- "hclk_vcodec", ++ "aclk", ++ "iface", + "clk_core", + "clk_cabac"; + /* +-- +2.16.4 + diff --git a/patch/kernel/rockchip-dev/2026-ARM-DTSI-rk3288-Set-the-VPU-MMU-power-domains.patch b/patch/kernel/rockchip-dev/2026-ARM-DTSI-rk3288-Set-the-VPU-MMU-power-domains.patch new file mode 100644 index 000000000..ad8eac7dc --- /dev/null +++ b/patch/kernel/rockchip-dev/2026-ARM-DTSI-rk3288-Set-the-VPU-MMU-power-domains.patch @@ -0,0 +1,56 @@ +From d3d3fe433d9038dcd1a98f4d6711c0777ed06703 Mon Sep 17 00:00:00 2001 +From: "Miouyouyou (Myy)" +Date: Mon, 25 Jun 2018 17:08:32 +0200 +Subject: [PATCH 26/26] ARM: DTSI: rk3288: Set the VPU MMU power domains + +Without that, the auto-activation of the VPU hardware IOMMU fails +when enabling the hardware, before the "probe" phase of its device +driver. + +Basically, when loading a "of_platform" device driver targeting +the VPU devices, you'll get these errors without this patch : + +[12753.996950] rk_iommu ff9c0440.iommu: Error during raw reset. MMU_DTE_ADDR is not functioning +[12754.007483] rk_iommu ff9c0440.iommu: Disable stall request timed out, status: 0xffffffff +[12754.026652] rk_iommu ff9c0440.iommu: Disable paging request timed out, status: 0xffffffff +[12754.045975] rk_iommu ff9c0440.iommu: Disable stall request timed out, status: 0xffffffff + +When using this patch, the errors disappear. + +This seems to be due to the IOMMU device sharing the same power domain +than the device. +When loading an "of_platform" driver, the kernel logic seems to try +enabling the associated IOMMU device before letting the driver handles +anything with the actual VPU hardware. +It appears that setting the power domain of the VPU IOMMU nodes let the +IOMMU driver enable the IOMMU shared power domain, and make the IOMMU +device useable. + +Signed-off-by: Miouyouyou (Myy) +--- + arch/arm/boot/dts/rk3288.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 45ec4e89..46e1b8e2 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1230,6 +1230,7 @@ + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; ++ power-domains = <&power RK3288_PD_VIDEO>; + #iommu-cells = <0>; + status = "disabled"; + }; +@@ -1262,6 +1263,7 @@ + interrupt-names = "hevc_mmu"; + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; + clock-names = "aclk", "iface"; ++ power-domains = <&power RK3288_PD_HEVC>; + #iommu-cells = <0>; + status = "disabled"; + }; +-- +2.16.4 + diff --git a/patch/kernel/rockchip-dev/2027-ARM-DTS-rk3288-miqi-enable-sound.patch b/patch/kernel/rockchip-dev/2027-ARM-DTS-rk3288-miqi-enable-sound.patch deleted file mode 100644 index a6b07ddd4..000000000 --- a/patch/kernel/rockchip-dev/2027-ARM-DTS-rk3288-miqi-enable-sound.patch +++ /dev/null @@ -1,46 +0,0 @@ -From b5d066aba887ebd5963da588d0229d356f1ae79a Mon Sep 17 00:00:00 2001 -From: Sebastian -Date: Wed, 14 Mar 2018 12:49:45 +0200 -Subject: [PATCH] MIQI-DTS-enable-sound-node - ---- - .../2027-ARM-DTS-rk3288-miqi-enable-sound.patch | 30 ++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - create mode 100644 patch/kernel/rockchip-dev/2027-ARM-DTS-rk3288-miqi-enable-sound.patch - -diff --git a/patch/kernel/rockchip-dev/2027-ARM-DTS-rk3288-miqi-enable-sound.patch b/patch/kernel/rockchip-dev/2027-ARM-DTS-rk3288-miqi-enable-sound.patch -new file mode 100644 -index 000000000..3f728abdd ---- /dev/null -+++ b/patch/kernel/rockchip-dev/2027-ARM-DTS-rk3288-miqi-enable-sound.patch -@@ -0,0 +1,30 @@ -+diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts -+index dd785c7..5824ee7 100644 -+--- a/arch/arm/boot/dts/rk3288-miqi.dts -++++ b/arch/arm/boot/dts/rk3288-miqi.dts -+@@ -57,6 +57,23 @@ -+ reg = <0x0 0x0 0x0 0x80000000>; -+ }; -+ -++ sound { -++ compatible = "simple-audio-card"; -++ simple-audio-card,format = "i2s"; -++ simple-audio-card,name = "DW-HDMI"; -++ simple-audio-card,mclk-fs = <512>; -++ -++ simple-audio-card,dai-link@0 { /* I2S - S/PDIF */ -++ format = "i2s"; -++ cpu { -++ sound-dai = <&i2s>; -++ }; -++ codec { -++ sound-dai = <&hdmi>; -++ }; -++ }; -++ }; -++ -+ ext_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+-- -+2.14.1 diff --git a/patch/kernel/rockchip-dev/2027-ARM-dtsi-The-VPU-service-as-defined-in-the-V4L2-driv.patch b/patch/kernel/rockchip-dev/2027-ARM-dtsi-The-VPU-service-as-defined-in-the-V4L2-driv.patch new file mode 100644 index 000000000..9e0374ed2 --- /dev/null +++ b/patch/kernel/rockchip-dev/2027-ARM-dtsi-The-VPU-service-as-defined-in-the-V4L2-driv.patch @@ -0,0 +1,43 @@ +From 7f8607ba9a20f8ddb5c24559d9b875af762d4717 Mon Sep 17 00:00:00 2001 +From: "Miouyouyou (Myy)" +Date: Tue, 11 Sep 2018 02:55:55 +0200 +Subject: [PATCH] ARM: dtsi: The VPU service as defined in the V4L2 driver + +Let's try the V4L2 road. +They've got a lot of things ready, like an entire H264 +movie with the V4L2 data of *every frame*. + +That might help in this endless endeavour. + +Signed-off-by: Miouyouyou (Myy) +--- + arch/arm/boot/dts/rk3288.dtsi | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 72c36af6..d23c7fa5 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1246,7 +1246,18 @@ + clock-names = "aclk", "iface"; + power-domains = <&power RK3288_PD_VIDEO>; + #iommu-cells = <0>; +- status = "disabled"; ++ }; ++ ++ vpu: video-codec@ff9a0000 { ++ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; ++ clock-names = "aclk", "hclk"; ++ compatible = "rockchip,rk3288-vpu"; ++ interrupts = , ++ ; ++ interrupt-names = "vepu", "vdpu"; ++ iommus = <&vpu_mmu>; ++ power-domains = <&power RK3288_PD_VIDEO>; ++ reg = <0x0 0xff9a0000 0x0 0x800>; + }; + + hevc_mmu: iommu@ff9c0440 { +-- +2.16.4 + diff --git a/patch/kernel/rockchip-dev/assert-phy-reset-when-waking-up-in-rk3288-platform.patch b/patch/kernel/rockchip-dev/assert-phy-reset-when-waking-up-in-rk3288-platform.patch.disabled similarity index 100% rename from patch/kernel/rockchip-dev/assert-phy-reset-when-waking-up-in-rk3288-platform.patch rename to patch/kernel/rockchip-dev/assert-phy-reset-when-waking-up-in-rk3288-platform.patch.disabled diff --git a/patch/kernel/rockchip-dev/general-aufs4.18-20180820.patch b/patch/kernel/rockchip-dev/general-aufs4.18-20180820.patch.disabled similarity index 100% rename from patch/kernel/rockchip-dev/general-aufs4.18-20180820.patch rename to patch/kernel/rockchip-dev/general-aufs4.18-20180820.patch.disabled diff --git a/patch/kernel/rockchip-dev/usb-dwc2-disable-power_down-on-rockchip-devices.patch b/patch/kernel/rockchip-dev/usb-dwc2-disable-power_down-on-rockchip-devices.patch.disabled similarity index 100% rename from patch/kernel/rockchip-dev/usb-dwc2-disable-power_down-on-rockchip-devices.patch rename to patch/kernel/rockchip-dev/usb-dwc2-disable-power_down-on-rockchip-devices.patch.disabled diff --git a/patch/kernel/rockchip-dev/wifi-2001-01-rtl8188eu-kconfig-makefile.patch b/patch/kernel/rockchip-dev/wifi-2001-01-rtl8188eu-kconfig-makefile.patch.disabled similarity index 100% rename from patch/kernel/rockchip-dev/wifi-2001-01-rtl8188eu-kconfig-makefile.patch rename to patch/kernel/rockchip-dev/wifi-2001-01-rtl8188eu-kconfig-makefile.patch.disabled diff --git a/patch/kernel/rockchip-dev/wifi-2002-02-rtl8188eu.patch b/patch/kernel/rockchip-dev/wifi-2002-02-rtl8188eu.patch.disabled similarity index 100% rename from patch/kernel/rockchip-dev/wifi-2002-02-rtl8188eu.patch rename to patch/kernel/rockchip-dev/wifi-2002-02-rtl8188eu.patch.disabled