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Add large SPI transfers patch to sunxi-next
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zador-blood-stained
parent
17d8ef385d
commit
fdd69714af
1 changed files with 158 additions and 0 deletions
158
patch/kernel/sunxi-next/spi-sunxi-allow-large-transfers.patch
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158
patch/kernel/sunxi-next/spi-sunxi-allow-large-transfers.patch
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@ -0,0 +1,158 @@
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diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
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index 4969dc1..138f224 100644
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--- a/drivers/spi/spi-sun4i.c
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+++ b/drivers/spi/spi-sun4i.c
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@@ -46,6 +46,8 @@
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#define SUN4I_CTL_TP BIT(18)
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#define SUN4I_INT_CTL_REG 0x0c
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+#define SUN4I_INT_CTL_RF_F34 BIT(4)
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+#define SUN4I_INT_CTL_TF_E34 BIT(12)
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#define SUN4I_INT_CTL_TC BIT(16)
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#define SUN4I_INT_STA_REG 0x10
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@@ -61,11 +63,14 @@
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#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
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#define SUN4I_CLK_CTL_DRS BIT(12)
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+#define SUN4I_MAX_XFER_SIZE 0xffffff
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+
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#define SUN4I_BURST_CNT_REG 0x20
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-#define SUN4I_BURST_CNT(cnt) ((cnt) & 0xffffff)
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+#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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#define SUN4I_XMIT_CNT_REG 0x24
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-#define SUN4I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
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+#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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+
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#define SUN4I_FIFO_STA_REG 0x28
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#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
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@@ -96,6 +101,31 @@ static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
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writel(value, sspi->base_addr + reg);
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}
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+static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
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+{
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+ u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
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+
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+ reg >>= SUN4I_FIFO_STA_TF_CNT_BITS;
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+
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+ return reg & SUN4I_FIFO_STA_TF_CNT_MASK;
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+}
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+
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+static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)
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+{
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+ u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
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+
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+ reg |= mask;
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+ sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
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+}
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+
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+static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask)
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+{
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+ u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
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+
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+ reg &= ~mask;
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+ sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
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+}
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+
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static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
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{
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u32 reg, cnt;
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@@ -118,10 +148,13 @@ static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
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static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
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{
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+ u32 cnt;
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u8 byte;
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- if (len > sspi->len)
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- len = sspi->len;
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+ /* See how much data we can fit */
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+ cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
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+
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+ len = min3(len, (int)cnt, sspi->len);
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while (len--) {
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byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
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@@ -169,7 +202,7 @@ static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
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static size_t sun4i_spi_max_transfer_size(struct spi_device *spi)
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{
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- return SUN4I_FIFO_DEPTH - 1;
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+ return SUN4I_MAX_XFER_SIZE - 1;
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}
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static int sun4i_spi_transfer_one(struct spi_master *master,
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@@ -183,11 +216,10 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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int ret = 0;
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u32 reg;
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- /* We don't support transfer larger than the FIFO */
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- if (tfr->len > SUN4I_FIFO_DEPTH)
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+ if (tfr->len > SUN4I_MAX_XFER_SIZE)
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return -EMSGSIZE;
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- if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH)
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+ if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE)
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return -EMSGSIZE;
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reinit_completion(&sspi->done);
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@@ -286,7 +318,11 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
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/* Enable the interrupts */
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- sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
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+ sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC |
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+ SUN4I_INT_CTL_RF_F34);
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+ /* Only enable Tx FIFO interrupt if we really need it */
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+ if (tx_len > SUN4I_FIFO_DEPTH)
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+ sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
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/* Start the transfer */
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reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
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@@ -306,8 +342,6 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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goto out;
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}
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- sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
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-
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out:
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sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
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@@ -322,10 +356,33 @@ static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
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/* Transfer complete */
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if (status & SUN4I_INT_CTL_TC) {
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sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
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+ sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
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complete(&sspi->done);
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return IRQ_HANDLED;
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}
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+ /* Receive FIFO 3/4 full */
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+ if (status & SUN4I_INT_CTL_RF_F34) {
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+ sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
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+ /* Only clear the interrupt _after_ draining the FIFO */
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+ sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34);
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+ return IRQ_HANDLED;
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+ }
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+
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+ /* Transmit FIFO 3/4 empty */
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+ if (status & SUN4I_INT_CTL_TF_E34) {
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+ sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
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+
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+ if (!sspi->len)
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+ /* nothing left to transmit */
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+ sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
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+
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+ /* Only clear the interrupt _after_ re-seeding the FIFO */
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+ sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34);
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+
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+ return IRQ_HANDLED;
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+ }
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+
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return IRQ_NONE;
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}
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