mirror of
https://github.com/Fishwaldo/build.git
synced 2025-03-16 03:41:26 +00:00
Move to 5.4.y (#1686)
* Wireguard: bump tag to most recent since it breaks building on 5.4.y * Move rockchip current to 5.4.y * Move sunxi current to 5.4.y * Move meson64 to 5.4.y * Move odroidxu4 to 5.4.y and enable "current" targets * Enable missing target
This commit is contained in:
Igor Pečovnik
GitHub
parent
f002ad749c
commit
ff4c1488da
388 changed files with 48288 additions and 1240143 deletions
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@ -3,5 +3,5 @@ BOARD_NAME="Odroid XU4"
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BOARDFAMILY="odroidxu4"
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BOOTCONFIG="odroid-xu4_defconfig"
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SERIALCON="ttySAC2"
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KERNEL_TARGET="legacy,dev"
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KERNEL_TARGET="legacy,current,dev"
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FULL_DESKTOP="yes"
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@ -1,6 +1,6 @@
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#
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# Automatically generated file; DO NOT EDIT.
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# Linux/arm64 5.3.16 Kernel Configuration
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# Linux/arm64 5.4.5 Kernel Configuration
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#
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#
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@ -11,6 +11,7 @@ CONFIG_GCC_VERSION=80300
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CONFIG_CLANG_VERSION=0
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CONFIG_CC_CAN_LINK=y
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CONFIG_CC_HAS_ASM_GOTO=y
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CONFIG_CC_HAS_ASM_INLINE=y
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CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y
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CONFIG_IRQ_WORK=y
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CONFIG_BUILDTIME_EXTABLE_SORT=y
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@ -393,6 +394,7 @@ CONFIG_HARDEN_EL2_VECTORS=y
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CONFIG_ARM64_SSBD=y
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CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
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# CONFIG_ARM64_SW_TTBR0_PAN is not set
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CONFIG_ARM64_TAGGED_ADDR_ABI=y
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CONFIG_COMPAT=y
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CONFIG_KUSER_HELPERS=y
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CONFIG_ARMV8_DEPRECATED=y
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@ -489,6 +491,7 @@ CONFIG_DT_IDLE_STATES=y
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# ARM CPU Idle Drivers
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#
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CONFIG_ARM_CPUIDLE=y
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CONFIG_ARM_PSCI_CPUIDLE=y
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# end of ARM CPU Idle Drivers
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# end of CPU Idle
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@ -663,6 +666,7 @@ CONFIG_JUMP_LABEL=y
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CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
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CONFIG_HAVE_KPROBES=y
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CONFIG_HAVE_KRETPROBES=y
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CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
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CONFIG_HAVE_NMI=y
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CONFIG_HAVE_ARCH_TRACEHOOK=y
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CONFIG_HAVE_DMA_CONTIGUOUS=y
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@ -673,6 +677,7 @@ CONFIG_ARCH_HAS_KEEPINITRD=y
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CONFIG_ARCH_HAS_SET_MEMORY=y
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CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
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CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
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CONFIG_HAVE_ASM_MODVERSIONS=y
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CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
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CONFIG_HAVE_RSEQ=y
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CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
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@ -707,6 +712,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
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CONFIG_ARCH_MMAP_RND_BITS=18
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CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
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CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_OLD_SIGSUSPEND3=y
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CONFIG_COMPAT_OLD_SIGACTION=y
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@ -744,6 +750,8 @@ CONFIG_MODULE_UNLOAD=y
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# CONFIG_MODULE_SRCVERSION_ALL is not set
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# CONFIG_MODULE_SIG is not set
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# CONFIG_MODULE_COMPRESS is not set
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# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
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# CONFIG_UNUSED_SYMBOLS is not set
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# CONFIG_TRIM_UNUSED_KSYMS is not set
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CONFIG_MODULES_TREE_LOOKUP=y
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CONFIG_BLOCK=y
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@ -757,6 +765,7 @@ CONFIG_BLK_DEV_THROTTLING=y
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# CONFIG_BLK_CMDLINE_PARSER is not set
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CONFIG_BLK_WBT=y
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# CONFIG_BLK_CGROUP_IOLATENCY is not set
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# CONFIG_BLK_CGROUP_IOCOST is not set
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CONFIG_BLK_WBT_MQ=y
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# CONFIG_BLK_DEBUG_FS is not set
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# CONFIG_BLK_SED_OPAL is not set
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@ -864,6 +873,7 @@ CONFIG_ARCH_HAS_PTE_DEVMAP=y
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CONFIG_FRAME_VECTOR=y
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# CONFIG_PERCPU_STATS is not set
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# CONFIG_GUP_BENCHMARK is not set
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# CONFIG_READ_ONLY_THP_FOR_FS is not set
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CONFIG_ARCH_HAS_PTE_SPECIAL=y
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# end of Memory Management options
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@ -1408,9 +1418,7 @@ CONFIG_NET_DSA_TAG_GSWIP=m
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CONFIG_NET_DSA_TAG_DSA=m
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CONFIG_NET_DSA_TAG_EDSA=m
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CONFIG_NET_DSA_TAG_MTK=m
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CONFIG_NET_DSA_TAG_KSZ_COMMON=m
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CONFIG_NET_DSA_TAG_KSZ=m
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CONFIG_NET_DSA_TAG_KSZ9477=m
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CONFIG_NET_DSA_TAG_QCA=m
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CONFIG_NET_DSA_TAG_LAN9303=m
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CONFIG_NET_DSA_TAG_SJA1105=m
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@ -1536,6 +1544,7 @@ CONFIG_NET_ACT_CONNMARK=m
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# CONFIG_NET_ACT_IFE is not set
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# CONFIG_NET_ACT_TUNNEL_KEY is not set
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# CONFIG_NET_ACT_CT is not set
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# CONFIG_NET_TC_SKB_EXT is not set
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CONFIG_NET_SCH_FIFO=y
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CONFIG_DCB=y
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CONFIG_DNS_RESOLVER=y
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@ -1609,6 +1618,7 @@ CONFIG_CAN=m
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CONFIG_CAN_RAW=m
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CONFIG_CAN_BCM=m
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CONFIG_CAN_GW=m
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CONFIG_CAN_J1939=m
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#
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# CAN Device Drivers
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@ -1621,6 +1631,7 @@ CONFIG_CAN_CALC_BITTIMING=y
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# CONFIG_CAN_FLEXCAN is not set
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CONFIG_CAN_GRCAN=m
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# CONFIG_CAN_JANZ_ICAN3 is not set
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CONFIG_CAN_KVASER_PCIEFD=m
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CONFIG_CAN_XILINXCAN=m
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CONFIG_CAN_C_CAN=m
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CONFIG_CAN_C_CAN_PLATFORM=m
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@ -1630,15 +1641,18 @@ CONFIG_CAN_CC770_ISA=m
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CONFIG_CAN_CC770_PLATFORM=m
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# CONFIG_CAN_IFI_CANFD is not set
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CONFIG_CAN_M_CAN=m
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CONFIG_CAN_M_CAN_PLATFORM=m
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CONFIG_CAN_M_CAN_TCAN4X5X=m
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CONFIG_CAN_PEAK_PCIEFD=m
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CONFIG_CAN_SJA1000=m
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CONFIG_CAN_SJA1000_ISA=m
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CONFIG_CAN_SJA1000_PLATFORM=m
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CONFIG_CAN_EMS_PCI=m
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CONFIG_CAN_F81601=m
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CONFIG_CAN_KVASER_PCI=m
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CONFIG_CAN_PEAK_PCI=m
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CONFIG_CAN_PEAK_PCIEC=y
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CONFIG_CAN_KVASER_PCI=m
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CONFIG_CAN_PLX_PCI=m
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CONFIG_CAN_SJA1000_ISA=m
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CONFIG_CAN_SJA1000_PLATFORM=m
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CONFIG_CAN_SOFTING=m
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#
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@ -1885,6 +1899,7 @@ CONFIG_PCIE_DW_HOST=y
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CONFIG_PCI_HISI=y
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CONFIG_PCIE_KIRIN=y
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CONFIG_PCI_MESON=y
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# CONFIG_PCIE_AL is not set
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# end of DesignWare PCI Core Support
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# end of PCI controller drivers
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@ -1948,6 +1963,7 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y
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# Bus devices
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#
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CONFIG_BRCMSTB_GISB_ARB=y
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# CONFIG_MOXTET is not set
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CONFIG_SIMPLE_PM_BUS=y
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CONFIG_VEXPRESS_CONFIG=y
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# end of Bus devices
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@ -1960,13 +1976,13 @@ CONFIG_GNSS_SIRF_SERIAL=m
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CONFIG_GNSS_UBX_SERIAL=m
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CONFIG_MTD=y
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# CONFIG_MTD_TESTS is not set
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# CONFIG_MTD_CMDLINE_PARTS is not set
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CONFIG_MTD_OF_PARTS=y
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# CONFIG_MTD_AR7_PARTS is not set
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#
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# Partition parsers
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#
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# CONFIG_MTD_AR7_PARTS is not set
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# CONFIG_MTD_CMDLINE_PARTS is not set
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CONFIG_MTD_OF_PARTS=y
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# CONFIG_MTD_AFS_PARTS is not set
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# CONFIG_MTD_REDBOOT_PARTS is not set
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# end of Partition parsers
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@ -2023,7 +2039,6 @@ CONFIG_MTD_PHYSMAP=m
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#
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# CONFIG_MTD_PMC551 is not set
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# CONFIG_MTD_DATAFLASH is not set
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CONFIG_MTD_M25P80=m
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# CONFIG_MTD_MCHP23K256 is not set
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# CONFIG_MTD_SST25L is not set
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# CONFIG_MTD_SLRAM is not set
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@ -2052,6 +2067,7 @@ CONFIG_MTD_NAND_DENALI=m
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CONFIG_MTD_NAND_DENALI_DT=m
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CONFIG_MTD_NAND_CAFE=m
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CONFIG_MTD_NAND_BRCMNAND=m
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CONFIG_MTD_NAND_MXIC=m
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CONFIG_MTD_NAND_MESON=m
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CONFIG_MTD_NAND_GPIO=m
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CONFIG_MTD_NAND_PLATFORM=m
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@ -2149,7 +2165,6 @@ CONFIG_NVME_TCP=m
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# CONFIG_AD525X_DPOT is not set
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# CONFIG_DUMMY_IRQ is not set
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CONFIG_PHANTOM=m
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CONFIG_SGI_IOC4=m
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CONFIG_TIFM_CORE=m
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CONFIG_TIFM_7XX1=m
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# CONFIG_ICS932S401 is not set
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@ -2365,6 +2380,7 @@ CONFIG_DM_CACHE=m
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CONFIG_DM_CACHE_SMQ=m
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# CONFIG_DM_WRITECACHE is not set
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CONFIG_DM_ERA=m
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CONFIG_DM_CLONE=m
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CONFIG_DM_MIRROR=m
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CONFIG_DM_LOG_USERSPACE=m
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CONFIG_DM_RAID=m
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@ -2377,6 +2393,7 @@ CONFIG_DM_DELAY=m
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# CONFIG_DM_UEVENT is not set
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# CONFIG_DM_FLAKEY is not set
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CONFIG_DM_VERITY=m
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# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
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# CONFIG_DM_VERITY_FEC is not set
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CONFIG_DM_SWITCH=m
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CONFIG_DM_LOG_WRITES=m
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@ -2463,7 +2480,10 @@ CONFIG_NET_DSA_MT7530=m
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CONFIG_NET_DSA_MV88E6060=m
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CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
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CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
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CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
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CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
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CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
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CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
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CONFIG_NET_DSA_MV88E6XXX=m
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CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
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# CONFIG_NET_DSA_MV88E6XXX_PTP is not set
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@ -2638,10 +2658,11 @@ CONFIG_NET_VENDOR_OKI=y
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CONFIG_NET_VENDOR_PACKET_ENGINES=y
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# CONFIG_HAMACHI is not set
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# CONFIG_YELLOWFIN is not set
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CONFIG_NET_VENDOR_PENSANDO=y
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CONFIG_IONIC=m
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CONFIG_NET_VENDOR_QLOGIC=y
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# CONFIG_QLA3XXX is not set
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# CONFIG_QLCNIC is not set
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# CONFIG_QLGE is not set
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# CONFIG_NETXEN_NIC is not set
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# CONFIG_QED is not set
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CONFIG_NET_VENDOR_QUALCOMM=y
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@ -2688,8 +2709,7 @@ CONFIG_NET_VENDOR_SUN=y
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# CONFIG_SUNGEM is not set
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# CONFIG_CASSINI is not set
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# CONFIG_NIU is not set
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CONFIG_NET_VENDOR_SYNOPSYS=y
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# CONFIG_DWC_XLGMAC is not set
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# CONFIG_NET_VENDOR_SYNOPSYS is not set
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CONFIG_NET_VENDOR_TEHUTI=y
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# CONFIG_TEHUTI is not set
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CONFIG_NET_VENDOR_TI=y
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@ -2728,6 +2748,7 @@ CONFIG_LED_TRIGGER_PHY=y
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# MII PHY device drivers
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#
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# CONFIG_SFP is not set
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CONFIG_ADIN_PHY=m
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CONFIG_AMD_PHY=m
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CONFIG_AQUANTIA_PHY=m
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CONFIG_AX88796B_PHY=m
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@ -2853,6 +2874,7 @@ CONFIG_ATH9K_WOW=y
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CONFIG_ATH9K_RFKILL=y
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CONFIG_ATH9K_CHANNEL_CONTEXT=y
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CONFIG_ATH9K_PCOEM=y
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CONFIG_ATH9K_PCI_NO_EEPROM=m
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CONFIG_ATH9K_HTC=m
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# CONFIG_ATH9K_HTC_DEBUGFS is not set
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# CONFIG_ATH9K_HWRNG is not set
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@ -3324,10 +3346,10 @@ CONFIG_SERIAL_8250_EXTENDED=y
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CONFIG_SERIAL_8250_SHARE_IRQ=y
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# CONFIG_SERIAL_8250_DETECT_IRQ is not set
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# CONFIG_SERIAL_8250_RSA is not set
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CONFIG_SERIAL_8250_DWLIB=y
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CONFIG_SERIAL_8250_FSL=y
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CONFIG_SERIAL_8250_DW=y
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# CONFIG_SERIAL_8250_RT288X is not set
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CONFIG_SERIAL_8250_MOXA=m
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CONFIG_SERIAL_OF_PLATFORM=y
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#
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@ -3357,6 +3379,7 @@ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
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# CONFIG_SERIAL_ARC is not set
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# CONFIG_SERIAL_RP2 is not set
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# CONFIG_SERIAL_FSL_LPUART is not set
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CONFIG_SERIAL_FSL_LINFLEXUART=m
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# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
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# end of Serial drivers
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@ -3391,12 +3414,15 @@ CONFIG_TCG_TIS_I2C_INFINEON=y
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# CONFIG_TCG_XEN is not set
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# CONFIG_TCG_CRB is not set
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# CONFIG_TCG_VTPM_PROXY is not set
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# CONFIG_TCG_FTPM_TEE is not set
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# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
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# CONFIG_TCG_TIS_ST33ZP24_SPI is not set
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CONFIG_DEVPORT=y
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# CONFIG_XILLYBUS is not set
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# end of Character devices
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# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
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#
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# I2C support
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#
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@ -3676,6 +3702,7 @@ CONFIG_W1_MASTER_DS2490=m
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CONFIG_W1_MASTER_DS2482=m
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CONFIG_W1_MASTER_DS1WM=m
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CONFIG_W1_MASTER_GPIO=m
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CONFIG_W1_MASTER_SGI=m
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# end of 1-wire Bus Masters
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#
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@ -3694,6 +3721,7 @@ CONFIG_W1_SLAVE_DS2431=m
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CONFIG_W1_SLAVE_DS2433=m
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# CONFIG_W1_SLAVE_DS2433_CRC is not set
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# CONFIG_W1_SLAVE_DS2438 is not set
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CONFIG_W1_SLAVE_DS250X=m
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CONFIG_W1_SLAVE_DS2780=m
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CONFIG_W1_SLAVE_DS2781=m
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CONFIG_W1_SLAVE_DS28E04=m
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@ -3776,6 +3804,7 @@ CONFIG_SENSORS_ADT7411=m
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CONFIG_SENSORS_ADT7462=m
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CONFIG_SENSORS_ADT7470=m
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CONFIG_SENSORS_ADT7475=m
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CONFIG_SENSORS_AS370=m
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CONFIG_SENSORS_ASC7621=m
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CONFIG_SENSORS_ARM_SCMI=m
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CONFIG_SENSORS_ARM_SCPI=m
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@ -3853,6 +3882,7 @@ CONFIG_PMBUS=m
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CONFIG_SENSORS_PMBUS=m
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CONFIG_SENSORS_ADM1275=m
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CONFIG_SENSORS_IBM_CFFPS=m
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CONFIG_SENSORS_INSPUR_IPSPS=m
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CONFIG_SENSORS_IR35221=m
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||||
CONFIG_SENSORS_IR38064=m
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||||
# CONFIG_SENSORS_IRPS5401 is not set
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@ -3890,7 +3920,6 @@ CONFIG_SENSORS_SCH5636=m
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|||
CONFIG_SENSORS_STTS751=m
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CONFIG_SENSORS_SMM665=m
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||||
CONFIG_SENSORS_ADC128D818=m
|
||||
CONFIG_SENSORS_ADS1015=m
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||||
CONFIG_SENSORS_ADS7828=m
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||||
CONFIG_SENSORS_ADS7871=m
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||||
CONFIG_SENSORS_AMC6821=m
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||||
|
|
@ -4029,8 +4058,7 @@ CONFIG_MFD_CORE=y
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|||
# CONFIG_MFD_BCM590XX is not set
|
||||
CONFIG_MFD_BD9571MWV=y
|
||||
# CONFIG_MFD_AXP20X_I2C is not set
|
||||
CONFIG_MFD_CROS_EC=y
|
||||
# CONFIG_MFD_CROS_EC_CHARDEV is not set
|
||||
# CONFIG_MFD_CROS_EC_DEV is not set
|
||||
# CONFIG_MFD_MADERA is not set
|
||||
# CONFIG_PMIC_DA903X is not set
|
||||
# CONFIG_MFD_DA9052_SPI is not set
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||||
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|
@ -4169,6 +4197,7 @@ CONFIG_REGULATOR_S2MPS11=y
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|||
# CONFIG_REGULATOR_S5M8767 is not set
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||||
# CONFIG_REGULATOR_SLG51000 is not set
|
||||
# CONFIG_REGULATOR_SY8106A is not set
|
||||
CONFIG_REGULATOR_SY8824X=m
|
||||
# CONFIG_REGULATOR_TPS51632 is not set
|
||||
# CONFIG_REGULATOR_TPS62360 is not set
|
||||
# CONFIG_REGULATOR_TPS65023 is not set
|
||||
|
|
@ -4239,6 +4268,7 @@ CONFIG_MEDIA_CONTROLLER_DVB=y
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|||
CONFIG_VIDEO_DEV=m
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
CONFIG_VIDEO_V4L2=m
|
||||
CONFIG_VIDEO_V4L2_I2C=y
|
||||
CONFIG_VIDEO_ADV_DEBUG=y
|
||||
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
|
||||
CONFIG_VIDEO_TUNER=m
|
||||
|
|
@ -4594,6 +4624,7 @@ CONFIG_VIDEO_OV2640=m
|
|||
# CONFIG_VIDEO_OV5647 is not set
|
||||
# CONFIG_VIDEO_OV6650 is not set
|
||||
# CONFIG_VIDEO_OV5670 is not set
|
||||
CONFIG_VIDEO_OV5675=m
|
||||
# CONFIG_VIDEO_OV5695 is not set
|
||||
# CONFIG_VIDEO_OV7251 is not set
|
||||
# CONFIG_VIDEO_OV772X is not set
|
||||
|
|
@ -4898,6 +4929,7 @@ CONFIG_DVB_SP2=m
|
|||
CONFIG_VGA_ARB=y
|
||||
CONFIG_VGA_ARB_MAX_GPUS=16
|
||||
CONFIG_DRM=m
|
||||
CONFIG_DRM_MIPI_DBI=m
|
||||
CONFIG_DRM_MIPI_DSI=y
|
||||
# CONFIG_DRM_DP_AUX_CHARDEV is not set
|
||||
# CONFIG_DRM_DEBUG_SELFTEST is not set
|
||||
|
|
@ -4912,6 +4944,7 @@ CONFIG_DRM_TTM=m
|
|||
CONFIG_DRM_VRAM_HELPER=m
|
||||
CONFIG_DRM_GEM_CMA_HELPER=y
|
||||
CONFIG_DRM_KMS_CMA_HELPER=y
|
||||
CONFIG_DRM_GEM_SHMEM_HELPER=y
|
||||
CONFIG_DRM_VM=y
|
||||
CONFIG_DRM_SCHED=m
|
||||
|
||||
|
|
@ -4970,12 +5003,16 @@ CONFIG_DRM_PANEL_ARM_VERSATILE=m
|
|||
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
|
||||
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
|
||||
CONFIG_DRM_PANEL_LG_LB035Q02=m
|
||||
# CONFIG_DRM_PANEL_LG_LG4573 is not set
|
||||
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
|
||||
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
|
||||
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
|
||||
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
|
||||
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
|
||||
# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
|
||||
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
|
||||
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
|
||||
# CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set
|
||||
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
|
||||
|
|
@ -4986,9 +5023,13 @@ CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
|
|||
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
|
||||
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
|
||||
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
|
||||
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
||||
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
|
||||
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
|
||||
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
|
||||
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
|
||||
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
|
||||
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
|
||||
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
|
||||
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
|
||||
# end of Display Panels
|
||||
|
|
@ -5018,7 +5059,7 @@ CONFIG_DRM_TOSHIBA_TC358764=m
|
|||
CONFIG_DRM_DW_HDMI=m
|
||||
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
|
||||
CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
|
||||
CONFIG_DRM_DW_HDMI_CEC=m
|
||||
# CONFIG_DRM_DW_HDMI_CEC is not set
|
||||
# end of Display Interface Bridges
|
||||
|
||||
# CONFIG_DRM_ETNAVIV is not set
|
||||
|
|
@ -5028,7 +5069,14 @@ CONFIG_DRM_DW_HDMI_CEC=m
|
|||
# CONFIG_DRM_MXSFB is not set
|
||||
CONFIG_DRM_MESON=m
|
||||
CONFIG_DRM_MESON_DW_HDMI=m
|
||||
# CONFIG_DRM_TINYDRM is not set
|
||||
CONFIG_DRM_GM12U320=m
|
||||
CONFIG_TINYDRM_HX8357D=m
|
||||
CONFIG_TINYDRM_ILI9225=m
|
||||
CONFIG_TINYDRM_ILI9341=m
|
||||
CONFIG_TINYDRM_MI0283QT=m
|
||||
CONFIG_TINYDRM_REPAPER=m
|
||||
CONFIG_TINYDRM_ST7586=m
|
||||
CONFIG_TINYDRM_ST7735R=m
|
||||
# CONFIG_DRM_PL111 is not set
|
||||
# CONFIG_DRM_XEN is not set
|
||||
CONFIG_DRM_LIMA=m
|
||||
|
|
@ -5451,6 +5499,7 @@ CONFIG_SND_SOC_TLV320AIC3X=m
|
|||
CONFIG_SND_SOC_TS3A227E=m
|
||||
CONFIG_SND_SOC_TSCS42XX=m
|
||||
CONFIG_SND_SOC_TSCS454=m
|
||||
CONFIG_SND_SOC_UDA1334=m
|
||||
CONFIG_SND_SOC_WM8510=m
|
||||
CONFIG_SND_SOC_WM8523=m
|
||||
CONFIG_SND_SOC_WM8524=m
|
||||
|
|
@ -5523,6 +5572,7 @@ CONFIG_HID_CORSAIR=m
|
|||
CONFIG_HID_PRODIKEYS=m
|
||||
# CONFIG_HID_CMEDIA is not set
|
||||
# CONFIG_HID_CP2112 is not set
|
||||
CONFIG_HID_CREATIVE_SB0540=m
|
||||
CONFIG_HID_CYPRESS=m
|
||||
CONFIG_HID_DRAGONRISE=m
|
||||
CONFIG_DRAGONRISE_FF=y
|
||||
|
|
@ -5631,6 +5681,9 @@ CONFIG_I2C_HID=m
|
|||
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_COMMON=y
|
||||
# CONFIG_USB_LED_TRIG is not set
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
CONFIG_USB_CONN_GPIO=m
|
||||
CONFIG_USB_ARCH_HAS_HCD=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_PCI=y
|
||||
|
|
@ -5648,7 +5701,6 @@ CONFIG_USB_OTG_FSM=m
|
|||
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
|
||||
CONFIG_USB_AUTOSUSPEND_DELAY=2
|
||||
CONFIG_USB_MON=m
|
||||
# CONFIG_USB_WUSB_CBAF is not set
|
||||
|
||||
#
|
||||
# USB Host Controller Drivers
|
||||
|
|
@ -5724,6 +5776,10 @@ CONFIG_USBIP_VHCI_NR_HCS=1
|
|||
CONFIG_USBIP_HOST=m
|
||||
CONFIG_USBIP_VUDC=m
|
||||
# CONFIG_USBIP_DEBUG is not set
|
||||
CONFIG_USB_CDNS3=m
|
||||
# CONFIG_USB_CDNS3_GADGET is not set
|
||||
# CONFIG_USB_CDNS3_HOST is not set
|
||||
CONFIG_USB_CDNS3_PCI_WRAP=m
|
||||
CONFIG_USB_MUSB_HDRC=y
|
||||
# CONFIG_USB_MUSB_HOST is not set
|
||||
# CONFIG_USB_MUSB_GADGET is not set
|
||||
|
|
@ -5936,9 +5992,6 @@ CONFIG_TYPEC_DP_ALTMODE=m
|
|||
# end of USB Type-C Alternate Mode drivers
|
||||
|
||||
CONFIG_USB_ROLE_SWITCH=y
|
||||
# CONFIG_USB_LED_TRIG is not set
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
# CONFIG_UWB is not set
|
||||
CONFIG_MMC=y
|
||||
CONFIG_PWRSEQ_EMMC=y
|
||||
# CONFIG_PWRSEQ_SD8787 is not set
|
||||
|
|
@ -5959,6 +6012,7 @@ CONFIG_MMC_SDHCI=y
|
|||
CONFIG_MMC_SDHCI_ACPI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_ASPEED=m
|
||||
# CONFIG_MMC_SDHCI_OF_AT91 is not set
|
||||
CONFIG_MMC_SDHCI_OF_DWCMSHC=m
|
||||
CONFIG_MMC_SDHCI_CADENCE=y
|
||||
|
|
@ -6100,6 +6154,7 @@ CONFIG_RTC_DRV_DS1307=m
|
|||
# CONFIG_RTC_DRV_HYM8563 is not set
|
||||
# CONFIG_RTC_DRV_MAX6900 is not set
|
||||
CONFIG_RTC_DRV_MAX77686=y
|
||||
CONFIG_RTC_DRV_MESON_VRTC=m
|
||||
CONFIG_RTC_DRV_RK808=m
|
||||
# CONFIG_RTC_DRV_RS5C372 is not set
|
||||
# CONFIG_RTC_DRV_ISL1208 is not set
|
||||
|
|
@ -6229,6 +6284,7 @@ CONFIG_DMA_ENGINE_RAID=y
|
|||
CONFIG_SYNC_FILE=y
|
||||
# CONFIG_SW_SYNC is not set
|
||||
# CONFIG_UDMABUF is not set
|
||||
# CONFIG_DMABUF_SELFTESTS is not set
|
||||
# end of DMABUF options
|
||||
|
||||
# CONFIG_AUXDISPLAY is not set
|
||||
|
|
@ -6289,6 +6345,7 @@ CONFIG_XEN_AUTO_XLATE=y
|
|||
CONFIG_XEN_FRONT_PGDIR_SHBUF=m
|
||||
# end of Xen driver support
|
||||
|
||||
# CONFIG_GREYBUS is not set
|
||||
CONFIG_STAGING=y
|
||||
# CONFIG_PRISM2_USB is not set
|
||||
# CONFIG_COMEDI is not set
|
||||
|
|
@ -6373,7 +6430,6 @@ CONFIG_FB_SM750=m
|
|||
# end of Speakup console speech
|
||||
|
||||
CONFIG_STAGING_MEDIA=y
|
||||
CONFIG_I2C_BCM2048=m
|
||||
CONFIG_VIDEO_MESON_VDEC=m
|
||||
|
||||
#
|
||||
|
|
@ -6422,8 +6478,6 @@ CONFIG_FB_TFT_UC1611=m
|
|||
CONFIG_FB_TFT_UC1701=m
|
||||
CONFIG_FB_TFT_UPD161704=m
|
||||
CONFIG_FB_TFT_WATTEROTT=m
|
||||
CONFIG_FB_FLEX=m
|
||||
CONFIG_FB_TFT_FBTFT_DEVICE=m
|
||||
# CONFIG_WILC1000_SDIO is not set
|
||||
# CONFIG_WILC1000_SPI is not set
|
||||
CONFIG_MOST=m
|
||||
|
|
@ -6435,7 +6489,6 @@ CONFIG_MOST=m
|
|||
# CONFIG_MOST_I2C is not set
|
||||
# CONFIG_MOST_USB is not set
|
||||
# CONFIG_KS7010 is not set
|
||||
# CONFIG_GREYBUS is not set
|
||||
# CONFIG_PI433 is not set
|
||||
|
||||
#
|
||||
|
|
@ -6446,12 +6499,24 @@ CONFIG_STAGING_GASKET_FRAMEWORK=m
|
|||
# end of Gasket devices
|
||||
|
||||
# CONFIG_XIL_AXIS_FIFO is not set
|
||||
# CONFIG_EROFS_FS is not set
|
||||
# CONFIG_FIELDBUS_DEV is not set
|
||||
# CONFIG_KPC2000 is not set
|
||||
# CONFIG_USB_WUSB_CBAF is not set
|
||||
# CONFIG_UWB is not set
|
||||
CONFIG_EXFAT_FS=m
|
||||
CONFIG_EXFAT_DONT_MOUNT_VFAT=y
|
||||
CONFIG_EXFAT_DISCARD=y
|
||||
# CONFIG_EXFAT_DELAYED_SYNC is not set
|
||||
# CONFIG_EXFAT_KERNEL_DEBUG is not set
|
||||
# CONFIG_EXFAT_DEBUG_MSG is not set
|
||||
CONFIG_EXFAT_DEFAULT_CODEPAGE=437
|
||||
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
|
||||
# CONFIG_QLGE is not set
|
||||
# CONFIG_GOLDFISH is not set
|
||||
CONFIG_MFD_CROS_EC=y
|
||||
CONFIG_CHROME_PLATFORMS=y
|
||||
# CONFIG_CHROMEOS_TBMC is not set
|
||||
CONFIG_CROS_EC=y
|
||||
# CONFIG_CROS_EC_I2C is not set
|
||||
# CONFIG_CROS_EC_RPMSG is not set
|
||||
# CONFIG_CROS_EC_SPI is not set
|
||||
|
|
@ -6488,7 +6553,6 @@ CONFIG_COMMON_CLK_XGENE=y
|
|||
CONFIG_COMMON_CLK_PWM=y
|
||||
# CONFIG_COMMON_CLK_VC5 is not set
|
||||
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
|
||||
CONFIG_COMMON_CLK_MESON_INPUT=y
|
||||
CONFIG_COMMON_CLK_MESON_REGMAP=y
|
||||
CONFIG_COMMON_CLK_MESON_DUALDIV=y
|
||||
CONFIG_COMMON_CLK_MESON_MPLL=y
|
||||
|
|
@ -6496,6 +6560,7 @@ CONFIG_COMMON_CLK_MESON_PLL=y
|
|||
CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
|
||||
CONFIG_COMMON_CLK_MESON_AO_CLKC=y
|
||||
CONFIG_COMMON_CLK_MESON_EE_CLKC=y
|
||||
CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
|
||||
CONFIG_COMMON_CLK_GXBB=y
|
||||
CONFIG_COMMON_CLK_AXG=y
|
||||
# CONFIG_COMMON_CLK_AXG_AUDIO is not set
|
||||
|
|
@ -6578,6 +6643,7 @@ CONFIG_MESON_CANVAS=m
|
|||
CONFIG_MESON_CLK_MEASURE=y
|
||||
CONFIG_MESON_GX_SOCINFO=y
|
||||
CONFIG_MESON_GX_PM_DOMAINS=y
|
||||
CONFIG_MESON_EE_PM_DOMAINS=y
|
||||
CONFIG_MESON_MX_SOCINFO=y
|
||||
# end of Amlogic SoC drivers
|
||||
|
||||
|
|
@ -6681,7 +6747,6 @@ CONFIG_DMARD06=m
|
|||
CONFIG_DMARD09=m
|
||||
CONFIG_DMARD10=m
|
||||
CONFIG_HID_SENSOR_ACCEL_3D=m
|
||||
CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
|
||||
CONFIG_IIO_ST_ACCEL_3AXIS=m
|
||||
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
|
||||
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
|
||||
|
|
@ -6926,6 +6991,7 @@ CONFIG_SI7020=m
|
|||
# Inertial measurement units
|
||||
#
|
||||
# CONFIG_ADIS16400 is not set
|
||||
# CONFIG_ADIS16460 is not set
|
||||
# CONFIG_ADIS16480 is not set
|
||||
# CONFIG_BMI160_I2C is not set
|
||||
# CONFIG_BMI160_SPI is not set
|
||||
|
|
@ -6965,6 +7031,7 @@ CONFIG_LTR501=m
|
|||
CONFIG_LV0104CS=m
|
||||
CONFIG_MAX44000=m
|
||||
CONFIG_MAX44009=m
|
||||
CONFIG_NOA1305=m
|
||||
CONFIG_OPT3001=m
|
||||
CONFIG_PA12203001=m
|
||||
CONFIG_SI1133=m
|
||||
|
|
@ -7035,6 +7102,7 @@ CONFIG_IIO_SYSFS_TRIGGER=m
|
|||
#
|
||||
CONFIG_AD5272=m
|
||||
# CONFIG_DS1803 is not set
|
||||
CONFIG_MAX5432=m
|
||||
# CONFIG_MAX5481 is not set
|
||||
# CONFIG_MAX5487 is not set
|
||||
CONFIG_MCP4018=m
|
||||
|
|
@ -7139,6 +7207,7 @@ CONFIG_MESON_IRQ_GPIO=y
|
|||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RESET_MESON=y
|
||||
CONFIG_RESET_MESON_AUDIO_ARB=m
|
||||
CONFIG_RESET_SCMI=y
|
||||
# CONFIG_RESET_TI_SYSCON is not set
|
||||
|
||||
#
|
||||
|
|
@ -7299,6 +7368,7 @@ CONFIG_EXPORTFS_BLOCK_OPS=y
|
|||
CONFIG_FILE_LOCKING=y
|
||||
CONFIG_MANDATORY_FILE_LOCKING=y
|
||||
CONFIG_FS_ENCRYPTION=y
|
||||
# CONFIG_FS_VERITY is not set
|
||||
CONFIG_FSNOTIFY=y
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
|
|
@ -7316,6 +7386,7 @@ CONFIG_AUTOFS4_FS=y
|
|||
CONFIG_AUTOFS_FS=y
|
||||
CONFIG_FUSE_FS=m
|
||||
CONFIG_CUSE=m
|
||||
CONFIG_VIRTIO_FS=m
|
||||
CONFIG_OVERLAY_FS=m
|
||||
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
|
||||
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
|
||||
|
|
@ -7432,24 +7503,7 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
|
|||
# CONFIG_PSTORE_RAM is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
CONFIG_AUFS_FS=m
|
||||
CONFIG_AUFS_BRANCH_MAX_127=y
|
||||
# CONFIG_AUFS_BRANCH_MAX_511 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_1023 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_32767 is not set
|
||||
CONFIG_AUFS_SBILIST=y
|
||||
# CONFIG_AUFS_HNOTIFY is not set
|
||||
# CONFIG_AUFS_EXPORT is not set
|
||||
# CONFIG_AUFS_XATTR is not set
|
||||
# CONFIG_AUFS_FHSM is not set
|
||||
# CONFIG_AUFS_RDU is not set
|
||||
# CONFIG_AUFS_DIRREN is not set
|
||||
# CONFIG_AUFS_SHWH is not set
|
||||
# CONFIG_AUFS_BR_RAMFS is not set
|
||||
# CONFIG_AUFS_BR_FUSE is not set
|
||||
CONFIG_AUFS_BR_HFSPLUS=y
|
||||
CONFIG_AUFS_BDEV_LOOP=y
|
||||
# CONFIG_AUFS_DEBUG is not set
|
||||
# CONFIG_EROFS_FS is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V2=y
|
||||
|
|
@ -7478,7 +7532,6 @@ CONFIG_NFSD_BLOCKLAYOUT=y
|
|||
CONFIG_NFSD_SCSILAYOUT=y
|
||||
CONFIG_NFSD_FLEXFILELAYOUT=y
|
||||
CONFIG_NFSD_V4_SECURITY_LABEL=y
|
||||
# CONFIG_NFSD_FAULT_INJECTION is not set
|
||||
CONFIG_GRACE_PERIOD=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
|
|
@ -7603,6 +7656,7 @@ CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
|
|||
# CONFIG_SECURITY_LOADPIN is not set
|
||||
# CONFIG_SECURITY_YAMA is not set
|
||||
# CONFIG_SECURITY_SAFESETID is not set
|
||||
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
|
||||
CONFIG_INTEGRITY=y
|
||||
# CONFIG_INTEGRITY_SIGNATURE is not set
|
||||
CONFIG_INTEGRITY_AUDIT=y
|
||||
|
|
@ -7686,10 +7740,7 @@ CONFIG_CRYPTO_CCM=y
|
|||
CONFIG_CRYPTO_GCM=y
|
||||
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
|
||||
CONFIG_CRYPTO_AEGIS128=m
|
||||
CONFIG_CRYPTO_AEGIS128L=m
|
||||
CONFIG_CRYPTO_AEGIS256=m
|
||||
CONFIG_CRYPTO_MORUS640=m
|
||||
CONFIG_CRYPTO_MORUS1280=m
|
||||
CONFIG_CRYPTO_AEGIS128_SIMD=y
|
||||
CONFIG_CRYPTO_SEQIV=y
|
||||
CONFIG_CRYPTO_ECHAINIV=y
|
||||
|
||||
|
|
@ -7708,6 +7759,7 @@ CONFIG_CRYPTO_XTS=y
|
|||
CONFIG_CRYPTO_KEYWRAP=m
|
||||
CONFIG_CRYPTO_NHPOLY1305=m
|
||||
CONFIG_CRYPTO_ADIANTUM=m
|
||||
CONFIG_CRYPTO_ESSIV=m
|
||||
|
||||
#
|
||||
# Hash modes
|
||||
|
|
@ -7734,6 +7786,7 @@ CONFIG_CRYPTO_RMD160=m
|
|||
CONFIG_CRYPTO_RMD256=m
|
||||
CONFIG_CRYPTO_RMD320=m
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_LIB_SHA256=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
CONFIG_CRYPTO_SHA3=m
|
||||
|
|
@ -7745,6 +7798,7 @@ CONFIG_CRYPTO_WP512=m
|
|||
#
|
||||
# Ciphers
|
||||
#
|
||||
CONFIG_CRYPTO_LIB_AES=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
CONFIG_CRYPTO_AES_TI=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
|
|
@ -7756,6 +7810,7 @@ CONFIG_CRYPTO_CAMELLIA=m
|
|||
CONFIG_CRYPTO_CAST_COMMON=m
|
||||
CONFIG_CRYPTO_CAST5=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_LIB_DES=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_FCRYPT=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
|
|
@ -7802,8 +7857,12 @@ CONFIG_CRYPTO_HW=y
|
|||
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
|
||||
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
|
||||
CONFIG_CRYPTO_DEV_VIRTIO=m
|
||||
CONFIG_CRYPTO_DEV_SAFEXCEL=m
|
||||
CONFIG_CRYPTO_DEV_CCREE=m
|
||||
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
|
||||
CONFIG_CRYPTO_DEV_HISI_QM=m
|
||||
CONFIG_CRYPTO_HISI_SGL=m
|
||||
CONFIG_CRYPTO_DEV_HISI_ZIP=m
|
||||
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
|
||||
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
|
||||
CONFIG_ASYMMETRIC_KEY_TYPE=y
|
||||
|
|
@ -7911,7 +7970,6 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
|
|||
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
|
||||
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
|
||||
CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
|
||||
CONFIG_ARCH_HAS_DMA_MMAP_PGPROT=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_DMA_REMAP=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
|
|
@ -7947,6 +8005,7 @@ CONFIG_FONT_SUPPORT=y
|
|||
# CONFIG_FONTS is not set
|
||||
CONFIG_FONT_8x8=y
|
||||
CONFIG_FONT_8x16=y
|
||||
CONFIG_SG_SPLIT=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SBITMAP=y
|
||||
# CONFIG_STRING_SELFTEST is not set
|
||||
|
|
@ -7976,10 +8035,9 @@ CONFIG_ENABLE_MUST_CHECK=y
|
|||
CONFIG_FRAME_WARN=2048
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_READABLE_ASM is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_INSTALL is not set
|
||||
# CONFIG_OPTIMIZE_INLINING is not set
|
||||
CONFIG_OPTIMIZE_INLINING=y
|
||||
# CONFIG_DEBUG_SECTION_MISMATCH is not set
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
CONFIG_ARCH_WANT_FRAME_POINTERS=y
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
1
config/kernel/linux-meson64-dev.config
Symbolic link
1
config/kernel/linux-meson64-dev.config
Symbolic link
|
|
@ -0,0 +1 @@
|
|||
linux-meson64-current.config
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
1
config/kernel/linux-odroidxu4-dev.config
Symbolic link
1
config/kernel/linux-odroidxu4-dev.config
Symbolic link
|
|
@ -0,0 +1 @@
|
|||
linux-odroidxu4-current.config
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 5.3.15 Kernel Configuration
|
||||
# Linux/arm 5.4.5 Kernel Configuration
|
||||
#
|
||||
|
||||
#
|
||||
|
|
@ -11,6 +11,7 @@ CONFIG_GCC_VERSION=80300
|
|||
CONFIG_CLANG_VERSION=0
|
||||
CONFIG_CC_CAN_LINK=y
|
||||
CONFIG_CC_HAS_ASM_GOTO=y
|
||||
CONFIG_CC_HAS_ASM_INLINE=y
|
||||
CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_BUILDTIME_EXTABLE_SORT=y
|
||||
|
|
@ -261,19 +262,13 @@ CONFIG_ARCH_MULTIPLATFORM=y
|
|||
# CONFIG_ARCH_EBSA110 is not set
|
||||
# CONFIG_ARCH_EP93XX is not set
|
||||
# CONFIG_ARCH_FOOTBRIDGE is not set
|
||||
# CONFIG_ARCH_IOP13XX is not set
|
||||
# CONFIG_ARCH_IOP32X is not set
|
||||
# CONFIG_ARCH_IOP33X is not set
|
||||
# CONFIG_ARCH_IXP4XX is not set
|
||||
# CONFIG_ARCH_DOVE is not set
|
||||
# CONFIG_ARCH_KS8695 is not set
|
||||
# CONFIG_ARCH_W90X900 is not set
|
||||
# CONFIG_ARCH_LPC32XX is not set
|
||||
# CONFIG_ARCH_PXA is not set
|
||||
# CONFIG_ARCH_RPC is not set
|
||||
# CONFIG_ARCH_SA1100 is not set
|
||||
# CONFIG_ARCH_S3C24XX is not set
|
||||
# CONFIG_ARCH_DAVINCI is not set
|
||||
# CONFIG_ARCH_OMAP1 is not set
|
||||
|
||||
#
|
||||
|
|
@ -292,6 +287,7 @@ CONFIG_ARCH_MULTI_V6_V7=y
|
|||
# CONFIG_ARCH_ACTIONS is not set
|
||||
# CONFIG_ARCH_ALPINE is not set
|
||||
# CONFIG_ARCH_ARTPEC is not set
|
||||
# CONFIG_ARCH_ASPEED is not set
|
||||
# CONFIG_ARCH_AT91 is not set
|
||||
# CONFIG_ARCH_BCM is not set
|
||||
# CONFIG_ARCH_BERLIN is not set
|
||||
|
|
@ -647,6 +643,7 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
|
|||
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
|
||||
CONFIG_HAVE_EXIT_THREAD=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=8
|
||||
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
CONFIG_OLD_SIGACTION=y
|
||||
|
|
@ -683,6 +680,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
|
|||
# CONFIG_MODULE_SRCVERSION_ALL is not set
|
||||
# CONFIG_MODULE_SIG is not set
|
||||
# CONFIG_MODULE_COMPRESS is not set
|
||||
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_TRIM_UNUSED_KSYMS is not set
|
||||
CONFIG_MODULES_TREE_LOOKUP=y
|
||||
CONFIG_BLOCK=y
|
||||
|
|
@ -696,6 +695,7 @@ CONFIG_BLK_DEV_THROTTLING=y
|
|||
# CONFIG_BLK_CMDLINE_PARSER is not set
|
||||
# CONFIG_BLK_WBT is not set
|
||||
# CONFIG_BLK_CGROUP_IOLATENCY is not set
|
||||
# CONFIG_BLK_CGROUP_IOCOST is not set
|
||||
CONFIG_BLK_DEBUG_FS=y
|
||||
# CONFIG_BLK_SED_OPAL is not set
|
||||
|
||||
|
|
@ -724,6 +724,7 @@ CONFIG_EFI_PARTITION=y
|
|||
# CONFIG_CMDLINE_PARTITION is not set
|
||||
# end of Partition Types
|
||||
|
||||
CONFIG_BLK_MQ_VIRTIO=y
|
||||
CONFIG_BLK_PM=y
|
||||
|
||||
#
|
||||
|
|
@ -1326,9 +1327,7 @@ CONFIG_NET_DSA_TAG_GSWIP=m
|
|||
CONFIG_NET_DSA_TAG_DSA=m
|
||||
CONFIG_NET_DSA_TAG_EDSA=m
|
||||
CONFIG_NET_DSA_TAG_MTK=m
|
||||
CONFIG_NET_DSA_TAG_KSZ_COMMON=m
|
||||
CONFIG_NET_DSA_TAG_KSZ=m
|
||||
CONFIG_NET_DSA_TAG_KSZ9477=m
|
||||
CONFIG_NET_DSA_TAG_QCA=m
|
||||
CONFIG_NET_DSA_TAG_LAN9303=m
|
||||
CONFIG_NET_DSA_TAG_SJA1105=m
|
||||
|
|
@ -1458,6 +1457,7 @@ CONFIG_NET_ACT_TUNNEL_KEY=m
|
|||
CONFIG_NET_IFE_SKBMARK=m
|
||||
CONFIG_NET_IFE_SKBPRIO=m
|
||||
CONFIG_NET_IFE_SKBTCINDEX=m
|
||||
# CONFIG_NET_TC_SKB_EXT is not set
|
||||
CONFIG_NET_SCH_FIFO=y
|
||||
CONFIG_DCB=y
|
||||
CONFIG_DNS_RESOLVER=y
|
||||
|
|
@ -1508,6 +1508,7 @@ CONFIG_CAN=y
|
|||
CONFIG_CAN_RAW=m
|
||||
CONFIG_CAN_BCM=m
|
||||
CONFIG_CAN_GW=m
|
||||
CONFIG_CAN_J1939=m
|
||||
|
||||
#
|
||||
# CAN Device Drivers
|
||||
|
|
@ -1527,6 +1528,8 @@ CONFIG_CAN_CC770_ISA=m
|
|||
CONFIG_CAN_CC770_PLATFORM=m
|
||||
CONFIG_CAN_IFI_CANFD=m
|
||||
CONFIG_CAN_M_CAN=m
|
||||
CONFIG_CAN_M_CAN_PLATFORM=m
|
||||
CONFIG_CAN_M_CAN_TCAN4X5X=m
|
||||
CONFIG_CAN_RCAR=m
|
||||
CONFIG_CAN_RCAR_CANFD=m
|
||||
CONFIG_CAN_SJA1000=m
|
||||
|
|
@ -1733,6 +1736,7 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
|||
#
|
||||
CONFIG_ARM_CCI=y
|
||||
# CONFIG_BRCMSTB_GISB_ARB is not set
|
||||
# CONFIG_MOXTET is not set
|
||||
# CONFIG_SIMPLE_PM_BUS is not set
|
||||
# CONFIG_VEXPRESS_CONFIG is not set
|
||||
# end of Bus devices
|
||||
|
|
@ -1777,6 +1781,8 @@ CONFIG_BLK_DEV_RAM_COUNT=1
|
|||
CONFIG_BLK_DEV_RAM_SIZE=4096
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
CONFIG_ATA_OVER_ETH=m
|
||||
CONFIG_VIRTIO_BLK=m
|
||||
# CONFIG_VIRTIO_BLK_SCSI is not set
|
||||
# CONFIG_BLK_DEV_RBD is not set
|
||||
|
||||
#
|
||||
|
|
@ -1911,6 +1917,7 @@ CONFIG_SCSI_LOWLEVEL=y
|
|||
# CONFIG_ISCSI_BOOT_SYSFS is not set
|
||||
# CONFIG_SCSI_UFSHCD is not set
|
||||
# CONFIG_SCSI_DEBUG is not set
|
||||
CONFIG_SCSI_VIRTIO=m
|
||||
# CONFIG_SCSI_DH is not set
|
||||
# end of SCSI device support
|
||||
|
||||
|
|
@ -1940,6 +1947,7 @@ CONFIG_DM_THIN_PROVISIONING=y
|
|||
# CONFIG_DM_CACHE is not set
|
||||
CONFIG_DM_WRITECACHE=m
|
||||
# CONFIG_DM_ERA is not set
|
||||
CONFIG_DM_CLONE=m
|
||||
CONFIG_DM_MIRROR=y
|
||||
# CONFIG_DM_LOG_USERSPACE is not set
|
||||
CONFIG_DM_RAID=y
|
||||
|
|
@ -1951,6 +1959,7 @@ CONFIG_DM_DUST=m
|
|||
# CONFIG_DM_UEVENT is not set
|
||||
# CONFIG_DM_FLAKEY is not set
|
||||
CONFIG_DM_VERITY=y
|
||||
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
|
||||
# CONFIG_DM_VERITY_FEC is not set
|
||||
# CONFIG_DM_SWITCH is not set
|
||||
# CONFIG_DM_LOG_WRITES is not set
|
||||
|
|
@ -1978,6 +1987,7 @@ CONFIG_TUN=y
|
|||
CONFIG_TAP=m
|
||||
# CONFIG_TUN_VNET_CROSS_LE is not set
|
||||
CONFIG_VETH=m
|
||||
CONFIG_VIRTIO_NET=m
|
||||
# CONFIG_NLMON is not set
|
||||
CONFIG_NET_VRF=m
|
||||
CONFIG_ATM_DRIVERS=y
|
||||
|
|
@ -2002,7 +2012,10 @@ CONFIG_NET_DSA_LOOP=m
|
|||
# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
|
||||
CONFIG_NET_DSA_MT7530=m
|
||||
CONFIG_NET_DSA_MV88E6060=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
|
||||
# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
|
||||
CONFIG_NET_DSA_MV88E6XXX=m
|
||||
CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
|
||||
# CONFIG_NET_DSA_MV88E6XXX_PTP is not set
|
||||
|
|
@ -2053,6 +2066,7 @@ CONFIG_MSCC_OCELOT_SWITCH_OCELOT=m
|
|||
CONFIG_NET_VENDOR_NI=y
|
||||
# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
|
||||
# CONFIG_ETHOC is not set
|
||||
CONFIG_NET_VENDOR_PENSANDO=y
|
||||
# CONFIG_NET_VENDOR_QUALCOMM is not set
|
||||
# CONFIG_NET_VENDOR_RENESAS is not set
|
||||
# CONFIG_NET_VENDOR_ROCKER is not set
|
||||
|
|
@ -2092,6 +2106,7 @@ CONFIG_LED_TRIGGER_PHY=y
|
|||
# MII PHY device drivers
|
||||
#
|
||||
# CONFIG_SFP is not set
|
||||
CONFIG_ADIN_PHY=m
|
||||
# CONFIG_AMD_PHY is not set
|
||||
# CONFIG_AQUANTIA_PHY is not set
|
||||
CONFIG_AX88796B_PHY=m
|
||||
|
|
@ -2426,6 +2441,7 @@ CONFIG_JOYSTICK_XPAD_FF=y
|
|||
CONFIG_JOYSTICK_XPAD_LEDS=y
|
||||
# CONFIG_JOYSTICK_PSXPAD_SPI is not set
|
||||
CONFIG_JOYSTICK_PXRC=m
|
||||
CONFIG_JOYSTICK_FSIA6B=m
|
||||
CONFIG_INPUT_TABLET=y
|
||||
# CONFIG_TABLET_USB_ACECAD is not set
|
||||
# CONFIG_TABLET_USB_AIPTEK is not set
|
||||
|
|
@ -2547,7 +2563,6 @@ CONFIG_INPUT_UINPUT=y
|
|||
# CONFIG_INPUT_ADXL34X is not set
|
||||
# CONFIG_INPUT_IMS_PCU is not set
|
||||
# CONFIG_INPUT_CMA3000 is not set
|
||||
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
|
||||
# CONFIG_INPUT_DRV260X_HAPTICS is not set
|
||||
# CONFIG_INPUT_DRV2665_HAPTICS is not set
|
||||
# CONFIG_INPUT_DRV2667_HAPTICS is not set
|
||||
|
|
@ -2619,6 +2634,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
|
|||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
# CONFIG_SERIAL_8250_EXTENDED is not set
|
||||
# CONFIG_SERIAL_8250_ASPEED_VUART is not set
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
# CONFIG_SERIAL_8250_EM is not set
|
||||
|
|
@ -2646,6 +2662,7 @@ CONFIG_SERIAL_SIFIVE=m
|
|||
# CONFIG_SERIAL_XILINX_PS_UART is not set
|
||||
# CONFIG_SERIAL_ARC is not set
|
||||
# CONFIG_SERIAL_FSL_LPUART is not set
|
||||
CONFIG_SERIAL_FSL_LINFLEXUART=m
|
||||
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
|
||||
# CONFIG_SERIAL_ST_ASC is not set
|
||||
# end of Serial drivers
|
||||
|
|
@ -2654,10 +2671,13 @@ CONFIG_SERIAL_MCTRL_GPIO=y
|
|||
CONFIG_SERIAL_DEV_BUS=y
|
||||
# CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set
|
||||
# CONFIG_TTY_PRINTK is not set
|
||||
CONFIG_HVC_DRIVER=y
|
||||
# CONFIG_HVC_DCC is not set
|
||||
CONFIG_VIRTIO_CONSOLE=m
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
|
||||
CONFIG_HW_RANDOM_VIRTIO=m
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
CONFIG_TCG_TPM=y
|
||||
CONFIG_HW_RANDOM_TPM=y
|
||||
|
|
@ -2673,6 +2693,8 @@ CONFIG_TCG_TIS_I2C_INFINEON=y
|
|||
# CONFIG_XILLYBUS is not set
|
||||
# end of Character devices
|
||||
|
||||
# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
|
|
@ -2891,6 +2913,7 @@ CONFIG_W1_CON=y
|
|||
# CONFIG_W1_MASTER_DS2482 is not set
|
||||
# CONFIG_W1_MASTER_DS1WM is not set
|
||||
CONFIG_W1_MASTER_GPIO=m
|
||||
CONFIG_W1_MASTER_SGI=m
|
||||
# end of 1-wire Bus Masters
|
||||
|
||||
#
|
||||
|
|
@ -2909,6 +2932,7 @@ CONFIG_W1_SLAVE_DS2431=m
|
|||
CONFIG_W1_SLAVE_DS2433=m
|
||||
# CONFIG_W1_SLAVE_DS2433_CRC is not set
|
||||
CONFIG_W1_SLAVE_DS2438=m
|
||||
CONFIG_W1_SLAVE_DS250X=m
|
||||
CONFIG_W1_SLAVE_DS2780=m
|
||||
CONFIG_W1_SLAVE_DS2781=m
|
||||
# CONFIG_W1_SLAVE_DS28E04 is not set
|
||||
|
|
@ -2989,6 +3013,7 @@ CONFIG_SENSORS_ADT7411=m
|
|||
CONFIG_SENSORS_ADT7462=m
|
||||
CONFIG_SENSORS_ADT7470=m
|
||||
CONFIG_SENSORS_ADT7475=m
|
||||
CONFIG_SENSORS_AS370=m
|
||||
CONFIG_SENSORS_ASC7621=m
|
||||
# CONFIG_SENSORS_ASPEED is not set
|
||||
CONFIG_SENSORS_ATXP1=m
|
||||
|
|
@ -3077,7 +3102,6 @@ CONFIG_SENSORS_SCH5636=m
|
|||
CONFIG_SENSORS_STTS751=m
|
||||
CONFIG_SENSORS_SMM665=m
|
||||
CONFIG_SENSORS_ADC128D818=m
|
||||
CONFIG_SENSORS_ADS1015=m
|
||||
CONFIG_SENSORS_ADS7828=m
|
||||
CONFIG_SENSORS_ADS7871=m
|
||||
CONFIG_SENSORS_AMC6821=m
|
||||
|
|
@ -3176,8 +3200,7 @@ CONFIG_MFD_CORE=y
|
|||
# CONFIG_MFD_BCM590XX is not set
|
||||
# CONFIG_MFD_BD9571MWV is not set
|
||||
# CONFIG_MFD_AXP20X_I2C is not set
|
||||
CONFIG_MFD_CROS_EC=y
|
||||
# CONFIG_MFD_CROS_EC_CHARDEV is not set
|
||||
CONFIG_MFD_CROS_EC_DEV=m
|
||||
CONFIG_MFD_MADERA=m
|
||||
CONFIG_MFD_MADERA_I2C=m
|
||||
# CONFIG_MFD_MADERA_SPI is not set
|
||||
|
|
@ -3319,6 +3342,7 @@ CONFIG_REGULATOR_RK808=y
|
|||
# CONFIG_REGULATOR_SLG51000 is not set
|
||||
# CONFIG_REGULATOR_STPMIC1 is not set
|
||||
# CONFIG_REGULATOR_SY8106A is not set
|
||||
CONFIG_REGULATOR_SY8824X=m
|
||||
# CONFIG_REGULATOR_TPS51632 is not set
|
||||
# CONFIG_REGULATOR_TPS62360 is not set
|
||||
# CONFIG_REGULATOR_TPS65023 is not set
|
||||
|
|
@ -3381,6 +3405,7 @@ CONFIG_MEDIA_CONTROLLER_DVB=y
|
|||
CONFIG_VIDEO_DEV=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
CONFIG_VIDEO_V4L2=y
|
||||
CONFIG_VIDEO_V4L2_I2C=y
|
||||
# CONFIG_VIDEO_ADV_DEBUG is not set
|
||||
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
|
||||
CONFIG_VIDEO_TUNER=m
|
||||
|
|
@ -3734,6 +3759,7 @@ CONFIG_VIDEO_OV5645=m
|
|||
CONFIG_VIDEO_OV5647=m
|
||||
CONFIG_VIDEO_OV6650=m
|
||||
CONFIG_VIDEO_OV5670=m
|
||||
CONFIG_VIDEO_OV5675=m
|
||||
CONFIG_VIDEO_OV5695=m
|
||||
CONFIG_VIDEO_OV7251=m
|
||||
CONFIG_VIDEO_OV772X=m
|
||||
|
|
@ -4057,6 +4083,7 @@ CONFIG_MALI_PLATFORM_DEVICETREE=y
|
|||
CONFIG_MALI_PWRSOFT_765=y
|
||||
CONFIG_MALI_KUTF=m
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_MIPI_DBI=m
|
||||
CONFIG_DRM_MIPI_DSI=y
|
||||
# CONFIG_DRM_DP_AUX_CHARDEV is not set
|
||||
CONFIG_DRM_DEBUG_MM=y
|
||||
|
|
@ -4068,6 +4095,7 @@ CONFIG_DRM_FBDEV_OVERALLOC=100
|
|||
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
|
||||
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
|
||||
# CONFIG_DRM_DP_CEC is not set
|
||||
CONFIG_DRM_TTM=m
|
||||
CONFIG_DRM_GEM_CMA_HELPER=y
|
||||
CONFIG_DRM_KMS_CMA_HELPER=y
|
||||
CONFIG_DRM_GEM_SHMEM_HELPER=y
|
||||
|
|
@ -4112,6 +4140,7 @@ CONFIG_DRM_UDL=y
|
|||
CONFIG_DRM_RCAR_LVDS=m
|
||||
# CONFIG_DRM_OMAP is not set
|
||||
# CONFIG_DRM_TILCDC is not set
|
||||
CONFIG_DRM_VIRTIO_GPU=m
|
||||
# CONFIG_DRM_FSL_DCU is not set
|
||||
# CONFIG_DRM_STM is not set
|
||||
CONFIG_DRM_PANEL=y
|
||||
|
|
@ -4129,12 +4158,16 @@ CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
|
|||
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
|
||||
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
|
||||
CONFIG_DRM_PANEL_LG_LB035Q02=m
|
||||
# CONFIG_DRM_PANEL_LG_LG4573 is not set
|
||||
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
|
||||
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
|
||||
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
|
||||
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
|
||||
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
|
||||
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
|
||||
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
|
||||
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
|
||||
# CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set
|
||||
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
|
||||
|
|
@ -4145,9 +4178,13 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
|
|||
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
|
||||
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
|
||||
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
|
||||
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
|
||||
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
|
||||
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
|
||||
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
|
||||
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
|
||||
CONFIG_DRM_PANEL_TPO_TPG110=m
|
||||
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
|
||||
# end of Display Panels
|
||||
|
|
@ -4185,8 +4222,7 @@ CONFIG_DRM_ETNAVIV=m
|
|||
CONFIG_DRM_ETNAVIV_THERMAL=y
|
||||
# CONFIG_DRM_ARCPGU is not set
|
||||
# CONFIG_DRM_MXSFB is not set
|
||||
CONFIG_DRM_TINYDRM=m
|
||||
CONFIG_TINYDRM_MIPI_DBI=m
|
||||
CONFIG_DRM_GM12U320=m
|
||||
# CONFIG_TINYDRM_HX8357D is not set
|
||||
# CONFIG_TINYDRM_ILI9225 is not set
|
||||
CONFIG_TINYDRM_ILI9341=m
|
||||
|
|
@ -4484,6 +4520,7 @@ CONFIG_SND_SOC_TDA7419=m
|
|||
CONFIG_SND_SOC_TS3A227E=m
|
||||
# CONFIG_SND_SOC_TSCS42XX is not set
|
||||
CONFIG_SND_SOC_TSCS454=m
|
||||
CONFIG_SND_SOC_UDA1334=m
|
||||
# CONFIG_SND_SOC_WM8510 is not set
|
||||
# CONFIG_SND_SOC_WM8523 is not set
|
||||
# CONFIG_SND_SOC_WM8524 is not set
|
||||
|
|
@ -4553,6 +4590,7 @@ CONFIG_HID_MACALLY=m
|
|||
CONFIG_HID_PRODIKEYS=m
|
||||
# CONFIG_HID_CMEDIA is not set
|
||||
CONFIG_HID_CP2112=m
|
||||
CONFIG_HID_CREATIVE_SB0540=m
|
||||
CONFIG_HID_CYPRESS=m
|
||||
CONFIG_HID_DRAGONRISE=m
|
||||
CONFIG_DRAGONRISE_FF=y
|
||||
|
|
@ -4660,6 +4698,9 @@ CONFIG_I2C_HID=y
|
|||
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_COMMON=y
|
||||
# CONFIG_USB_LED_TRIG is not set
|
||||
# CONFIG_USB_ULPI_BUS is not set
|
||||
CONFIG_USB_CONN_GPIO=m
|
||||
CONFIG_USB_ARCH_HAS_HCD=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
|
|
@ -4676,7 +4717,6 @@ CONFIG_USB_OTG=y
|
|||
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
|
||||
CONFIG_USB_AUTOSUSPEND_DELAY=2
|
||||
CONFIG_USB_MON=y
|
||||
# CONFIG_USB_WUSB_CBAF is not set
|
||||
|
||||
#
|
||||
# USB Host Controller Drivers
|
||||
|
|
@ -4741,6 +4781,9 @@ CONFIG_USBIP_VHCI_NR_HCS=1
|
|||
CONFIG_USBIP_HOST=m
|
||||
CONFIG_USBIP_VUDC=m
|
||||
# CONFIG_USBIP_DEBUG is not set
|
||||
CONFIG_USB_CDNS3=m
|
||||
# CONFIG_USB_CDNS3_GADGET is not set
|
||||
# CONFIG_USB_CDNS3_HOST is not set
|
||||
# CONFIG_USB_MUSB_HDRC is not set
|
||||
# CONFIG_USB_DWC3 is not set
|
||||
CONFIG_USB_DWC2=y
|
||||
|
|
@ -4925,9 +4968,6 @@ CONFIG_USB_G_HID=m
|
|||
# CONFIG_USB_G_WEBCAM is not set
|
||||
# CONFIG_TYPEC is not set
|
||||
CONFIG_USB_ROLE_SWITCH=m
|
||||
# CONFIG_USB_LED_TRIG is not set
|
||||
# CONFIG_USB_ULPI_BUS is not set
|
||||
# CONFIG_UWB is not set
|
||||
CONFIG_MMC=y
|
||||
CONFIG_PWRSEQ_EMMC=y
|
||||
CONFIG_PWRSEQ_SD8787=m
|
||||
|
|
@ -4945,6 +4985,7 @@ CONFIG_MMC_TEST=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
# CONFIG_MMC_SDHCI_OF_ARASAN is not set
|
||||
CONFIG_MMC_SDHCI_OF_ASPEED=m
|
||||
# CONFIG_MMC_SDHCI_OF_AT91 is not set
|
||||
CONFIG_MMC_SDHCI_OF_DWCMSHC=m
|
||||
CONFIG_MMC_SDHCI_CADENCE=m
|
||||
|
|
@ -5199,12 +5240,14 @@ CONFIG_DMA_ENGINE_RAID=y
|
|||
CONFIG_SYNC_FILE=y
|
||||
# CONFIG_SW_SYNC is not set
|
||||
# CONFIG_UDMABUF is not set
|
||||
CONFIG_DMABUF_SELFTESTS=m
|
||||
# end of DMABUF options
|
||||
|
||||
# CONFIG_AUXDISPLAY is not set
|
||||
# CONFIG_UIO is not set
|
||||
# CONFIG_VFIO is not set
|
||||
# CONFIG_VIRT_DRIVERS is not set
|
||||
CONFIG_VIRTIO=m
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
|
||||
#
|
||||
|
|
@ -5212,6 +5255,7 @@ CONFIG_SYNC_FILE=y
|
|||
#
|
||||
# end of Microsoft Hyper-V guest support
|
||||
|
||||
# CONFIG_GREYBUS is not set
|
||||
CONFIG_STAGING=y
|
||||
# CONFIG_PRISM2_USB is not set
|
||||
# CONFIG_COMEDI is not set
|
||||
|
|
@ -5287,7 +5331,6 @@ CONFIG_88EU_AP_MODE=y
|
|||
# end of Speakup console speech
|
||||
|
||||
CONFIG_STAGING_MEDIA=y
|
||||
# CONFIG_I2C_BCM2048 is not set
|
||||
|
||||
#
|
||||
# soc_camera sensor drivers
|
||||
|
|
@ -5337,8 +5380,6 @@ CONFIG_FB_TFT_UC1611=m
|
|||
CONFIG_FB_TFT_UC1701=m
|
||||
CONFIG_FB_TFT_UPD161704=m
|
||||
CONFIG_FB_TFT_WATTEROTT=m
|
||||
CONFIG_FB_FLEX=m
|
||||
CONFIG_FB_TFT_FBTFT_DEVICE=m
|
||||
# CONFIG_WILC1000_SDIO is not set
|
||||
# CONFIG_WILC1000_SPI is not set
|
||||
CONFIG_MOST=m
|
||||
|
|
@ -5350,7 +5391,6 @@ CONFIG_MOST=m
|
|||
# CONFIG_MOST_I2C is not set
|
||||
# CONFIG_MOST_USB is not set
|
||||
# CONFIG_KS7010 is not set
|
||||
# CONFIG_GREYBUS is not set
|
||||
# CONFIG_PI433 is not set
|
||||
|
||||
#
|
||||
|
|
@ -5359,16 +5399,32 @@ CONFIG_MOST=m
|
|||
# end of Gasket devices
|
||||
|
||||
# CONFIG_XIL_AXIS_FIFO is not set
|
||||
# CONFIG_EROFS_FS is not set
|
||||
CONFIG_FIELDBUS_DEV=m
|
||||
CONFIG_HMS_ANYBUSS_BUS=m
|
||||
CONFIG_ARCX_ANYBUS_CONTROLLER=m
|
||||
CONFIG_HMS_PROFINET=m
|
||||
# CONFIG_USB_WUSB_CBAF is not set
|
||||
# CONFIG_UWB is not set
|
||||
CONFIG_EXFAT_FS=m
|
||||
CONFIG_EXFAT_DONT_MOUNT_VFAT=y
|
||||
CONFIG_EXFAT_DISCARD=y
|
||||
# CONFIG_EXFAT_DELAYED_SYNC is not set
|
||||
# CONFIG_EXFAT_KERNEL_DEBUG is not set
|
||||
# CONFIG_EXFAT_DEBUG_MSG is not set
|
||||
CONFIG_EXFAT_DEFAULT_CODEPAGE=437
|
||||
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
|
||||
# CONFIG_GOLDFISH is not set
|
||||
CONFIG_MFD_CROS_EC=y
|
||||
CONFIG_CHROME_PLATFORMS=y
|
||||
CONFIG_CROS_EC=y
|
||||
# CONFIG_CROS_EC_I2C is not set
|
||||
# CONFIG_CROS_EC_SPI is not set
|
||||
CONFIG_CROS_EC_PROTO=y
|
||||
CONFIG_CROS_EC_CHARDEV=m
|
||||
CONFIG_CROS_EC_LIGHTBAR=m
|
||||
CONFIG_CROS_EC_VBC=m
|
||||
CONFIG_CROS_EC_DEBUGFS=m
|
||||
CONFIG_CROS_EC_SYSFS=m
|
||||
CONFIG_CROS_USBPD_LOGGER=m
|
||||
# CONFIG_MELLANOX_PLATFORM is not set
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
|
|
@ -5517,7 +5573,7 @@ CONFIG_IIO_BUFFER=y
|
|||
CONFIG_IIO_BUFFER_CB=m
|
||||
# CONFIG_IIO_BUFFER_HW_CONSUMER is not set
|
||||
CONFIG_IIO_KFIFO_BUF=y
|
||||
CONFIG_IIO_TRIGGERED_BUFFER=m
|
||||
CONFIG_IIO_TRIGGERED_BUFFER=y
|
||||
# CONFIG_IIO_CONFIGFS is not set
|
||||
CONFIG_IIO_TRIGGER=y
|
||||
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
|
||||
|
|
@ -5543,7 +5599,6 @@ CONFIG_ADXL345_SPI=m
|
|||
# CONFIG_DMARD09 is not set
|
||||
# CONFIG_DMARD10 is not set
|
||||
CONFIG_HID_SENSOR_ACCEL_3D=m
|
||||
# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set
|
||||
# CONFIG_IIO_ST_ACCEL_3AXIS is not set
|
||||
# CONFIG_KXSD9 is not set
|
||||
# CONFIG_KXCJK1013 is not set
|
||||
|
|
@ -5771,6 +5826,7 @@ CONFIG_SI7020=m
|
|||
# Inertial measurement units
|
||||
#
|
||||
# CONFIG_ADIS16400 is not set
|
||||
CONFIG_ADIS16460=m
|
||||
# CONFIG_ADIS16480 is not set
|
||||
# CONFIG_BMI160_I2C is not set
|
||||
# CONFIG_BMI160_SPI is not set
|
||||
|
|
@ -5780,6 +5836,9 @@ CONFIG_SI7020=m
|
|||
# CONFIG_IIO_ST_LSM6DSX is not set
|
||||
# end of Inertial measurement units
|
||||
|
||||
CONFIG_IIO_ADIS_LIB=m
|
||||
CONFIG_IIO_ADIS_LIB_BUFFER=y
|
||||
|
||||
#
|
||||
# Light sensors
|
||||
#
|
||||
|
|
@ -5806,6 +5865,7 @@ CONFIG_HID_SENSOR_PROX=m
|
|||
CONFIG_LV0104CS=m
|
||||
# CONFIG_MAX44000 is not set
|
||||
CONFIG_MAX44009=m
|
||||
CONFIG_NOA1305=m
|
||||
# CONFIG_OPT3001 is not set
|
||||
# CONFIG_PA12203001 is not set
|
||||
CONFIG_SI1133=m
|
||||
|
|
@ -5869,6 +5929,7 @@ CONFIG_IIO_SYSFS_TRIGGER=y
|
|||
#
|
||||
CONFIG_AD5272=m
|
||||
# CONFIG_DS1803 is not set
|
||||
CONFIG_MAX5432=m
|
||||
# CONFIG_MAX5481 is not set
|
||||
# CONFIG_MAX5487 is not set
|
||||
CONFIG_MCP4018=m
|
||||
|
|
@ -6104,6 +6165,7 @@ CONFIG_EXPORTFS=y
|
|||
CONFIG_FILE_LOCKING=y
|
||||
CONFIG_MANDATORY_FILE_LOCKING=y
|
||||
CONFIG_FS_ENCRYPTION=y
|
||||
# CONFIG_FS_VERITY is not set
|
||||
CONFIG_FSNOTIFY=y
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
|
|
@ -6120,6 +6182,7 @@ CONFIG_AUTOFS4_FS=y
|
|||
CONFIG_AUTOFS_FS=y
|
||||
CONFIG_FUSE_FS=m
|
||||
CONFIG_CUSE=m
|
||||
CONFIG_VIRTIO_FS=m
|
||||
CONFIG_OVERLAY_FS=m
|
||||
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
|
||||
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
|
||||
|
|
@ -6230,24 +6293,7 @@ CONFIG_PSTORE_CONSOLE=y
|
|||
CONFIG_PSTORE_RAM=y
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
CONFIG_AUFS_FS=m
|
||||
CONFIG_AUFS_BRANCH_MAX_127=y
|
||||
# CONFIG_AUFS_BRANCH_MAX_511 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_1023 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_32767 is not set
|
||||
CONFIG_AUFS_SBILIST=y
|
||||
# CONFIG_AUFS_HNOTIFY is not set
|
||||
# CONFIG_AUFS_EXPORT is not set
|
||||
# CONFIG_AUFS_XATTR is not set
|
||||
# CONFIG_AUFS_FHSM is not set
|
||||
# CONFIG_AUFS_RDU is not set
|
||||
# CONFIG_AUFS_DIRREN is not set
|
||||
# CONFIG_AUFS_SHWH is not set
|
||||
# CONFIG_AUFS_BR_RAMFS is not set
|
||||
# CONFIG_AUFS_BR_FUSE is not set
|
||||
CONFIG_AUFS_BR_HFSPLUS=y
|
||||
CONFIG_AUFS_BDEV_LOOP=y
|
||||
# CONFIG_AUFS_DEBUG is not set
|
||||
# CONFIG_EROFS_FS is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V2=y
|
||||
|
|
@ -6276,7 +6322,6 @@ CONFIG_NFSD_V4=y
|
|||
# CONFIG_NFSD_SCSILAYOUT is not set
|
||||
# CONFIG_NFSD_FLEXFILELAYOUT is not set
|
||||
CONFIG_NFSD_V4_SECURITY_LABEL=y
|
||||
CONFIG_NFSD_FAULT_INJECTION=y
|
||||
CONFIG_GRACE_PERIOD=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
|
|
@ -6387,6 +6432,7 @@ CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
|
|||
# CONFIG_SECURITY_LOADPIN is not set
|
||||
CONFIG_SECURITY_YAMA=y
|
||||
# CONFIG_SECURITY_SAFESETID is not set
|
||||
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
|
||||
CONFIG_INTEGRITY=y
|
||||
# CONFIG_INTEGRITY_SIGNATURE is not set
|
||||
CONFIG_INTEGRITY_AUDIT=y
|
||||
|
|
@ -6448,6 +6494,7 @@ CONFIG_CRYPTO_CRYPTD=m
|
|||
CONFIG_CRYPTO_AUTHENC=y
|
||||
CONFIG_CRYPTO_TEST=m
|
||||
CONFIG_CRYPTO_SIMD=m
|
||||
CONFIG_CRYPTO_ENGINE=m
|
||||
|
||||
#
|
||||
# Public-key cryptography
|
||||
|
|
@ -6465,10 +6512,7 @@ CONFIG_CRYPTO_CCM=y
|
|||
CONFIG_CRYPTO_GCM=y
|
||||
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
|
||||
CONFIG_CRYPTO_AEGIS128=m
|
||||
CONFIG_CRYPTO_AEGIS128L=m
|
||||
CONFIG_CRYPTO_AEGIS256=m
|
||||
CONFIG_CRYPTO_MORUS640=m
|
||||
CONFIG_CRYPTO_MORUS1280=m
|
||||
CONFIG_CRYPTO_AEGIS128_SIMD=y
|
||||
CONFIG_CRYPTO_SEQIV=y
|
||||
CONFIG_CRYPTO_ECHAINIV=y
|
||||
|
||||
|
|
@ -6487,6 +6531,7 @@ CONFIG_CRYPTO_XTS=y
|
|||
CONFIG_CRYPTO_KEYWRAP=m
|
||||
CONFIG_CRYPTO_NHPOLY1305=m
|
||||
# CONFIG_CRYPTO_ADIANTUM is not set
|
||||
CONFIG_CRYPTO_ESSIV=y
|
||||
|
||||
#
|
||||
# Hash modes
|
||||
|
|
@ -6513,6 +6558,7 @@ CONFIG_CRYPTO_RMD160=m
|
|||
CONFIG_CRYPTO_RMD256=m
|
||||
CONFIG_CRYPTO_RMD320=m
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_LIB_SHA256=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
CONFIG_CRYPTO_SHA3=m
|
||||
|
|
@ -6524,6 +6570,7 @@ CONFIG_CRYPTO_WP512=m
|
|||
#
|
||||
# Ciphers
|
||||
#
|
||||
CONFIG_CRYPTO_LIB_AES=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
CONFIG_CRYPTO_AES_TI=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
|
|
@ -6535,6 +6582,7 @@ CONFIG_CRYPTO_CAMELLIA=m
|
|||
CONFIG_CRYPTO_CAST_COMMON=m
|
||||
CONFIG_CRYPTO_CAST5=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_LIB_DES=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_FCRYPT=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
|
|
@ -6578,6 +6626,8 @@ CONFIG_CRYPTO_HW=y
|
|||
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
|
||||
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
|
||||
CONFIG_CRYPTO_DEV_ROCKCHIP=m
|
||||
CONFIG_CRYPTO_DEV_VIRTIO=m
|
||||
CONFIG_CRYPTO_DEV_SAFEXCEL=m
|
||||
CONFIG_CRYPTO_DEV_CCREE=m
|
||||
CONFIG_ASYMMETRIC_KEY_TYPE=y
|
||||
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
|
||||
|
|
@ -6698,7 +6748,6 @@ CONFIG_LRU_CACHE=m
|
|||
CONFIG_CLZ_TAB=y
|
||||
# CONFIG_IRQ_POLL is not set
|
||||
CONFIG_MPILIB=y
|
||||
CONFIG_DIMLIB=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_OID_REGISTRY=y
|
||||
CONFIG_FONT_SUPPORT=y
|
||||
|
|
@ -6735,10 +6784,9 @@ CONFIG_ENABLE_MUST_CHECK=y
|
|||
CONFIG_FRAME_WARN=1024
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_READABLE_ASM is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_INSTALL is not set
|
||||
# CONFIG_OPTIMIZE_INLINING is not set
|
||||
CONFIG_OPTIMIZE_INLINING=y
|
||||
# CONFIG_DEBUG_SECTION_MISMATCH is not set
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
CONFIG_ARCH_WANT_FRAME_POINTERS=y
|
||||
|
|
|
|||
1
config/kernel/linux-rockchip-dev.config
Symbolic link
1
config/kernel/linux-rockchip-dev.config
Symbolic link
|
|
@ -0,0 +1 @@
|
|||
linux-rockchip-current.config
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 5.3.13 Kernel Configuration
|
||||
# Linux/arm 5.4.2 Kernel Configuration
|
||||
#
|
||||
|
||||
#
|
||||
|
|
@ -11,6 +11,7 @@ CONFIG_GCC_VERSION=80300
|
|||
CONFIG_CLANG_VERSION=0
|
||||
CONFIG_CC_CAN_LINK=y
|
||||
CONFIG_CC_HAS_ASM_GOTO=y
|
||||
CONFIG_CC_HAS_ASM_INLINE=y
|
||||
CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_BUILDTIME_EXTABLE_SORT=y
|
||||
|
|
@ -263,19 +264,13 @@ CONFIG_ARCH_MULTIPLATFORM=y
|
|||
# CONFIG_ARCH_EBSA110 is not set
|
||||
# CONFIG_ARCH_EP93XX is not set
|
||||
# CONFIG_ARCH_FOOTBRIDGE is not set
|
||||
# CONFIG_ARCH_IOP13XX is not set
|
||||
# CONFIG_ARCH_IOP32X is not set
|
||||
# CONFIG_ARCH_IOP33X is not set
|
||||
# CONFIG_ARCH_IXP4XX is not set
|
||||
# CONFIG_ARCH_DOVE is not set
|
||||
# CONFIG_ARCH_KS8695 is not set
|
||||
# CONFIG_ARCH_W90X900 is not set
|
||||
# CONFIG_ARCH_LPC32XX is not set
|
||||
# CONFIG_ARCH_PXA is not set
|
||||
# CONFIG_ARCH_RPC is not set
|
||||
# CONFIG_ARCH_SA1100 is not set
|
||||
# CONFIG_ARCH_S3C24XX is not set
|
||||
# CONFIG_ARCH_DAVINCI is not set
|
||||
# CONFIG_ARCH_OMAP1 is not set
|
||||
|
||||
#
|
||||
|
|
@ -294,6 +289,7 @@ CONFIG_ARCH_MULTI_V6_V7=y
|
|||
# CONFIG_ARCH_ACTIONS is not set
|
||||
# CONFIG_ARCH_ALPINE is not set
|
||||
# CONFIG_ARCH_ARTPEC is not set
|
||||
# CONFIG_ARCH_ASPEED is not set
|
||||
# CONFIG_ARCH_AT91 is not set
|
||||
# CONFIG_ARCH_BCM is not set
|
||||
# CONFIG_ARCH_BERLIN is not set
|
||||
|
|
@ -516,6 +512,7 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
|||
#
|
||||
CONFIG_CPUFREQ_DT=m
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m
|
||||
CONFIG_ARM_BIG_LITTLE_CPUFREQ=m
|
||||
# CONFIG_QORIQ_CPUFREQ is not set
|
||||
# end of CPU Frequency scaling
|
||||
|
|
@ -534,6 +531,7 @@ CONFIG_DT_IDLE_STATES=y
|
|||
# ARM CPU Idle Drivers
|
||||
#
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
CONFIG_ARM_PSCI_CPUIDLE=y
|
||||
# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
|
||||
# end of ARM CPU Idle Drivers
|
||||
# end of CPU Idle
|
||||
|
|
@ -657,6 +655,7 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
|
|||
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
|
||||
CONFIG_HAVE_EXIT_THREAD=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=8
|
||||
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
CONFIG_OLD_SIGACTION=y
|
||||
|
|
@ -693,6 +692,8 @@ CONFIG_MODULE_UNLOAD=y
|
|||
# CONFIG_MODULE_SRCVERSION_ALL is not set
|
||||
# CONFIG_MODULE_SIG is not set
|
||||
# CONFIG_MODULE_COMPRESS is not set
|
||||
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_TRIM_UNUSED_KSYMS is not set
|
||||
CONFIG_MODULES_TREE_LOOKUP=y
|
||||
CONFIG_BLOCK=y
|
||||
|
|
@ -706,6 +707,7 @@ CONFIG_BLK_DEV_THROTTLING=y
|
|||
# CONFIG_BLK_CMDLINE_PARSER is not set
|
||||
CONFIG_BLK_WBT=y
|
||||
# CONFIG_BLK_CGROUP_IOLATENCY is not set
|
||||
# CONFIG_BLK_CGROUP_IOCOST is not set
|
||||
CONFIG_BLK_WBT_MQ=y
|
||||
# CONFIG_BLK_DEBUG_FS is not set
|
||||
# CONFIG_BLK_SED_OPAL is not set
|
||||
|
|
@ -1328,9 +1330,7 @@ CONFIG_NET_DSA_TAG_GSWIP=m
|
|||
CONFIG_NET_DSA_TAG_DSA=m
|
||||
CONFIG_NET_DSA_TAG_EDSA=m
|
||||
CONFIG_NET_DSA_TAG_MTK=m
|
||||
CONFIG_NET_DSA_TAG_KSZ_COMMON=m
|
||||
CONFIG_NET_DSA_TAG_KSZ=m
|
||||
CONFIG_NET_DSA_TAG_KSZ9477=m
|
||||
CONFIG_NET_DSA_TAG_QCA=m
|
||||
CONFIG_NET_DSA_TAG_LAN9303=m
|
||||
CONFIG_NET_DSA_TAG_SJA1105=m
|
||||
|
|
@ -1450,6 +1450,7 @@ CONFIG_NET_ACT_SKBMOD=m
|
|||
# CONFIG_NET_ACT_IFE is not set
|
||||
CONFIG_NET_ACT_TUNNEL_KEY=m
|
||||
# CONFIG_NET_ACT_CT is not set
|
||||
# CONFIG_NET_TC_SKB_EXT is not set
|
||||
CONFIG_NET_SCH_FIFO=y
|
||||
CONFIG_DCB=y
|
||||
CONFIG_DNS_RESOLVER=y
|
||||
|
|
@ -1523,6 +1524,7 @@ CONFIG_CAN=m
|
|||
CONFIG_CAN_RAW=m
|
||||
CONFIG_CAN_BCM=m
|
||||
CONFIG_CAN_GW=m
|
||||
CONFIG_CAN_J1939=m
|
||||
|
||||
#
|
||||
# CAN Device Drivers
|
||||
|
|
@ -1543,6 +1545,8 @@ CONFIG_CAN_CC770_ISA=m
|
|||
CONFIG_CAN_CC770_PLATFORM=m
|
||||
# CONFIG_CAN_IFI_CANFD is not set
|
||||
CONFIG_CAN_M_CAN=m
|
||||
CONFIG_CAN_M_CAN_PLATFORM=m
|
||||
CONFIG_CAN_M_CAN_TCAN4X5X=m
|
||||
CONFIG_CAN_RCAR=m
|
||||
CONFIG_CAN_RCAR_CANFD=m
|
||||
CONFIG_CAN_SJA1000=m
|
||||
|
|
@ -1767,6 +1771,7 @@ CONFIG_REGMAP_SPI=y
|
|||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGMAP_IRQ=y
|
||||
CONFIG_REGMAP_SCCB=m
|
||||
CONFIG_REGMAP_I3C=m
|
||||
CONFIG_DMA_SHARED_BUFFER=y
|
||||
# CONFIG_DMA_FENCE_TRACE is not set
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
|
|
@ -1779,6 +1784,7 @@ CONFIG_ARM_CCI=y
|
|||
CONFIG_ARM_CCI400_COMMON=y
|
||||
CONFIG_ARM_CCI400_PORT_CTRL=y
|
||||
# CONFIG_BRCMSTB_GISB_ARB is not set
|
||||
# CONFIG_MOXTET is not set
|
||||
# CONFIG_SIMPLE_PM_BUS is not set
|
||||
CONFIG_SUN50I_DE2_BUS=y
|
||||
CONFIG_SUNXI_RSB=y
|
||||
|
|
@ -1793,13 +1799,13 @@ CONFIG_GNSS_SIRF_SERIAL=m
|
|||
# CONFIG_GNSS_UBX_SERIAL is not set
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_MTD_TESTS is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
|
||||
#
|
||||
# Partition parsers
|
||||
#
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
# CONFIG_MTD_AFS_PARTS is not set
|
||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
||||
# end of Partition parsers
|
||||
|
|
@ -1846,7 +1852,6 @@ CONFIG_MTD_CFI_I2=y
|
|||
# Self-contained MTD device drivers
|
||||
#
|
||||
# CONFIG_MTD_DATAFLASH is not set
|
||||
CONFIG_MTD_M25P80=y
|
||||
# CONFIG_MTD_MCHP23K256 is not set
|
||||
# CONFIG_MTD_SST25L is not set
|
||||
# CONFIG_MTD_SLRAM is not set
|
||||
|
|
@ -1873,6 +1878,7 @@ CONFIG_MTD_RAW_NAND=m
|
|||
# CONFIG_MTD_NAND_DENALI_DT is not set
|
||||
# CONFIG_MTD_NAND_BRCMNAND is not set
|
||||
CONFIG_MTD_NAND_SUNXI=m
|
||||
CONFIG_MTD_NAND_MXIC=m
|
||||
CONFIG_MTD_NAND_GPIO=m
|
||||
CONFIG_MTD_NAND_PLATFORM=m
|
||||
|
||||
|
|
@ -2144,6 +2150,7 @@ CONFIG_DM_CACHE=m
|
|||
CONFIG_DM_CACHE_SMQ=m
|
||||
CONFIG_DM_WRITECACHE=m
|
||||
# CONFIG_DM_ERA is not set
|
||||
CONFIG_DM_CLONE=m
|
||||
# CONFIG_DM_MIRROR is not set
|
||||
CONFIG_DM_RAID=m
|
||||
# CONFIG_DM_ZERO is not set
|
||||
|
|
@ -2155,6 +2162,7 @@ CONFIG_DM_DUST=m
|
|||
CONFIG_DM_UEVENT=y
|
||||
CONFIG_DM_FLAKEY=m
|
||||
CONFIG_DM_VERITY=m
|
||||
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
|
||||
# CONFIG_DM_VERITY_FEC is not set
|
||||
CONFIG_DM_SWITCH=m
|
||||
CONFIG_DM_LOG_WRITES=m
|
||||
|
|
@ -2214,12 +2222,16 @@ CONFIG_NET_DSA_MT7530=m
|
|||
CONFIG_NET_DSA_MV88E6060=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
|
||||
CONFIG_NET_DSA_MV88E6XXX=m
|
||||
CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
|
||||
CONFIG_NET_DSA_MV88E6XXX_PTP=y
|
||||
CONFIG_NET_DSA_SJA1105=m
|
||||
# CONFIG_NET_DSA_SJA1105_PTP is not set
|
||||
# CONFIG_NET_DSA_SJA1105_TAS is not set
|
||||
CONFIG_NET_DSA_QCA8K=m
|
||||
CONFIG_NET_DSA_REALTEK_SMI=m
|
||||
CONFIG_NET_DSA_SMSC_LAN9303=m
|
||||
|
|
@ -2278,6 +2290,7 @@ CONFIG_NET_VENDOR_NETRONOME=y
|
|||
CONFIG_NET_VENDOR_NI=y
|
||||
CONFIG_NI_XGE_MANAGEMENT_ENET=m
|
||||
# CONFIG_ETHOC is not set
|
||||
CONFIG_NET_VENDOR_PENSANDO=y
|
||||
CONFIG_NET_VENDOR_QUALCOMM=y
|
||||
# CONFIG_QCA7000_SPI is not set
|
||||
# CONFIG_QCA7000_UART is not set
|
||||
|
|
@ -2324,6 +2337,7 @@ CONFIG_LED_TRIGGER_PHY=y
|
|||
# MII PHY device drivers
|
||||
#
|
||||
# CONFIG_SFP is not set
|
||||
CONFIG_ADIN_PHY=m
|
||||
CONFIG_AMD_PHY=m
|
||||
CONFIG_AQUANTIA_PHY=m
|
||||
CONFIG_AX88796B_PHY=m
|
||||
|
|
@ -2753,7 +2767,6 @@ CONFIG_INPUT_AXP20X_PEK=y
|
|||
# CONFIG_INPUT_ADXL34X is not set
|
||||
# CONFIG_INPUT_IMS_PCU is not set
|
||||
# CONFIG_INPUT_CMA3000 is not set
|
||||
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
|
||||
# CONFIG_INPUT_DRV260X_HAPTICS is not set
|
||||
# CONFIG_INPUT_DRV2665_HAPTICS is not set
|
||||
# CONFIG_INPUT_DRV2667_HAPTICS is not set
|
||||
|
|
@ -2824,6 +2837,7 @@ CONFIG_SERIAL_8250_NR_UARTS=8
|
|||
CONFIG_SERIAL_8250_RUNTIME_UARTS=8
|
||||
# CONFIG_SERIAL_8250_EXTENDED is not set
|
||||
# CONFIG_SERIAL_8250_ASPEED_VUART is not set
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
# CONFIG_SERIAL_8250_EM is not set
|
||||
|
|
@ -2853,6 +2867,7 @@ CONFIG_SERIAL_SC16IS7XX_SPI=y
|
|||
# CONFIG_SERIAL_XILINX_PS_UART is not set
|
||||
# CONFIG_SERIAL_ARC is not set
|
||||
# CONFIG_SERIAL_FSL_LPUART is not set
|
||||
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
|
||||
CONFIG_SERIAL_CONEXANT_DIGICOLOR=m
|
||||
# CONFIG_SERIAL_ST_ASC is not set
|
||||
# end of Serial drivers
|
||||
|
|
@ -2873,6 +2888,8 @@ CONFIG_HW_RANDOM_OPTEE=m
|
|||
# CONFIG_XILLYBUS is not set
|
||||
# end of Character devices
|
||||
|
||||
# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
|
|
@ -3115,6 +3132,7 @@ CONFIG_W1=m
|
|||
# CONFIG_W1_MASTER_DS2482 is not set
|
||||
# CONFIG_W1_MASTER_DS1WM is not set
|
||||
CONFIG_W1_MASTER_GPIO=m
|
||||
CONFIG_W1_MASTER_SGI=m
|
||||
# end of 1-wire Bus Masters
|
||||
|
||||
#
|
||||
|
|
@ -3133,6 +3151,7 @@ CONFIG_W1_SLAVE_DS2431=m
|
|||
CONFIG_W1_SLAVE_DS2433=m
|
||||
# CONFIG_W1_SLAVE_DS2433_CRC is not set
|
||||
# CONFIG_W1_SLAVE_DS2438 is not set
|
||||
CONFIG_W1_SLAVE_DS250X=m
|
||||
# CONFIG_W1_SLAVE_DS2780 is not set
|
||||
# CONFIG_W1_SLAVE_DS2781 is not set
|
||||
# CONFIG_W1_SLAVE_DS28E04 is not set
|
||||
|
|
@ -3217,6 +3236,7 @@ CONFIG_SENSORS_ADT7411=m
|
|||
CONFIG_SENSORS_ADT7462=m
|
||||
CONFIG_SENSORS_ADT7470=m
|
||||
CONFIG_SENSORS_ADT7475=m
|
||||
CONFIG_SENSORS_AS370=m
|
||||
CONFIG_SENSORS_ASC7621=m
|
||||
# CONFIG_SENSORS_ASPEED is not set
|
||||
CONFIG_SENSORS_ATXP1=m
|
||||
|
|
@ -3306,7 +3326,6 @@ CONFIG_SENSORS_SCH5636=m
|
|||
CONFIG_SENSORS_STTS751=m
|
||||
CONFIG_SENSORS_SMM665=m
|
||||
CONFIG_SENSORS_ADC128D818=m
|
||||
CONFIG_SENSORS_ADS1015=m
|
||||
CONFIG_SENSORS_ADS7828=m
|
||||
CONFIG_SENSORS_ADS7871=m
|
||||
CONFIG_SENSORS_AMC6821=m
|
||||
|
|
@ -3418,7 +3437,6 @@ CONFIG_MFD_SUN4I_GPADC=m
|
|||
CONFIG_MFD_AXP20X=y
|
||||
CONFIG_MFD_AXP20X_I2C=y
|
||||
CONFIG_MFD_AXP20X_RSB=y
|
||||
# CONFIG_MFD_CROS_EC is not set
|
||||
CONFIG_MFD_MADERA=m
|
||||
# CONFIG_MFD_MADERA_I2C is not set
|
||||
# CONFIG_MFD_MADERA_SPI is not set
|
||||
|
|
@ -3524,6 +3542,7 @@ CONFIG_REGULATOR=y
|
|||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
|
||||
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
|
||||
CONFIG_REGULATOR_USERSPACE_CONSUMER_OF=m
|
||||
# CONFIG_REGULATOR_88PG86X is not set
|
||||
# CONFIG_REGULATOR_ACT8865 is not set
|
||||
# CONFIG_REGULATOR_AD5398 is not set
|
||||
|
|
@ -3561,6 +3580,7 @@ CONFIG_REGULATOR_PWM=m
|
|||
# CONFIG_REGULATOR_SLG51000 is not set
|
||||
CONFIG_REGULATOR_STPMIC1=m
|
||||
CONFIG_REGULATOR_SY8106A=m
|
||||
CONFIG_REGULATOR_SY8824X=m
|
||||
# CONFIG_REGULATOR_TPS51632 is not set
|
||||
# CONFIG_REGULATOR_TPS62360 is not set
|
||||
# CONFIG_REGULATOR_TPS65023 is not set
|
||||
|
|
@ -3568,6 +3588,7 @@ CONFIG_REGULATOR_SY8106A=m
|
|||
# CONFIG_REGULATOR_TPS65132 is not set
|
||||
# CONFIG_REGULATOR_TPS6524X is not set
|
||||
# CONFIG_REGULATOR_VCTRL is not set
|
||||
# CONFIG_REGULATOR_TP65185X is not set
|
||||
CONFIG_CEC_CORE=y
|
||||
CONFIG_CEC_NOTIFIER=y
|
||||
CONFIG_CEC_PIN=y
|
||||
|
|
@ -3626,6 +3647,7 @@ CONFIG_MEDIA_CONTROLLER_DVB=y
|
|||
CONFIG_VIDEO_DEV=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
CONFIG_VIDEO_V4L2=y
|
||||
CONFIG_VIDEO_V4L2_I2C=y
|
||||
# CONFIG_VIDEO_ADV_DEBUG is not set
|
||||
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
|
||||
CONFIG_VIDEO_TUNER=m
|
||||
|
|
@ -3809,6 +3831,7 @@ CONFIG_V4L_PLATFORM_DRIVERS=y
|
|||
CONFIG_VIDEO_ASPEED=m
|
||||
# CONFIG_VIDEO_MUX is not set
|
||||
# CONFIG_VIDEO_XILINX is not set
|
||||
CONFIG_VIDEO_SUN4I_CSI=m
|
||||
CONFIG_VIDEO_SUN6I_CSI=y
|
||||
CONFIG_V4L_MEM2MEM_DRIVERS=y
|
||||
# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
|
||||
|
|
@ -3975,6 +3998,7 @@ CONFIG_VIDEO_OV5645=m
|
|||
CONFIG_VIDEO_OV5647=m
|
||||
# CONFIG_VIDEO_OV6650 is not set
|
||||
# CONFIG_VIDEO_OV5670 is not set
|
||||
CONFIG_VIDEO_OV5675=m
|
||||
CONFIG_VIDEO_OV5695=m
|
||||
CONFIG_VIDEO_OV7251=m
|
||||
CONFIG_VIDEO_OV772X=m
|
||||
|
|
@ -4279,6 +4303,7 @@ CONFIG_DVB_DUMMY_FE=m
|
|||
#
|
||||
# CONFIG_IMX_IPUV3_CORE is not set
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_MIPI_DBI=m
|
||||
CONFIG_DRM_MIPI_DSI=y
|
||||
# CONFIG_DRM_DP_AUX_CHARDEV is not set
|
||||
# CONFIG_DRM_DEBUG_MM is not set
|
||||
|
|
@ -4351,12 +4376,16 @@ CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
|
|||
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
|
||||
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
|
||||
CONFIG_DRM_PANEL_LG_LB035Q02=m
|
||||
# CONFIG_DRM_PANEL_LG_LG4573 is not set
|
||||
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
|
||||
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
|
||||
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
|
||||
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
|
||||
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
|
||||
# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
|
||||
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
|
||||
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
|
||||
CONFIG_DRM_PANEL_ROCKTECH_JH057N00900=m
|
||||
CONFIG_DRM_PANEL_RONBO_RB070D30=m
|
||||
|
|
@ -4367,9 +4396,13 @@ CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
|
|||
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
|
||||
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
|
||||
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
|
||||
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
||||
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
|
||||
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
|
||||
CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
|
||||
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
|
||||
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
|
||||
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
|
||||
CONFIG_DRM_PANEL_TPO_TPG110=m
|
||||
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
|
||||
# end of Display Panels
|
||||
|
|
@ -4380,6 +4413,7 @@ CONFIG_DRM_PANEL_BRIDGE=y
|
|||
#
|
||||
# Display Interface Bridges
|
||||
#
|
||||
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
|
||||
# CONFIG_DRM_CDNS_DSI is not set
|
||||
# CONFIG_DRM_DUMB_VGA_DAC is not set
|
||||
# CONFIG_DRM_LVDS_ENCODER is not set
|
||||
|
|
@ -4395,7 +4429,6 @@ CONFIG_DRM_TOSHIBA_TC358764=m
|
|||
# CONFIG_DRM_TI_TFP410 is not set
|
||||
CONFIG_DRM_TI_SN65DSI86=m
|
||||
CONFIG_DRM_ANALOGIX_DP_I2C=m
|
||||
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
|
||||
CONFIG_DRM_ANALOGIX_ANX6345=m
|
||||
# CONFIG_DRM_I2C_ADV7511 is not set
|
||||
CONFIG_DRM_DW_HDMI=y
|
||||
|
|
@ -4409,8 +4442,7 @@ CONFIG_DRM_ETNAVIV=m
|
|||
CONFIG_DRM_ETNAVIV_THERMAL=y
|
||||
# CONFIG_DRM_ARCPGU is not set
|
||||
# CONFIG_DRM_MXSFB is not set
|
||||
CONFIG_DRM_TINYDRM=m
|
||||
CONFIG_TINYDRM_MIPI_DBI=m
|
||||
CONFIG_DRM_GM12U320=m
|
||||
CONFIG_TINYDRM_HX8357D=m
|
||||
# CONFIG_TINYDRM_ILI9225 is not set
|
||||
CONFIG_TINYDRM_ILI9341=m
|
||||
|
|
@ -4451,6 +4483,7 @@ CONFIG_FB_BACKLIGHT=m
|
|||
#
|
||||
# CONFIG_FB_OPENCORES is not set
|
||||
# CONFIG_FB_S1D13XXX is not set
|
||||
# CONFIG_FB_SUN5I_EINK is not set
|
||||
# CONFIG_FB_SMSCUFX is not set
|
||||
# CONFIG_FB_UDL is not set
|
||||
# CONFIG_FB_IBM_GXT4500 is not set
|
||||
|
|
@ -4725,6 +4758,7 @@ CONFIG_SND_SOC_TDA7419=m
|
|||
# CONFIG_SND_SOC_TS3A227E is not set
|
||||
# CONFIG_SND_SOC_TSCS42XX is not set
|
||||
# CONFIG_SND_SOC_TSCS454 is not set
|
||||
CONFIG_SND_SOC_UDA1334=m
|
||||
# CONFIG_SND_SOC_WM8510 is not set
|
||||
# CONFIG_SND_SOC_WM8523 is not set
|
||||
# CONFIG_SND_SOC_WM8524 is not set
|
||||
|
|
@ -4794,6 +4828,7 @@ CONFIG_HID_MACALLY=m
|
|||
CONFIG_HID_PRODIKEYS=m
|
||||
# CONFIG_HID_CMEDIA is not set
|
||||
CONFIG_HID_CP2112=m
|
||||
CONFIG_HID_CREATIVE_SB0540=m
|
||||
CONFIG_HID_CYPRESS=m
|
||||
CONFIG_HID_DRAGONRISE=m
|
||||
CONFIG_DRAGONRISE_FF=y
|
||||
|
|
@ -4901,6 +4936,9 @@ CONFIG_I2C_HID=m
|
|||
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_COMMON=y
|
||||
# CONFIG_USB_LED_TRIG is not set
|
||||
CONFIG_USB_ULPI_BUS=m
|
||||
CONFIG_USB_CONN_GPIO=m
|
||||
CONFIG_USB_ARCH_HAS_HCD=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
|
|
@ -4917,7 +4955,6 @@ CONFIG_USB_OTG=y
|
|||
CONFIG_USB_LEDS_TRIGGER_USBPORT=y
|
||||
CONFIG_USB_AUTOSUSPEND_DELAY=2
|
||||
CONFIG_USB_MON=m
|
||||
# CONFIG_USB_WUSB_CBAF is not set
|
||||
|
||||
#
|
||||
# USB Host Controller Drivers
|
||||
|
|
@ -4987,6 +5024,7 @@ CONFIG_USBIP_VHCI_NR_HCS=1
|
|||
CONFIG_USBIP_HOST=m
|
||||
CONFIG_USBIP_VUDC=m
|
||||
# CONFIG_USBIP_DEBUG is not set
|
||||
# CONFIG_USB_CDNS3 is not set
|
||||
CONFIG_USB_MUSB_HDRC=y
|
||||
# CONFIG_USB_MUSB_HOST is not set
|
||||
# CONFIG_USB_MUSB_GADGET is not set
|
||||
|
|
@ -5194,9 +5232,6 @@ CONFIG_USB_G_HID=m
|
|||
CONFIG_USB_G_WEBCAM=m
|
||||
# CONFIG_TYPEC is not set
|
||||
CONFIG_USB_ROLE_SWITCH=m
|
||||
# CONFIG_USB_LED_TRIG is not set
|
||||
CONFIG_USB_ULPI_BUS=m
|
||||
# CONFIG_UWB is not set
|
||||
CONFIG_MMC=y
|
||||
CONFIG_PWRSEQ_EMMC=m
|
||||
CONFIG_PWRSEQ_SD8787=m
|
||||
|
|
@ -5454,6 +5489,7 @@ CONFIG_DMA_ENGINE_RAID=y
|
|||
CONFIG_SYNC_FILE=y
|
||||
# CONFIG_SW_SYNC is not set
|
||||
# CONFIG_UDMABUF is not set
|
||||
CONFIG_DMABUF_SELFTESTS=m
|
||||
# end of DMABUF options
|
||||
|
||||
# CONFIG_AUXDISPLAY is not set
|
||||
|
|
@ -5472,6 +5508,7 @@ CONFIG_VIRTIO_MENU=y
|
|||
#
|
||||
# end of Microsoft Hyper-V guest support
|
||||
|
||||
# CONFIG_GREYBUS is not set
|
||||
CONFIG_STAGING=y
|
||||
# CONFIG_PRISM2_USB is not set
|
||||
# CONFIG_COMEDI is not set
|
||||
|
|
@ -5547,7 +5584,6 @@ CONFIG_AD9834=m
|
|||
# end of Speakup console speech
|
||||
|
||||
CONFIG_STAGING_MEDIA=y
|
||||
CONFIG_I2C_BCM2048=m
|
||||
CONFIG_VIDEO_SUNXI=y
|
||||
|
||||
#
|
||||
|
|
@ -5596,8 +5632,6 @@ CONFIG_FB_TFT_UC1611=m
|
|||
CONFIG_FB_TFT_UC1701=m
|
||||
CONFIG_FB_TFT_UPD161704=m
|
||||
CONFIG_FB_TFT_WATTEROTT=m
|
||||
CONFIG_FB_FLEX=m
|
||||
CONFIG_FB_TFT_FBTFT_DEVICE=m
|
||||
# CONFIG_WILC1000_SDIO is not set
|
||||
# CONFIG_WILC1000_SPI is not set
|
||||
CONFIG_MOST=m
|
||||
|
|
@ -5609,7 +5643,6 @@ CONFIG_MOST=m
|
|||
# CONFIG_MOST_I2C is not set
|
||||
# CONFIG_MOST_USB is not set
|
||||
# CONFIG_KS7010 is not set
|
||||
# CONFIG_GREYBUS is not set
|
||||
# CONFIG_PI433 is not set
|
||||
|
||||
#
|
||||
|
|
@ -5618,20 +5651,22 @@ CONFIG_MOST=m
|
|||
# end of Gasket devices
|
||||
|
||||
CONFIG_XIL_AXIS_FIFO=m
|
||||
CONFIG_EROFS_FS=m
|
||||
# CONFIG_EROFS_FS_DEBUG is not set
|
||||
CONFIG_EROFS_FS_XATTR=y
|
||||
CONFIG_EROFS_FS_POSIX_ACL=y
|
||||
# CONFIG_EROFS_FS_SECURITY is not set
|
||||
# CONFIG_EROFS_FS_USE_VM_MAP_RAM is not set
|
||||
# CONFIG_EROFS_FAULT_INJECTION is not set
|
||||
CONFIG_EROFS_FS_IO_MAX_RETRIES=5
|
||||
# CONFIG_EROFS_FS_ZIP is not set
|
||||
CONFIG_FIELDBUS_DEV=m
|
||||
CONFIG_HMS_ANYBUSS_BUS=m
|
||||
CONFIG_ARCX_ANYBUS_CONTROLLER=m
|
||||
CONFIG_HMS_PROFINET=m
|
||||
# CONFIG_USB_WUSB_CBAF is not set
|
||||
# CONFIG_UWB is not set
|
||||
CONFIG_EXFAT_FS=m
|
||||
CONFIG_EXFAT_DONT_MOUNT_VFAT=y
|
||||
CONFIG_EXFAT_DISCARD=y
|
||||
# CONFIG_EXFAT_DELAYED_SYNC is not set
|
||||
# CONFIG_EXFAT_KERNEL_DEBUG is not set
|
||||
# CONFIG_EXFAT_DEBUG_MSG is not set
|
||||
CONFIG_EXFAT_DEFAULT_CODEPAGE=437
|
||||
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
|
||||
# CONFIG_GOLDFISH is not set
|
||||
# CONFIG_MFD_CROS_EC is not set
|
||||
# CONFIG_CHROME_PLATFORMS is not set
|
||||
# CONFIG_MELLANOX_PLATFORM is not set
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
|
|
@ -5830,7 +5865,6 @@ CONFIG_ADXL372_I2C=m
|
|||
# CONFIG_DMARD09 is not set
|
||||
# CONFIG_DMARD10 is not set
|
||||
# CONFIG_HID_SENSOR_ACCEL_3D is not set
|
||||
# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set
|
||||
# CONFIG_IIO_ST_ACCEL_3AXIS is not set
|
||||
# CONFIG_KXSD9 is not set
|
||||
# CONFIG_KXCJK1013 is not set
|
||||
|
|
@ -6058,6 +6092,7 @@ CONFIG_SI7020=m
|
|||
# Inertial measurement units
|
||||
#
|
||||
# CONFIG_ADIS16400 is not set
|
||||
CONFIG_ADIS16460=m
|
||||
# CONFIG_ADIS16480 is not set
|
||||
# CONFIG_BMI160_I2C is not set
|
||||
# CONFIG_BMI160_SPI is not set
|
||||
|
|
@ -6067,8 +6102,12 @@ CONFIG_SI7020=m
|
|||
CONFIG_IIO_ST_LSM6DSX=m
|
||||
CONFIG_IIO_ST_LSM6DSX_I2C=m
|
||||
CONFIG_IIO_ST_LSM6DSX_SPI=m
|
||||
CONFIG_IIO_ST_LSM6DSX_I3C=m
|
||||
# end of Inertial measurement units
|
||||
|
||||
CONFIG_IIO_ADIS_LIB=m
|
||||
CONFIG_IIO_ADIS_LIB_BUFFER=y
|
||||
|
||||
#
|
||||
# Light sensors
|
||||
#
|
||||
|
|
@ -6095,6 +6134,7 @@ CONFIG_CM3605=m
|
|||
# CONFIG_LV0104CS is not set
|
||||
# CONFIG_MAX44000 is not set
|
||||
CONFIG_MAX44009=m
|
||||
CONFIG_NOA1305=m
|
||||
# CONFIG_OPT3001 is not set
|
||||
# CONFIG_PA12203001 is not set
|
||||
CONFIG_SI1133=m
|
||||
|
|
@ -6159,6 +6199,7 @@ CONFIG_IIO_SYSFS_TRIGGER=m
|
|||
#
|
||||
# CONFIG_AD5272 is not set
|
||||
# CONFIG_DS1803 is not set
|
||||
CONFIG_MAX5432=m
|
||||
CONFIG_MAX5481=m
|
||||
# CONFIG_MAX5487 is not set
|
||||
# CONFIG_MCP4018 is not set
|
||||
|
|
@ -6414,6 +6455,7 @@ CONFIG_EXPORTFS=y
|
|||
CONFIG_FILE_LOCKING=y
|
||||
CONFIG_MANDATORY_FILE_LOCKING=y
|
||||
CONFIG_FS_ENCRYPTION=y
|
||||
# CONFIG_FS_VERITY is not set
|
||||
CONFIG_FSNOTIFY=y
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
|
|
@ -6430,6 +6472,7 @@ CONFIG_AUTOFS4_FS=y
|
|||
CONFIG_AUTOFS_FS=y
|
||||
CONFIG_FUSE_FS=m
|
||||
CONFIG_CUSE=m
|
||||
# CONFIG_VIRTIO_FS is not set
|
||||
CONFIG_OVERLAY_FS=m
|
||||
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
|
||||
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
|
||||
|
|
@ -6542,24 +6585,12 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
|
|||
# CONFIG_PSTORE is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
CONFIG_AUFS_FS=m
|
||||
CONFIG_AUFS_BRANCH_MAX_127=y
|
||||
# CONFIG_AUFS_BRANCH_MAX_511 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_1023 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_32767 is not set
|
||||
CONFIG_AUFS_SBILIST=y
|
||||
# CONFIG_AUFS_HNOTIFY is not set
|
||||
# CONFIG_AUFS_EXPORT is not set
|
||||
# CONFIG_AUFS_XATTR is not set
|
||||
# CONFIG_AUFS_FHSM is not set
|
||||
# CONFIG_AUFS_RDU is not set
|
||||
# CONFIG_AUFS_DIRREN is not set
|
||||
# CONFIG_AUFS_SHWH is not set
|
||||
# CONFIG_AUFS_BR_RAMFS is not set
|
||||
# CONFIG_AUFS_BR_FUSE is not set
|
||||
CONFIG_AUFS_BR_HFSPLUS=y
|
||||
CONFIG_AUFS_BDEV_LOOP=y
|
||||
# CONFIG_AUFS_DEBUG is not set
|
||||
CONFIG_EROFS_FS=m
|
||||
# CONFIG_EROFS_FS_DEBUG is not set
|
||||
CONFIG_EROFS_FS_XATTR=y
|
||||
CONFIG_EROFS_FS_POSIX_ACL=y
|
||||
# CONFIG_EROFS_FS_SECURITY is not set
|
||||
# CONFIG_EROFS_FS_ZIP is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V2=y
|
||||
|
|
@ -6585,7 +6616,6 @@ CONFIG_NFSD_V4=y
|
|||
# CONFIG_NFSD_BLOCKLAYOUT is not set
|
||||
# CONFIG_NFSD_SCSILAYOUT is not set
|
||||
# CONFIG_NFSD_FLEXFILELAYOUT is not set
|
||||
# CONFIG_NFSD_FAULT_INJECTION is not set
|
||||
CONFIG_GRACE_PERIOD=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
|
|
@ -6757,10 +6787,6 @@ CONFIG_CRYPTO_CCM=m
|
|||
CONFIG_CRYPTO_GCM=m
|
||||
CONFIG_CRYPTO_CHACHA20POLY1305=m
|
||||
# CONFIG_CRYPTO_AEGIS128 is not set
|
||||
CONFIG_CRYPTO_AEGIS128L=m
|
||||
CONFIG_CRYPTO_AEGIS256=m
|
||||
CONFIG_CRYPTO_MORUS640=m
|
||||
CONFIG_CRYPTO_MORUS1280=m
|
||||
CONFIG_CRYPTO_SEQIV=y
|
||||
CONFIG_CRYPTO_ECHAINIV=m
|
||||
|
||||
|
|
@ -6779,6 +6805,7 @@ CONFIG_CRYPTO_XTS=y
|
|||
CONFIG_CRYPTO_KEYWRAP=m
|
||||
CONFIG_CRYPTO_NHPOLY1305=m
|
||||
CONFIG_CRYPTO_ADIANTUM=m
|
||||
CONFIG_CRYPTO_ESSIV=m
|
||||
|
||||
#
|
||||
# Hash modes
|
||||
|
|
@ -6805,8 +6832,9 @@ CONFIG_CRYPTO_RMD160=m
|
|||
CONFIG_CRYPTO_RMD256=m
|
||||
CONFIG_CRYPTO_RMD320=m
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_LIB_SHA256=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
CONFIG_CRYPTO_SHA3=m
|
||||
CONFIG_CRYPTO_SM3=m
|
||||
CONFIG_CRYPTO_STREEBOG=m
|
||||
|
|
@ -6816,6 +6844,7 @@ CONFIG_CRYPTO_WP512=m
|
|||
#
|
||||
# Ciphers
|
||||
#
|
||||
CONFIG_CRYPTO_LIB_AES=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
CONFIG_CRYPTO_AES_TI=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
|
|
@ -6827,6 +6856,7 @@ CONFIG_CRYPTO_CAMELLIA=m
|
|||
CONFIG_CRYPTO_CAST_COMMON=m
|
||||
CONFIG_CRYPTO_CAST5=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_LIB_DES=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_FCRYPT=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
|
|
@ -6871,6 +6901,7 @@ CONFIG_CRYPTO_HW=y
|
|||
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
|
||||
CONFIG_CRYPTO_DEV_SUN4I_SS=m
|
||||
# CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG is not set
|
||||
CONFIG_CRYPTO_DEV_SAFEXCEL=m
|
||||
CONFIG_CRYPTO_DEV_CCREE=m
|
||||
CONFIG_ASYMMETRIC_KEY_TYPE=y
|
||||
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
|
||||
|
|
@ -6988,7 +7019,6 @@ CONFIG_LRU_CACHE=m
|
|||
CONFIG_CLZ_TAB=y
|
||||
# CONFIG_IRQ_POLL is not set
|
||||
CONFIG_MPILIB=y
|
||||
CONFIG_DIMLIB=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_OID_REGISTRY=y
|
||||
CONFIG_FONT_SUPPORT=y
|
||||
|
|
@ -7024,10 +7054,9 @@ CONFIG_ENABLE_MUST_CHECK=y
|
|||
CONFIG_FRAME_WARN=1024
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_READABLE_ASM is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_INSTALL is not set
|
||||
# CONFIG_OPTIMIZE_INLINING is not set
|
||||
CONFIG_OPTIMIZE_INLINING=y
|
||||
# CONFIG_DEBUG_SECTION_MISMATCH is not set
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
1
config/kernel/linux-sunxi-dev.config
Symbolic link
1
config/kernel/linux-sunxi-dev.config
Symbolic link
|
|
@ -0,0 +1 @@
|
|||
linux-sunxi-current.config
|
||||
|
|
@ -1,16 +1,17 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm64 5.3.0-rc8 Kernel Configuration
|
||||
# Linux/arm64 5.4.2 Kernel Configuration
|
||||
#
|
||||
|
||||
#
|
||||
# Compiler: aarch64-linux-gnu-gcc (Linaro GCC 7.4-2019.02) 7.4.1 20181213 [linaro-7.4-2019.02 revision 56ec6f6b99cc167ff0c2f8e1a2eed33b1edc85d4]
|
||||
# Compiler: aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0
|
||||
#
|
||||
CONFIG_CC_IS_GCC=y
|
||||
CONFIG_GCC_VERSION=70401
|
||||
CONFIG_GCC_VERSION=80300
|
||||
CONFIG_CLANG_VERSION=0
|
||||
CONFIG_CC_CAN_LINK=y
|
||||
CONFIG_CC_HAS_ASM_GOTO=y
|
||||
CONFIG_CC_HAS_ASM_INLINE=y
|
||||
CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_BUILDTIME_EXTABLE_SORT=y
|
||||
|
|
@ -316,6 +317,7 @@ CONFIG_CAVIUM_ERRATUM_23144=y
|
|||
# CONFIG_CAVIUM_ERRATUM_23154 is not set
|
||||
# CONFIG_CAVIUM_ERRATUM_27456 is not set
|
||||
# CONFIG_CAVIUM_ERRATUM_30115 is not set
|
||||
CONFIG_CAVIUM_TX2_ERRATUM_219=y
|
||||
# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
|
||||
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
|
||||
# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
|
||||
|
|
@ -375,6 +377,7 @@ CONFIG_HARDEN_EL2_VECTORS=y
|
|||
CONFIG_ARM64_SSBD=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
# CONFIG_ARM64_SW_TTBR0_PAN is not set
|
||||
CONFIG_ARM64_TAGGED_ADDR_ABI=y
|
||||
CONFIG_COMPAT=y
|
||||
CONFIG_KUSER_HELPERS=y
|
||||
CONFIG_ARMV8_DEPRECATED=y
|
||||
|
|
@ -464,6 +467,7 @@ CONFIG_DT_IDLE_STATES=y
|
|||
# ARM CPU Idle Drivers
|
||||
#
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
CONFIG_ARM_PSCI_CPUIDLE=y
|
||||
# end of ARM CPU Idle Drivers
|
||||
# end of CPU Idle
|
||||
|
||||
|
|
@ -492,6 +496,7 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
|||
#
|
||||
CONFIG_CPUFREQ_DT=m
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
|
||||
CONFIG_ARM_SCPI_CPUFREQ=m
|
||||
# CONFIG_ARM_SCMI_CPUFREQ is not set
|
||||
# CONFIG_QORIQ_CPUFREQ is not set
|
||||
|
|
@ -548,6 +553,7 @@ CONFIG_JUMP_LABEL=y
|
|||
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
|
||||
CONFIG_HAVE_KPROBES=y
|
||||
CONFIG_HAVE_KRETPROBES=y
|
||||
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
|
||||
CONFIG_HAVE_NMI=y
|
||||
CONFIG_HAVE_ARCH_TRACEHOOK=y
|
||||
CONFIG_HAVE_DMA_CONTIGUOUS=y
|
||||
|
|
@ -558,6 +564,7 @@ CONFIG_ARCH_HAS_KEEPINITRD=y
|
|||
CONFIG_ARCH_HAS_SET_MEMORY=y
|
||||
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
|
||||
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
|
||||
CONFIG_HAVE_ASM_MODVERSIONS=y
|
||||
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
|
||||
CONFIG_HAVE_RSEQ=y
|
||||
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
|
||||
|
|
@ -592,6 +599,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
|
|||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
|
||||
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
CONFIG_COMPAT_OLD_SIGACTION=y
|
||||
|
|
@ -629,6 +637,8 @@ CONFIG_MODULE_UNLOAD=y
|
|||
# CONFIG_MODULE_SRCVERSION_ALL is not set
|
||||
# CONFIG_MODULE_SIG is not set
|
||||
# CONFIG_MODULE_COMPRESS is not set
|
||||
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_TRIM_UNUSED_KSYMS is not set
|
||||
CONFIG_MODULES_TREE_LOOKUP=y
|
||||
CONFIG_BLOCK=y
|
||||
|
|
@ -642,6 +652,7 @@ CONFIG_BLK_DEV_THROTTLING=y
|
|||
# CONFIG_BLK_CMDLINE_PARSER is not set
|
||||
CONFIG_BLK_WBT=y
|
||||
# CONFIG_BLK_CGROUP_IOLATENCY is not set
|
||||
# CONFIG_BLK_CGROUP_IOCOST is not set
|
||||
CONFIG_BLK_WBT_MQ=y
|
||||
# CONFIG_BLK_DEBUG_FS is not set
|
||||
# CONFIG_BLK_SED_OPAL is not set
|
||||
|
|
@ -794,6 +805,7 @@ CONFIG_ARCH_HAS_PTE_DEVMAP=y
|
|||
CONFIG_FRAME_VECTOR=y
|
||||
CONFIG_PERCPU_STATS=y
|
||||
# CONFIG_GUP_BENCHMARK is not set
|
||||
# CONFIG_READ_ONLY_THP_FOR_FS is not set
|
||||
CONFIG_ARCH_HAS_PTE_SPECIAL=y
|
||||
# end of Memory Management options
|
||||
|
||||
|
|
@ -1294,9 +1306,7 @@ CONFIG_NET_DSA_TAG_GSWIP=m
|
|||
CONFIG_NET_DSA_TAG_DSA=m
|
||||
CONFIG_NET_DSA_TAG_EDSA=m
|
||||
CONFIG_NET_DSA_TAG_MTK=m
|
||||
CONFIG_NET_DSA_TAG_KSZ_COMMON=m
|
||||
CONFIG_NET_DSA_TAG_KSZ=m
|
||||
CONFIG_NET_DSA_TAG_KSZ9477=m
|
||||
CONFIG_NET_DSA_TAG_QCA=m
|
||||
CONFIG_NET_DSA_TAG_LAN9303=m
|
||||
CONFIG_NET_DSA_TAG_SJA1105=m
|
||||
|
|
@ -1462,6 +1472,7 @@ CONFIG_CAN=m
|
|||
CONFIG_CAN_RAW=m
|
||||
CONFIG_CAN_BCM=m
|
||||
CONFIG_CAN_GW=m
|
||||
CONFIG_CAN_J1939=m
|
||||
|
||||
#
|
||||
# CAN Device Drivers
|
||||
|
|
@ -1703,6 +1714,7 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
|||
#
|
||||
CONFIG_ARM_CCI=y
|
||||
# CONFIG_BRCMSTB_GISB_ARB is not set
|
||||
# CONFIG_MOXTET is not set
|
||||
# CONFIG_SIMPLE_PM_BUS is not set
|
||||
CONFIG_SUN50I_DE2_BUS=y
|
||||
CONFIG_SUNXI_RSB=y
|
||||
|
|
@ -1717,13 +1729,13 @@ CONFIG_GNSS_SIRF_SERIAL=m
|
|||
CONFIG_GNSS_UBX_SERIAL=m
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_MTD_TESTS is not set
|
||||
# CONFIG_MTD_CMDLINE_PARTS is not set
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
|
||||
#
|
||||
# Partition parsers
|
||||
#
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
# CONFIG_MTD_CMDLINE_PARTS is not set
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
# CONFIG_MTD_AFS_PARTS is not set
|
||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
||||
# end of Partition parsers
|
||||
|
|
@ -1776,7 +1788,6 @@ CONFIG_MTD_CFI_UTIL=y
|
|||
# Self-contained MTD device drivers
|
||||
#
|
||||
# CONFIG_MTD_DATAFLASH is not set
|
||||
CONFIG_MTD_M25P80=y
|
||||
# CONFIG_MTD_MCHP23K256 is not set
|
||||
# CONFIG_MTD_SST25L is not set
|
||||
# CONFIG_MTD_SLRAM is not set
|
||||
|
|
@ -1804,6 +1815,7 @@ CONFIG_MTD_NAND_DENALI=m
|
|||
CONFIG_MTD_NAND_DENALI_DT=m
|
||||
CONFIG_MTD_NAND_BRCMNAND=m
|
||||
CONFIG_MTD_NAND_SUNXI=m
|
||||
CONFIG_MTD_NAND_MXIC=m
|
||||
CONFIG_MTD_NAND_GPIO=m
|
||||
CONFIG_MTD_NAND_PLATFORM=m
|
||||
|
||||
|
|
@ -1855,6 +1867,7 @@ CONFIG_BLK_DEV_LOOP=y
|
|||
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_BLK_DEV_DRBD=m
|
||||
# CONFIG_DRBD_FAULT_INJECTION is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
CONFIG_BLK_DEV_RAM=m
|
||||
CONFIG_BLK_DEV_RAM_COUNT=8
|
||||
|
|
@ -2042,6 +2055,7 @@ CONFIG_DM_CACHE=m
|
|||
CONFIG_DM_CACHE_SMQ=m
|
||||
CONFIG_DM_WRITECACHE=m
|
||||
CONFIG_DM_ERA=m
|
||||
CONFIG_DM_CLONE=m
|
||||
CONFIG_DM_MIRROR=m
|
||||
CONFIG_DM_LOG_USERSPACE=m
|
||||
CONFIG_DM_RAID=m
|
||||
|
|
@ -2107,10 +2121,14 @@ CONFIG_NET_DSA_LANTIQ_GSWIP=m
|
|||
# CONFIG_NET_DSA_MV88E6060 is not set
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
|
||||
CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
|
||||
# CONFIG_NET_DSA_MV88E6XXX is not set
|
||||
CONFIG_NET_DSA_SJA1105=m
|
||||
# CONFIG_NET_DSA_SJA1105_PTP is not set
|
||||
# CONFIG_NET_DSA_SJA1105_TAS is not set
|
||||
# CONFIG_NET_DSA_QCA8K is not set
|
||||
CONFIG_NET_DSA_REALTEK_SMI=m
|
||||
# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
|
||||
|
|
@ -2168,6 +2186,7 @@ CONFIG_NET_VENDOR_NETRONOME=y
|
|||
CONFIG_NET_VENDOR_NI=y
|
||||
CONFIG_NI_XGE_MANAGEMENT_ENET=m
|
||||
# CONFIG_ETHOC is not set
|
||||
CONFIG_NET_VENDOR_PENSANDO=y
|
||||
CONFIG_NET_VENDOR_QUALCOMM=y
|
||||
CONFIG_QCA7000=m
|
||||
# CONFIG_QCA7000_SPI is not set
|
||||
|
|
@ -2215,6 +2234,7 @@ CONFIG_LED_TRIGGER_PHY=y
|
|||
# MII PHY device drivers
|
||||
#
|
||||
# CONFIG_SFP is not set
|
||||
CONFIG_ADIN_PHY=m
|
||||
CONFIG_AMD_PHY=m
|
||||
CONFIG_AQUANTIA_PHY=m
|
||||
CONFIG_AX88796B_PHY=m
|
||||
|
|
@ -2425,11 +2445,11 @@ CONFIG_RTW88=m
|
|||
# CONFIG_WLAN_VENDOR_ST is not set
|
||||
# CONFIG_WLAN_VENDOR_TI is not set
|
||||
CONFIG_RTL8822BU=m
|
||||
CONFIG_RTL8188EU=m
|
||||
CONFIG_RTL8188EUS=m
|
||||
# CONFIG_WLAN_VENDOR_XRADIO is not set
|
||||
CONFIG_RTL8812AU=m
|
||||
# CONFIG_WLAN_VENDOR_ZYDAS is not set
|
||||
CONFIG_WLAN_VENDOR_QUANTENNA=y
|
||||
# CONFIG_WLAN_VENDOR_XRADIO is not set
|
||||
# CONFIG_MAC80211_HWSIM is not set
|
||||
CONFIG_USB_NET_RNDIS_WLAN=m
|
||||
CONFIG_VIRT_WIFI=m
|
||||
|
|
@ -2639,7 +2659,6 @@ CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
|
|||
# CONFIG_INPUT_ADXL34X is not set
|
||||
# CONFIG_INPUT_IMS_PCU is not set
|
||||
# CONFIG_INPUT_CMA3000 is not set
|
||||
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
|
||||
# CONFIG_INPUT_DRV260X_HAPTICS is not set
|
||||
# CONFIG_INPUT_DRV2665_HAPTICS is not set
|
||||
# CONFIG_INPUT_DRV2667_HAPTICS is not set
|
||||
|
|
@ -2709,6 +2728,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
|
|||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
# CONFIG_SERIAL_8250_EXTENDED is not set
|
||||
# CONFIG_SERIAL_8250_ASPEED_VUART is not set
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
# CONFIG_SERIAL_8250_RT288X is not set
|
||||
|
|
@ -2739,6 +2759,7 @@ CONFIG_SERIAL_XILINX_PS_UART=y
|
|||
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
|
||||
# CONFIG_SERIAL_ARC is not set
|
||||
# CONFIG_SERIAL_FSL_LPUART is not set
|
||||
CONFIG_SERIAL_FSL_LINFLEXUART=m
|
||||
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
|
||||
# end of Serial drivers
|
||||
|
||||
|
|
@ -2756,6 +2777,8 @@ CONFIG_VIRTIO_CONSOLE=y
|
|||
# CONFIG_XILLYBUS is not set
|
||||
# end of Character devices
|
||||
|
||||
# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
|
|
@ -3005,6 +3028,7 @@ CONFIG_W1_MASTER_DS2490=m
|
|||
CONFIG_W1_MASTER_DS2482=m
|
||||
CONFIG_W1_MASTER_DS1WM=m
|
||||
CONFIG_W1_MASTER_GPIO=m
|
||||
CONFIG_W1_MASTER_SGI=m
|
||||
# end of 1-wire Bus Masters
|
||||
|
||||
#
|
||||
|
|
@ -3023,6 +3047,7 @@ CONFIG_W1_SLAVE_DS2431=m
|
|||
CONFIG_W1_SLAVE_DS2433=m
|
||||
# CONFIG_W1_SLAVE_DS2433_CRC is not set
|
||||
# CONFIG_W1_SLAVE_DS2438 is not set
|
||||
CONFIG_W1_SLAVE_DS250X=m
|
||||
CONFIG_W1_SLAVE_DS2780=m
|
||||
CONFIG_W1_SLAVE_DS2781=m
|
||||
CONFIG_W1_SLAVE_DS28E04=m
|
||||
|
|
@ -3107,6 +3132,7 @@ CONFIG_SENSORS_ADT7411=m
|
|||
CONFIG_SENSORS_ADT7462=m
|
||||
CONFIG_SENSORS_ADT7470=m
|
||||
CONFIG_SENSORS_ADT7475=m
|
||||
CONFIG_SENSORS_AS370=m
|
||||
CONFIG_SENSORS_ASC7621=m
|
||||
CONFIG_SENSORS_ARM_SCMI=m
|
||||
CONFIG_SENSORS_ARM_SCPI=m
|
||||
|
|
@ -3183,6 +3209,7 @@ CONFIG_PMBUS=m
|
|||
CONFIG_SENSORS_PMBUS=m
|
||||
CONFIG_SENSORS_ADM1275=m
|
||||
CONFIG_SENSORS_IBM_CFFPS=m
|
||||
CONFIG_SENSORS_INSPUR_IPSPS=m
|
||||
CONFIG_SENSORS_IR35221=m
|
||||
CONFIG_SENSORS_IR38064=m
|
||||
# CONFIG_SENSORS_IRPS5401 is not set
|
||||
|
|
@ -3219,7 +3246,6 @@ CONFIG_SENSORS_SCH5636=m
|
|||
CONFIG_SENSORS_STTS751=m
|
||||
CONFIG_SENSORS_SMM665=m
|
||||
CONFIG_SENSORS_ADC128D818=m
|
||||
CONFIG_SENSORS_ADS1015=m
|
||||
CONFIG_SENSORS_ADS7828=m
|
||||
CONFIG_SENSORS_ADS7871=m
|
||||
CONFIG_SENSORS_AMC6821=m
|
||||
|
|
@ -3332,7 +3358,6 @@ CONFIG_MFD_BD9571MWV=m
|
|||
CONFIG_MFD_AXP20X=y
|
||||
CONFIG_MFD_AXP20X_I2C=y
|
||||
CONFIG_MFD_AXP20X_RSB=y
|
||||
# CONFIG_MFD_CROS_EC is not set
|
||||
CONFIG_MFD_MADERA=m
|
||||
CONFIG_MFD_MADERA_I2C=m
|
||||
# CONFIG_MFD_MADERA_SPI is not set
|
||||
|
|
@ -3433,6 +3458,7 @@ CONFIG_REGULATOR=y
|
|||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
|
||||
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
|
||||
CONFIG_REGULATOR_USERSPACE_CONSUMER_OF=m
|
||||
CONFIG_REGULATOR_88PG86X=m
|
||||
# CONFIG_REGULATOR_ACT8865 is not set
|
||||
# CONFIG_REGULATOR_AD5398 is not set
|
||||
|
|
@ -3473,6 +3499,7 @@ CONFIG_REGULATOR_S2MPS11=y
|
|||
# CONFIG_REGULATOR_S5M8767 is not set
|
||||
# CONFIG_REGULATOR_SLG51000 is not set
|
||||
CONFIG_REGULATOR_SY8106A=m
|
||||
CONFIG_REGULATOR_SY8824X=m
|
||||
# CONFIG_REGULATOR_TPS51632 is not set
|
||||
# CONFIG_REGULATOR_TPS62360 is not set
|
||||
# CONFIG_REGULATOR_TPS65023 is not set
|
||||
|
|
@ -3480,6 +3507,7 @@ CONFIG_REGULATOR_SY8106A=m
|
|||
# CONFIG_REGULATOR_TPS65132 is not set
|
||||
# CONFIG_REGULATOR_TPS6524X is not set
|
||||
# CONFIG_REGULATOR_VCTRL is not set
|
||||
CONFIG_REGULATOR_TP65185X=m
|
||||
CONFIG_CEC_CORE=y
|
||||
CONFIG_CEC_NOTIFIER=y
|
||||
CONFIG_CEC_PIN=y
|
||||
|
|
@ -3535,6 +3563,7 @@ CONFIG_MEDIA_CONTROLLER_DVB=y
|
|||
CONFIG_VIDEO_DEV=m
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
CONFIG_VIDEO_V4L2=m
|
||||
CONFIG_VIDEO_V4L2_I2C=y
|
||||
# CONFIG_VIDEO_ADV_DEBUG is not set
|
||||
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
|
||||
CONFIG_VIDEO_TUNER=m
|
||||
|
|
@ -3718,6 +3747,7 @@ CONFIG_VIDEO_MUX=m
|
|||
CONFIG_VIDEO_XILINX=m
|
||||
CONFIG_VIDEO_XILINX_TPG=m
|
||||
CONFIG_VIDEO_XILINX_VTC=m
|
||||
CONFIG_VIDEO_SUN4I_CSI=m
|
||||
CONFIG_VIDEO_SUN6I_CSI=m
|
||||
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
|
||||
# CONFIG_V4L_TEST_DRIVERS is not set
|
||||
|
|
@ -3771,9 +3801,14 @@ CONFIG_SMS_SIANO_RC=y
|
|||
# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
|
||||
#
|
||||
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
|
||||
CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y
|
||||
CONFIG_MEDIA_ATTACH=y
|
||||
CONFIG_VIDEO_IR_I2C=m
|
||||
|
||||
#
|
||||
# I2C drivers hidden by 'Autoselect ancillary drivers'
|
||||
#
|
||||
|
||||
#
|
||||
# Audio decoders, processors and mixers
|
||||
#
|
||||
|
|
@ -3830,6 +3865,10 @@ CONFIG_VIDEO_MT9V011=m
|
|||
# Miscellaneous helper chips
|
||||
#
|
||||
|
||||
#
|
||||
# SPI drivers hidden by 'Autoselect ancillary drivers'
|
||||
#
|
||||
|
||||
#
|
||||
# Media SPI Adapters
|
||||
#
|
||||
|
|
@ -3837,6 +3876,10 @@ CONFIG_CXD2880_SPI_DRV=m
|
|||
# end of Media SPI Adapters
|
||||
|
||||
CONFIG_MEDIA_TUNER=m
|
||||
|
||||
#
|
||||
# Tuner drivers hidden by 'Autoselect ancillary drivers'
|
||||
#
|
||||
CONFIG_MEDIA_TUNER_SIMPLE=m
|
||||
CONFIG_MEDIA_TUNER_TDA18250=m
|
||||
CONFIG_MEDIA_TUNER_TDA8290=m
|
||||
|
|
@ -3871,6 +3914,10 @@ CONFIG_MEDIA_TUNER_IT913X=m
|
|||
CONFIG_MEDIA_TUNER_R820T=m
|
||||
CONFIG_MEDIA_TUNER_QM1D1C0042=m
|
||||
|
||||
#
|
||||
# DVB Frontend drivers hidden by 'Autoselect ancillary drivers'
|
||||
#
|
||||
|
||||
#
|
||||
# Multistandard (satellite) frontends
|
||||
#
|
||||
|
|
@ -4006,6 +4053,7 @@ CONFIG_DVB_SP2=m
|
|||
# Graphics support
|
||||
#
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_MIPI_DBI=m
|
||||
CONFIG_DRM_MIPI_DSI=y
|
||||
# CONFIG_DRM_DP_AUX_CHARDEV is not set
|
||||
# CONFIG_DRM_DEBUG_MM is not set
|
||||
|
|
@ -4072,12 +4120,16 @@ CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
|
|||
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
|
||||
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
|
||||
CONFIG_DRM_PANEL_LG_LB035Q02=m
|
||||
# CONFIG_DRM_PANEL_LG_LG4573 is not set
|
||||
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
|
||||
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
|
||||
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
|
||||
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
|
||||
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
|
||||
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
|
||||
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
|
||||
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
|
||||
CONFIG_DRM_PANEL_ROCKTECH_JH057N00900=m
|
||||
CONFIG_DRM_PANEL_RONBO_RB070D30=m
|
||||
|
|
@ -4088,9 +4140,13 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
|
|||
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
|
||||
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
|
||||
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
|
||||
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
|
||||
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
|
||||
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
|
||||
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
|
||||
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
|
||||
CONFIG_DRM_PANEL_TPO_TPG110=m
|
||||
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
|
||||
# end of Display Panels
|
||||
|
|
@ -4101,6 +4157,7 @@ CONFIG_DRM_PANEL_BRIDGE=y
|
|||
#
|
||||
# Display Interface Bridges
|
||||
#
|
||||
CONFIG_DRM_ANALOGIX_ANX78XX=m
|
||||
CONFIG_DRM_CDNS_DSI=m
|
||||
# CONFIG_DRM_DUMB_VGA_DAC is not set
|
||||
# CONFIG_DRM_LVDS_ENCODER is not set
|
||||
|
|
@ -4116,7 +4173,6 @@ CONFIG_DRM_TOSHIBA_TC358764=m
|
|||
# CONFIG_DRM_TI_TFP410 is not set
|
||||
CONFIG_DRM_TI_SN65DSI86=m
|
||||
CONFIG_DRM_ANALOGIX_DP_I2C=m
|
||||
CONFIG_DRM_ANALOGIX_ANX78XX=m
|
||||
CONFIG_DRM_ANALOGIX_ANX6345=m
|
||||
# CONFIG_DRM_I2C_ADV7511 is not set
|
||||
CONFIG_DRM_DW_HDMI=y
|
||||
|
|
@ -4130,7 +4186,14 @@ CONFIG_DRM_ETNAVIV_THERMAL=y
|
|||
# CONFIG_DRM_ARCPGU is not set
|
||||
# CONFIG_DRM_HISI_KIRIN is not set
|
||||
# CONFIG_DRM_MXSFB is not set
|
||||
# CONFIG_DRM_TINYDRM is not set
|
||||
CONFIG_DRM_GM12U320=m
|
||||
CONFIG_TINYDRM_HX8357D=m
|
||||
CONFIG_TINYDRM_ILI9225=m
|
||||
CONFIG_TINYDRM_ILI9341=m
|
||||
CONFIG_TINYDRM_MI0283QT=m
|
||||
CONFIG_TINYDRM_REPAPER=m
|
||||
CONFIG_TINYDRM_ST7586=m
|
||||
CONFIG_TINYDRM_ST7735R=m
|
||||
# CONFIG_DRM_PL111 is not set
|
||||
CONFIG_DRM_LIMA=m
|
||||
CONFIG_DRM_PANFROST=m
|
||||
|
|
@ -4164,6 +4227,7 @@ CONFIG_FB_MODE_HELPERS=y
|
|||
# CONFIG_FB_UVESA is not set
|
||||
# CONFIG_FB_OPENCORES is not set
|
||||
# CONFIG_FB_S1D13XXX is not set
|
||||
# CONFIG_FB_SUN5I_EINK is not set
|
||||
# CONFIG_FB_SMSCUFX is not set
|
||||
# CONFIG_FB_UDL is not set
|
||||
# CONFIG_FB_IBM_GXT4500 is not set
|
||||
|
|
@ -4434,6 +4498,7 @@ CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
|
|||
# CONFIG_SND_SOC_TS3A227E is not set
|
||||
# CONFIG_SND_SOC_TSCS42XX is not set
|
||||
CONFIG_SND_SOC_TSCS454=m
|
||||
CONFIG_SND_SOC_UDA1334=m
|
||||
# CONFIG_SND_SOC_WM8510 is not set
|
||||
# CONFIG_SND_SOC_WM8523 is not set
|
||||
CONFIG_SND_SOC_WM8524=m
|
||||
|
|
@ -4503,6 +4568,7 @@ CONFIG_HID_MACALLY=m
|
|||
CONFIG_HID_PRODIKEYS=m
|
||||
# CONFIG_HID_CMEDIA is not set
|
||||
CONFIG_HID_CP2112=m
|
||||
CONFIG_HID_CREATIVE_SB0540=m
|
||||
CONFIG_HID_CYPRESS=m
|
||||
CONFIG_HID_DRAGONRISE=m
|
||||
CONFIG_DRAGONRISE_FF=y
|
||||
|
|
@ -4609,6 +4675,9 @@ CONFIG_I2C_HID=m
|
|||
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_LED_TRIG=y
|
||||
# CONFIG_USB_ULPI_BUS is not set
|
||||
CONFIG_USB_CONN_GPIO=m
|
||||
CONFIG_USB_ARCH_HAS_HCD=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
|
|
@ -4625,7 +4694,6 @@ CONFIG_USB_OTG=y
|
|||
CONFIG_USB_LEDS_TRIGGER_USBPORT=y
|
||||
CONFIG_USB_AUTOSUSPEND_DELAY=2
|
||||
CONFIG_USB_MON=m
|
||||
# CONFIG_USB_WUSB_CBAF is not set
|
||||
|
||||
#
|
||||
# USB Host Controller Drivers
|
||||
|
|
@ -4695,6 +4763,9 @@ CONFIG_USBIP_VHCI_NR_HCS=1
|
|||
CONFIG_USBIP_HOST=m
|
||||
CONFIG_USBIP_VUDC=m
|
||||
# CONFIG_USBIP_DEBUG is not set
|
||||
CONFIG_USB_CDNS3=m
|
||||
# CONFIG_USB_CDNS3_GADGET is not set
|
||||
# CONFIG_USB_CDNS3_HOST is not set
|
||||
CONFIG_USB_MUSB_HDRC=y
|
||||
# CONFIG_USB_MUSB_HOST is not set
|
||||
# CONFIG_USB_MUSB_GADGET is not set
|
||||
|
|
@ -4797,7 +4868,6 @@ CONFIG_USB_SERIAL_DEBUG=m
|
|||
# CONFIG_USB_EMI26 is not set
|
||||
# CONFIG_USB_ADUTUX is not set
|
||||
# CONFIG_USB_SEVSEG is not set
|
||||
# CONFIG_USB_RIO500 is not set
|
||||
# CONFIG_USB_LEGOTOWER is not set
|
||||
# CONFIG_USB_LCD is not set
|
||||
# CONFIG_USB_CYPRESS_CY7C63 is not set
|
||||
|
|
@ -4937,9 +5007,6 @@ CONFIG_TYPEC_DP_ALTMODE=m
|
|||
# end of USB Type-C Alternate Mode drivers
|
||||
|
||||
CONFIG_USB_ROLE_SWITCH=m
|
||||
CONFIG_USB_LED_TRIG=y
|
||||
# CONFIG_USB_ULPI_BUS is not set
|
||||
# CONFIG_UWB is not set
|
||||
CONFIG_MMC=y
|
||||
CONFIG_PWRSEQ_EMMC=y
|
||||
# CONFIG_PWRSEQ_SD8787 is not set
|
||||
|
|
@ -4959,6 +5026,7 @@ CONFIG_MMC_SDHCI=y
|
|||
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
# CONFIG_MMC_SDHCI_OF_ARASAN is not set
|
||||
CONFIG_MMC_SDHCI_OF_ASPEED=m
|
||||
# CONFIG_MMC_SDHCI_OF_AT91 is not set
|
||||
# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set
|
||||
# CONFIG_MMC_SDHCI_CADENCE is not set
|
||||
|
|
@ -5100,7 +5168,6 @@ CONFIG_RTC_DRV_PCF8563=m
|
|||
CONFIG_RTC_DRV_PCF8583=m
|
||||
CONFIG_RTC_DRV_M41T80=m
|
||||
CONFIG_RTC_DRV_M41T80_WDT=y
|
||||
# CONFIG_RTC_DRV_BD70528 is not set
|
||||
CONFIG_RTC_DRV_BQ32K=m
|
||||
CONFIG_RTC_DRV_S35390A=m
|
||||
CONFIG_RTC_DRV_FM3130=m
|
||||
|
|
@ -5215,6 +5282,7 @@ CONFIG_DMA_ENGINE_RAID=y
|
|||
CONFIG_SYNC_FILE=y
|
||||
# CONFIG_SW_SYNC is not set
|
||||
# CONFIG_UDMABUF is not set
|
||||
CONFIG_DMABUF_SELFTESTS=m
|
||||
# end of DMABUF options
|
||||
|
||||
# CONFIG_AUXDISPLAY is not set
|
||||
|
|
@ -5233,6 +5301,7 @@ CONFIG_VIRTIO_MMIO=y
|
|||
#
|
||||
# end of Microsoft Hyper-V guest support
|
||||
|
||||
# CONFIG_GREYBUS is not set
|
||||
CONFIG_STAGING=y
|
||||
# CONFIG_PRISM2_USB is not set
|
||||
# CONFIG_COMEDI is not set
|
||||
|
|
@ -5351,8 +5420,6 @@ CONFIG_FB_TFT_UC1611=m
|
|||
CONFIG_FB_TFT_UC1701=m
|
||||
CONFIG_FB_TFT_UPD161704=m
|
||||
CONFIG_FB_TFT_WATTEROTT=m
|
||||
CONFIG_FB_FLEX=m
|
||||
CONFIG_FB_TFT_FBTFT_DEVICE=m
|
||||
# CONFIG_WILC1000_SDIO is not set
|
||||
# CONFIG_WILC1000_SPI is not set
|
||||
CONFIG_MOST=m
|
||||
|
|
@ -5364,7 +5431,6 @@ CONFIG_MOST=m
|
|||
# CONFIG_MOST_I2C is not set
|
||||
# CONFIG_MOST_USB is not set
|
||||
# CONFIG_KS7010 is not set
|
||||
# CONFIG_GREYBUS is not set
|
||||
# CONFIG_PI433 is not set
|
||||
|
||||
#
|
||||
|
|
@ -5373,9 +5439,19 @@ CONFIG_MOST=m
|
|||
# end of Gasket devices
|
||||
|
||||
CONFIG_XIL_AXIS_FIFO=m
|
||||
# CONFIG_EROFS_FS is not set
|
||||
# CONFIG_FIELDBUS_DEV is not set
|
||||
# CONFIG_USB_WUSB_CBAF is not set
|
||||
# CONFIG_UWB is not set
|
||||
CONFIG_EXFAT_FS=m
|
||||
CONFIG_EXFAT_DONT_MOUNT_VFAT=y
|
||||
CONFIG_EXFAT_DISCARD=y
|
||||
# CONFIG_EXFAT_DELAYED_SYNC is not set
|
||||
# CONFIG_EXFAT_KERNEL_DEBUG is not set
|
||||
# CONFIG_EXFAT_DEBUG_MSG is not set
|
||||
CONFIG_EXFAT_DEFAULT_CODEPAGE=437
|
||||
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
|
||||
# CONFIG_GOLDFISH is not set
|
||||
# CONFIG_MFD_CROS_EC is not set
|
||||
# CONFIG_CHROME_PLATFORMS is not set
|
||||
# CONFIG_MELLANOX_PLATFORM is not set
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
|
|
@ -5510,13 +5586,6 @@ CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
|
|||
#
|
||||
# end of i.MX SoC drivers
|
||||
|
||||
#
|
||||
# IXP4xx SoC drivers
|
||||
#
|
||||
CONFIG_IXP4XX_QMGR=m
|
||||
CONFIG_IXP4XX_NPE=m
|
||||
# end of IXP4xx SoC drivers
|
||||
|
||||
#
|
||||
# Qualcomm SoC drivers
|
||||
#
|
||||
|
|
@ -5596,7 +5665,6 @@ CONFIG_DMARD06=m
|
|||
CONFIG_DMARD09=m
|
||||
CONFIG_DMARD10=m
|
||||
CONFIG_HID_SENSOR_ACCEL_3D=m
|
||||
CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
|
||||
CONFIG_IIO_ST_ACCEL_3AXIS=m
|
||||
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
|
||||
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
|
||||
|
|
@ -5850,6 +5918,7 @@ CONFIG_SI7020=m
|
|||
# Inertial measurement units
|
||||
#
|
||||
# CONFIG_ADIS16400 is not set
|
||||
CONFIG_ADIS16460=m
|
||||
# CONFIG_ADIS16480 is not set
|
||||
# CONFIG_BMI160_I2C is not set
|
||||
# CONFIG_BMI160_SPI is not set
|
||||
|
|
@ -5888,6 +5957,7 @@ CONFIG_LTR501=m
|
|||
CONFIG_LV0104CS=m
|
||||
CONFIG_MAX44000=m
|
||||
CONFIG_MAX44009=m
|
||||
CONFIG_NOA1305=m
|
||||
CONFIG_OPT3001=m
|
||||
CONFIG_PA12203001=m
|
||||
CONFIG_SI1133=m
|
||||
|
|
@ -5960,6 +6030,7 @@ CONFIG_IIO_TIGHTLOOP_TRIGGER=m
|
|||
#
|
||||
CONFIG_AD5272=m
|
||||
# CONFIG_DS1803 is not set
|
||||
CONFIG_MAX5432=m
|
||||
# CONFIG_MAX5481 is not set
|
||||
# CONFIG_MAX5487 is not set
|
||||
CONFIG_MCP4018=m
|
||||
|
|
@ -6058,6 +6129,7 @@ CONFIG_PARTITION_PERCPU=y
|
|||
# CONFIG_IPACK_BUS is not set
|
||||
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RESET_SCMI=y
|
||||
CONFIG_RESET_SIMPLE=y
|
||||
CONFIG_RESET_SUNXI=y
|
||||
# CONFIG_RESET_TI_SYSCON is not set
|
||||
|
|
@ -6195,6 +6267,7 @@ CONFIG_EXPORTFS_BLOCK_OPS=y
|
|||
CONFIG_FILE_LOCKING=y
|
||||
CONFIG_MANDATORY_FILE_LOCKING=y
|
||||
CONFIG_FS_ENCRYPTION=y
|
||||
# CONFIG_FS_VERITY is not set
|
||||
CONFIG_FSNOTIFY=y
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
|
|
@ -6211,6 +6284,7 @@ CONFIG_AUTOFS4_FS=y
|
|||
CONFIG_AUTOFS_FS=y
|
||||
CONFIG_FUSE_FS=m
|
||||
CONFIG_CUSE=m
|
||||
CONFIG_VIRTIO_FS=m
|
||||
CONFIG_OVERLAY_FS=m
|
||||
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
|
||||
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
|
||||
|
|
@ -6312,24 +6386,7 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
|
|||
# CONFIG_PSTORE is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
CONFIG_AUFS_FS=m
|
||||
CONFIG_AUFS_BRANCH_MAX_127=y
|
||||
# CONFIG_AUFS_BRANCH_MAX_511 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_1023 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_32767 is not set
|
||||
CONFIG_AUFS_SBILIST=y
|
||||
# CONFIG_AUFS_HNOTIFY is not set
|
||||
# CONFIG_AUFS_EXPORT is not set
|
||||
# CONFIG_AUFS_XATTR is not set
|
||||
# CONFIG_AUFS_FHSM is not set
|
||||
# CONFIG_AUFS_RDU is not set
|
||||
# CONFIG_AUFS_DIRREN is not set
|
||||
# CONFIG_AUFS_SHWH is not set
|
||||
# CONFIG_AUFS_BR_RAMFS is not set
|
||||
# CONFIG_AUFS_BR_FUSE is not set
|
||||
CONFIG_AUFS_BR_HFSPLUS=y
|
||||
CONFIG_AUFS_BDEV_LOOP=y
|
||||
# CONFIG_AUFS_DEBUG is not set
|
||||
# CONFIG_EROFS_FS is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V2=y
|
||||
|
|
@ -6479,6 +6536,7 @@ CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
|
|||
# CONFIG_SECURITY_LOADPIN is not set
|
||||
# CONFIG_SECURITY_YAMA is not set
|
||||
# CONFIG_SECURITY_SAFESETID is not set
|
||||
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
|
||||
CONFIG_INTEGRITY=y
|
||||
# CONFIG_INTEGRITY_SIGNATURE is not set
|
||||
CONFIG_INTEGRITY_AUDIT=y
|
||||
|
|
@ -6560,10 +6618,7 @@ CONFIG_CRYPTO_CCM=m
|
|||
CONFIG_CRYPTO_GCM=y
|
||||
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
|
||||
CONFIG_CRYPTO_AEGIS128=m
|
||||
CONFIG_CRYPTO_AEGIS128L=m
|
||||
CONFIG_CRYPTO_AEGIS256=m
|
||||
CONFIG_CRYPTO_MORUS640=m
|
||||
CONFIG_CRYPTO_MORUS1280=m
|
||||
CONFIG_CRYPTO_AEGIS128_SIMD=y
|
||||
CONFIG_CRYPTO_SEQIV=y
|
||||
CONFIG_CRYPTO_ECHAINIV=y
|
||||
|
||||
|
|
@ -6582,6 +6637,7 @@ CONFIG_CRYPTO_XTS=y
|
|||
# CONFIG_CRYPTO_KEYWRAP is not set
|
||||
CONFIG_CRYPTO_NHPOLY1305=m
|
||||
CONFIG_CRYPTO_ADIANTUM=m
|
||||
CONFIG_CRYPTO_ESSIV=m
|
||||
|
||||
#
|
||||
# Hash modes
|
||||
|
|
@ -6608,8 +6664,9 @@ CONFIG_CRYPTO_RMD160=m
|
|||
CONFIG_CRYPTO_RMD256=m
|
||||
CONFIG_CRYPTO_RMD320=m
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_LIB_SHA256=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
CONFIG_CRYPTO_SHA3=m
|
||||
CONFIG_CRYPTO_SM3=m
|
||||
CONFIG_CRYPTO_STREEBOG=m
|
||||
|
|
@ -6619,6 +6676,7 @@ CONFIG_CRYPTO_WP512=m
|
|||
#
|
||||
# Ciphers
|
||||
#
|
||||
CONFIG_CRYPTO_LIB_AES=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
CONFIG_CRYPTO_AES_TI=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
|
|
@ -6630,6 +6688,7 @@ CONFIG_CRYPTO_CAMELLIA=m
|
|||
CONFIG_CRYPTO_CAST_COMMON=m
|
||||
CONFIG_CRYPTO_CAST5=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_LIB_DES=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_FCRYPT=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
|
|
@ -6674,6 +6733,7 @@ CONFIG_CRYPTO_HW=y
|
|||
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
|
||||
# CONFIG_CRYPTO_DEV_CCP is not set
|
||||
CONFIG_CRYPTO_DEV_VIRTIO=m
|
||||
CONFIG_CRYPTO_DEV_SAFEXCEL=m
|
||||
CONFIG_CRYPTO_DEV_CCREE=m
|
||||
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
|
||||
CONFIG_ASYMMETRIC_KEY_TYPE=y
|
||||
|
|
@ -6778,7 +6838,6 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
|
|||
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
|
||||
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
|
||||
CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
|
||||
CONFIG_ARCH_HAS_DMA_MMAP_PGPROT=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_DMA_REMAP=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
|
|
@ -6800,16 +6859,14 @@ CONFIG_DQL=y
|
|||
CONFIG_GLOB=y
|
||||
# CONFIG_GLOB_SELFTEST is not set
|
||||
CONFIG_NLATTR=y
|
||||
CONFIG_LRU_CACHE=m
|
||||
CONFIG_CLZ_TAB=y
|
||||
# CONFIG_IRQ_POLL is not set
|
||||
CONFIG_MPILIB=y
|
||||
CONFIG_DIMLIB=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_OID_REGISTRY=y
|
||||
CONFIG_HAVE_GENERIC_VDSO=y
|
||||
CONFIG_GENERIC_GETTIMEOFDAY=y
|
||||
CONFIG_GENERIC_COMPAT_VDSO=y
|
||||
CONFIG_CROSS_COMPILE_COMPAT_VDSO=""
|
||||
CONFIG_FONT_SUPPORT=y
|
||||
# CONFIG_FONTS is not set
|
||||
CONFIG_FONT_8x8=y
|
||||
|
|
@ -6840,10 +6897,9 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
|
|||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_FRAME_WARN=2048
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_INSTALL is not set
|
||||
# CONFIG_OPTIMIZE_INLINING is not set
|
||||
CONFIG_OPTIMIZE_INLINING=y
|
||||
# CONFIG_DEBUG_SECTION_MISMATCH is not set
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
CONFIG_ARCH_WANT_FRAME_POINTERS=y
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
1
config/kernel/linux-sunxi64-dev.config
Symbolic link
1
config/kernel/linux-sunxi64-dev.config
Symbolic link
|
|
@ -0,0 +1 @@
|
|||
linux-sunxi64-current.config
|
||||
|
|
@ -21,4 +21,4 @@ ATF_COMPILER="aarch64-linux-gnu-"
|
|||
[[ -z $KERNEL_USE_GCC ]] && KERNEL_USE_GCC='> 8.0'
|
||||
[[ -z $KERNELDIR ]] && KERNELDIR=$MAINLINE_KERNEL_DIR
|
||||
[[ -z $KERNELSOURCE ]] && KERNELSOURCE=$MAINLINE_KERNEL_SOURCE
|
||||
[[ -z $KERNELBRANCH ]] && KERNELBRANCH='branch:linux-5.3.y'
|
||||
[[ -z $KERNELBRANCH ]] && KERNELBRANCH='branch:linux-5.4.y'
|
||||
|
|
|
|||
|
|
@ -14,4 +14,4 @@ CAN_BUILD_STRETCH=yes
|
|||
[[ -z $KERNEL_USE_GCC ]] && KERNEL_USE_GCC='> 8.0'
|
||||
[[ -z $KERNELDIR ]] && KERNELDIR=$MAINLINE_KERNEL_DIR
|
||||
[[ -z $KERNELSOURCE ]] && KERNELSOURCE=$MAINLINE_KERNEL_SOURCE
|
||||
[[ -z $KERNELBRANCH ]] && KERNELBRANCH='branch:linux-5.3.y'
|
||||
[[ -z $KERNELBRANCH ]] && KERNELBRANCH='branch:linux-5.4.y'
|
||||
|
|
|
|||
|
|
@ -19,12 +19,14 @@ CPUMAX=1536000
|
|||
GOVERNOR=conservative
|
||||
|
||||
case $BRANCH in
|
||||
dev)
|
||||
dev|current)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.4.y'
|
||||
KERNELSOURCE='https://github.com/150balbes/Amlogic_s905-kernel'
|
||||
KERNELBRANCH='branch:le'
|
||||
KERNELPATCHDIR='meson64-'$BRANCH
|
||||
|
||||
;;
|
||||
|
||||
esac
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ case $BRANCH in
|
|||
current)
|
||||
|
||||
KERNELSOURCE="https://github.com/megous/linux"
|
||||
KERNELBRANCH="branch:orange-pi-5.3"
|
||||
KERNELBRANCH="branch:orange-pi-5.4"
|
||||
KERNELPATCHDIR='sunxi-'$BRANCH
|
||||
|
||||
;;
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ case $BRANCH in
|
|||
current)
|
||||
|
||||
KERNELSOURCE="https://github.com/megous/linux"
|
||||
KERNELBRANCH="branch:orange-pi-5.3"
|
||||
KERNELBRANCH="branch:orange-pi-5.4"
|
||||
KERNELPATCHDIR='sunxi-'$BRANCH
|
||||
|
||||
;;
|
||||
|
|
|
|||
|
|
@ -24,18 +24,15 @@ case $BRANCH in
|
|||
|
||||
;;
|
||||
|
||||
current)
|
||||
current|dev)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.3.y'
|
||||
KERNELSOURCE='https://github.com/150balbes/Amlogic_s905-kernel'
|
||||
KERNELBRANCH='branch:le'
|
||||
KERNELPATCHDIR='meson64-'$BRANCH
|
||||
SERIALCON=ttyAML0
|
||||
BOOTSCRIPT="boot-odroid-n2-mainline.ini:boot.ini"
|
||||
|
||||
;;
|
||||
|
||||
dev)
|
||||
SERIALCON=ttyAML0
|
||||
BOOTSCRIPT="boot-odroid-n2-mainline.ini:boot.ini"
|
||||
;;
|
||||
esac
|
||||
|
||||
CPUMIN=504000
|
||||
|
|
|
|||
|
|
@ -16,13 +16,7 @@ case $BRANCH in
|
|||
|
||||
;;
|
||||
|
||||
current)
|
||||
|
||||
:
|
||||
|
||||
;;
|
||||
|
||||
dev)
|
||||
current|dev)
|
||||
|
||||
KERNELSOURCE='https://github.com/mihailescu2m/linux'
|
||||
KERNELBRANCH='branch:odroidxu4-5.4.y'
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ case $BRANCH in
|
|||
|
||||
current)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.3.y'
|
||||
KERNELBRANCH='branch:linux-5.4.y'
|
||||
|
||||
;;
|
||||
|
||||
|
|
|
|||
|
|
@ -282,7 +282,7 @@ nanopineo dev buster minimal beta yes
|
|||
|
||||
nanopineo2 current buster cli stable yes
|
||||
nanopineo2 current stretch cli stable yes
|
||||
nanopineo2 current eoan cli stable yes
|
||||
nanopineo2 current bionic cli stable yes
|
||||
nanopineo2 dev buster minimal beta yes
|
||||
|
||||
# nanopineo2black
|
||||
|
|
@ -336,6 +336,7 @@ odroidn2 legacy buster desktop stable yes
|
|||
odroidn2 legacy stretch cli stable yes
|
||||
odroidn2 legacy bionic desktop stable yes
|
||||
odroidn2 legacy buster minimal stable yes
|
||||
odroidn2 current buster cli stable yes
|
||||
odroidn2 current buster minimal beta yes
|
||||
|
||||
# Odroid XU4
|
||||
|
|
@ -343,8 +344,8 @@ odroidn2 current buster minimal beta yes
|
|||
odroidxu4 legacy buster cli stable yes
|
||||
odroidxu4 legacy buster desktop stable yes
|
||||
odroidxu4 legacy stretch cli stable yes
|
||||
odroidxu4 legacy bionic desktop stable yes
|
||||
odroidxu4 legacy buster minimal stable yes
|
||||
odroidxu4 current bionic desktop stable yes
|
||||
odroidxu4 current buster minimal stable yes
|
||||
odroidxu4 dev buster minimal beta yes
|
||||
|
||||
# orangepi2
|
||||
|
|
|
|||
|
|
@ -1,79 +0,0 @@
|
|||
From 6638fb281f435dcbb9ee62f519dd3889690fc7d7 Mon Sep 17 00:00:00 2001
|
||||
From: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Mon, 5 Aug 2019 15:40:55 +0200
|
||||
Subject: [PATCH 1/8] drm/bridge: dw-hdmi-i2s: support more i2s format
|
||||
|
||||
The dw-hdmi-i2s supports more formats than just regular i2s.
|
||||
Add support for left justified, right justified and dsp modes
|
||||
A and B.
|
||||
|
||||
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
||||
---
|
||||
.../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 26 ++++++++++++++++---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 6 +++--
|
||||
2 files changed, 27 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
index 5cbb71a866d5..2b624cff541d 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
@@ -44,9 +44,8 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
|
||||
u8 inputclkfs = 0;
|
||||
|
||||
/* it cares I2S only */
|
||||
- if ((fmt->fmt != HDMI_I2S) ||
|
||||
- (fmt->bit_clk_master | fmt->frame_clk_master)) {
|
||||
- dev_err(dev, "unsupported format/settings\n");
|
||||
+ if (fmt->bit_clk_master | fmt->frame_clk_master) {
|
||||
+ dev_err(dev, "unsupported clock settings\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@@ -63,6 +62,27 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
|
||||
break;
|
||||
}
|
||||
|
||||
+ switch (fmt->fmt) {
|
||||
+ case HDMI_I2S:
|
||||
+ conf1 |= HDMI_AUD_CONF1_MODE_I2S;
|
||||
+ break;
|
||||
+ case HDMI_RIGHT_J:
|
||||
+ conf1 |= HDMI_AUD_CONF1_MODE_RIGHT_J;
|
||||
+ break;
|
||||
+ case HDMI_LEFT_J:
|
||||
+ conf1 |= HDMI_AUD_CONF1_MODE_LEFT_J;
|
||||
+ break;
|
||||
+ case HDMI_DSP_A:
|
||||
+ conf1 |= HDMI_AUD_CONF1_MODE_BURST_1;
|
||||
+ break;
|
||||
+ case HDMI_DSP_B:
|
||||
+ conf1 |= HDMI_AUD_CONF1_MODE_BURST_2;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(dev, "unsupported format\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
|
||||
|
||||
hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS);
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
index 4e3ec09d3ca4..091d7c28aa17 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
@@ -869,8 +869,10 @@ enum {
|
||||
|
||||
/* AUD_CONF1 field values */
|
||||
HDMI_AUD_CONF1_MODE_I2S = 0x00,
|
||||
- HDMI_AUD_CONF1_MODE_RIGHT_J = 0x02,
|
||||
- HDMI_AUD_CONF1_MODE_LEFT_J = 0x04,
|
||||
+ HDMI_AUD_CONF1_MODE_RIGHT_J = 0x20,
|
||||
+ HDMI_AUD_CONF1_MODE_LEFT_J = 0x40,
|
||||
+ HDMI_AUD_CONF1_MODE_BURST_1 = 0x60,
|
||||
+ HDMI_AUD_CONF1_MODE_BURST_2 = 0x80,
|
||||
HDMI_AUD_CONF1_WIDTH_16 = 0x10,
|
||||
HDMI_AUD_CONF1_WIDTH_24 = 0x18,
|
||||
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,124 +0,0 @@
|
|||
From 2eeb2438382f58c9e44ea521809d3301f94f7db1 Mon Sep 17 00:00:00 2001
|
||||
From: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Mon, 5 Aug 2019 15:40:56 +0200
|
||||
Subject: [PATCH 2/8] drm/bridge: dw-hdmi: move audio channel setup out of ahb
|
||||
|
||||
Part of the channel count setup done in dw-hdmi ahb should
|
||||
actually be done whatever the interface providing the data.
|
||||
|
||||
Let's move it to dw-hdmi driver instead.
|
||||
|
||||
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
||||
---
|
||||
.../drm/bridge/synopsys/dw-hdmi-ahb-audio.c | 20 +++---------
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 32 +++++++++++++++++++
|
||||
include/drm/bridge/dw_hdmi.h | 2 ++
|
||||
3 files changed, 38 insertions(+), 16 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c
|
||||
index a494186ae6ce..2b7539701b42 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c
|
||||
@@ -63,10 +63,6 @@ enum {
|
||||
HDMI_REVISION_ID = 0x0001,
|
||||
HDMI_IH_AHBDMAAUD_STAT0 = 0x0109,
|
||||
HDMI_IH_MUTE_AHBDMAAUD_STAT0 = 0x0189,
|
||||
- HDMI_FC_AUDICONF2 = 0x1027,
|
||||
- HDMI_FC_AUDSCONF = 0x1063,
|
||||
- HDMI_FC_AUDSCONF_LAYOUT1 = 1 << 0,
|
||||
- HDMI_FC_AUDSCONF_LAYOUT0 = 0 << 0,
|
||||
HDMI_AHB_DMA_CONF0 = 0x3600,
|
||||
HDMI_AHB_DMA_START = 0x3601,
|
||||
HDMI_AHB_DMA_STOP = 0x3602,
|
||||
@@ -403,7 +399,7 @@ static int dw_hdmi_prepare(struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct snd_dw_hdmi *dw = substream->private_data;
|
||||
- u8 threshold, conf0, conf1, layout, ca;
|
||||
+ u8 threshold, conf0, conf1, ca;
|
||||
|
||||
/* Setup as per 3.0.5 FSL 4.1.0 BSP */
|
||||
switch (dw->revision) {
|
||||
@@ -434,20 +430,12 @@ static int dw_hdmi_prepare(struct snd_pcm_substream *substream)
|
||||
conf1 = default_hdmi_channel_config[runtime->channels - 2].conf1;
|
||||
ca = default_hdmi_channel_config[runtime->channels - 2].ca;
|
||||
|
||||
- /*
|
||||
- * For >2 channel PCM audio, we need to select layout 1
|
||||
- * and set an appropriate channel map.
|
||||
- */
|
||||
- if (runtime->channels > 2)
|
||||
- layout = HDMI_FC_AUDSCONF_LAYOUT1;
|
||||
- else
|
||||
- layout = HDMI_FC_AUDSCONF_LAYOUT0;
|
||||
-
|
||||
writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD);
|
||||
writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0);
|
||||
writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1);
|
||||
- writeb_relaxed(layout, dw->data.base + HDMI_FC_AUDSCONF);
|
||||
- writeb_relaxed(ca, dw->data.base + HDMI_FC_AUDICONF2);
|
||||
+
|
||||
+ dw_hdmi_set_channel_count(dw->data.hdmi, runtime->channels);
|
||||
+ dw_hdmi_set_channel_allocation(dw->data.hdmi, ca);
|
||||
|
||||
switch (runtime->format) {
|
||||
case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
index c6490949d9db..43ea231bba75 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
@@ -630,6 +630,38 @@ void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
|
||||
|
||||
+void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
|
||||
+{
|
||||
+ u8 layout;
|
||||
+
|
||||
+ mutex_lock(&hdmi->audio_mutex);
|
||||
+
|
||||
+ /*
|
||||
+ * For >2 channel PCM audio, we need to select layout 1
|
||||
+ * and set an appropriate channel map.
|
||||
+ */
|
||||
+ if (cnt > 2)
|
||||
+ layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
|
||||
+ else
|
||||
+ layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
|
||||
+
|
||||
+ hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
|
||||
+ HDMI_FC_AUDSCONF);
|
||||
+
|
||||
+ mutex_unlock(&hdmi->audio_mutex);
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
|
||||
+
|
||||
+void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
|
||||
+{
|
||||
+ mutex_lock(&hdmi->audio_mutex);
|
||||
+
|
||||
+ hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
|
||||
+
|
||||
+ mutex_unlock(&hdmi->audio_mutex);
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
|
||||
+
|
||||
static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
|
||||
index c402364aec0d..cf528c289857 100644
|
||||
--- a/include/drm/bridge/dw_hdmi.h
|
||||
+++ b/include/drm/bridge/dw_hdmi.h
|
||||
@@ -155,6 +155,8 @@ void dw_hdmi_resume(struct dw_hdmi *hdmi);
|
||||
void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
|
||||
|
||||
void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
|
||||
+void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt);
|
||||
+void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca);
|
||||
void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
|
||||
void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
|
||||
void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi);
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
From 26d326a3576c30946248bfd66f897bc075119274 Mon Sep 17 00:00:00 2001
|
||||
From: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Mon, 5 Aug 2019 15:40:57 +0200
|
||||
Subject: [PATCH 3/8] drm/bridge: dw-hdmi: set channel count in the infoframes
|
||||
|
||||
Set the number of channel in the infoframes
|
||||
|
||||
Cc: Jonas Karlman <jonas@kwiboo.se>
|
||||
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
index 43ea231bba75..7c53068e0177 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
@@ -648,6 +648,10 @@ void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
|
||||
hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
|
||||
HDMI_FC_AUDSCONF);
|
||||
|
||||
+ /* Set the audio infoframes channel count */
|
||||
+ hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
|
||||
+ HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
|
||||
+
|
||||
mutex_unlock(&hdmi->audio_mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
From e70cea224676f6d878ab8c297c441a5a18d2fa8f Mon Sep 17 00:00:00 2001
|
||||
From: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Mon, 5 Aug 2019 15:40:58 +0200
|
||||
Subject: [PATCH 4/8] drm/bridge: dw-hdmi-i2s: enable lpcm multi channels
|
||||
|
||||
Properly setup the channel count and layout in dw-hdmi i2s driver so
|
||||
we are not limited to 2 channels.
|
||||
|
||||
Also correct the maximum channel reported by the DAI from 6 to 8 ch
|
||||
|
||||
Cc: Jonas Karlman <jonas@kwiboo.se>
|
||||
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
index 2b624cff541d..caf8aed78fea 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
@@ -84,6 +84,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
|
||||
}
|
||||
|
||||
dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
|
||||
+ dw_hdmi_set_channel_count(hdmi, hparms->channels);
|
||||
|
||||
hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS);
|
||||
hdmi_write(audio, conf0, HDMI_AUD_CONF0);
|
||||
@@ -139,7 +140,7 @@ static int snd_dw_hdmi_probe(struct platform_device *pdev)
|
||||
|
||||
pdata.ops = &dw_hdmi_i2s_ops;
|
||||
pdata.i2s = 1;
|
||||
- pdata.max_i2s_channels = 6;
|
||||
+ pdata.max_i2s_channels = 8;
|
||||
pdata.data = audio;
|
||||
|
||||
memset(&pdevinfo, 0, sizeof(pdevinfo));
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
From b40eb3be7a148ca74ded938951f6f5c4bbb75449 Mon Sep 17 00:00:00 2001
|
||||
From: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Mon, 5 Aug 2019 15:40:59 +0200
|
||||
Subject: [PATCH 5/8] drm/bridge: dw-hdmi-i2s: set the channel allocation
|
||||
|
||||
setup the channel allocation provided by the generic hdmi-codec driver
|
||||
|
||||
Cc: Jonas Karlman <jonas@kwiboo.se>
|
||||
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
index caf8aed78fea..0864dee8d180 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
@@ -85,6 +85,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
|
||||
|
||||
dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
|
||||
dw_hdmi_set_channel_count(hdmi, hparms->channels);
|
||||
+ dw_hdmi_set_channel_allocation(hdmi, hparms->cea.channel_allocation);
|
||||
|
||||
hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS);
|
||||
hdmi_write(audio, conf0, HDMI_AUD_CONF0);
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
From 82367607f5142c602a63b66ca6fd18bc6753b462 Mon Sep 17 00:00:00 2001
|
||||
From: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Mon, 5 Aug 2019 15:41:00 +0200
|
||||
Subject: [PATCH 6/8] drm/bridge: dw-hdmi-i2s: reset audio fifo before applying
|
||||
new params
|
||||
|
||||
When changing the audio hw params, reset the audio fifo to make sure
|
||||
any old remaining data is flushed.
|
||||
|
||||
The databook mentions that such reset should be followed by a reset of
|
||||
the i2s block to make sure the samples stay aligned
|
||||
|
||||
Cc: Jonas Karlman <jonas@kwiboo.se>
|
||||
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 6 ++++--
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 +
|
||||
2 files changed, 5 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
index 0864dee8d180..41bee0099578 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
@@ -49,6 +49,10 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
+ /* Reset the FIFOs before applying new params */
|
||||
+ hdmi_write(audio, HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0);
|
||||
+ hdmi_write(audio, (u8)~HDMI_MC_SWRSTZ_I2SSWRST_REQ, HDMI_MC_SWRSTZ);
|
||||
+
|
||||
inputclkfs = HDMI_AUD_INPUTCLKFS_64FS;
|
||||
conf0 = HDMI_AUD_CONF0_I2S_ALL_ENABLE;
|
||||
|
||||
@@ -102,8 +106,6 @@ static void dw_hdmi_i2s_audio_shutdown(struct device *dev, void *data)
|
||||
struct dw_hdmi *hdmi = audio->hdmi;
|
||||
|
||||
dw_hdmi_audio_disable(hdmi);
|
||||
-
|
||||
- hdmi_write(audio, HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0);
|
||||
}
|
||||
|
||||
static int dw_hdmi_i2s_get_dai_id(struct snd_soc_component *component,
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
index 091d7c28aa17..a272fa393ae6 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
@@ -940,6 +940,7 @@ enum {
|
||||
HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
|
||||
|
||||
/* MC_SWRSTZ field values */
|
||||
+ HDMI_MC_SWRSTZ_I2SSWRST_REQ = 0x08,
|
||||
HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
|
||||
|
||||
/* MC_FLOWCTRL field values */
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
From 47ea50564e8e7e6eb4c6544e47e25ae92a7ec1ec Mon Sep 17 00:00:00 2001
|
||||
From: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Mon, 5 Aug 2019 15:41:01 +0200
|
||||
Subject: [PATCH 7/8] drm/bridge: dw-hdmi-i2s: enable only the required i2s
|
||||
lanes
|
||||
|
||||
Enable the i2s lanes depending on the number of channel in the stream
|
||||
|
||||
Cc: Jonas Karlman <jonas@kwiboo.se>
|
||||
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
||||
---
|
||||
.../gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 15 ++++++++++++++-
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 6 +++++-
|
||||
2 files changed, 19 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
index 41bee0099578..b8ece9c1ba2c 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
@@ -54,7 +54,20 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
|
||||
hdmi_write(audio, (u8)~HDMI_MC_SWRSTZ_I2SSWRST_REQ, HDMI_MC_SWRSTZ);
|
||||
|
||||
inputclkfs = HDMI_AUD_INPUTCLKFS_64FS;
|
||||
- conf0 = HDMI_AUD_CONF0_I2S_ALL_ENABLE;
|
||||
+ conf0 = (HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_EN0);
|
||||
+
|
||||
+ /* Enable the required i2s lanes */
|
||||
+ switch (hparms->channels) {
|
||||
+ case 7 ... 8:
|
||||
+ conf0 |= HDMI_AUD_CONF0_I2S_EN3;
|
||||
+ /* Fall-thru */
|
||||
+ case 5 ... 6:
|
||||
+ conf0 |= HDMI_AUD_CONF0_I2S_EN2;
|
||||
+ /* Fall-thru */
|
||||
+ case 3 ... 4:
|
||||
+ conf0 |= HDMI_AUD_CONF0_I2S_EN1;
|
||||
+ /* Fall-thru */
|
||||
+ }
|
||||
|
||||
switch (hparms->sample_width) {
|
||||
case 16:
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
index a272fa393ae6..6988f12d89d9 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
@@ -865,7 +865,11 @@ enum {
|
||||
|
||||
/* AUD_CONF0 field values */
|
||||
HDMI_AUD_CONF0_SW_RESET = 0x80,
|
||||
- HDMI_AUD_CONF0_I2S_ALL_ENABLE = 0x2F,
|
||||
+ HDMI_AUD_CONF0_I2S_SELECT = 0x20,
|
||||
+ HDMI_AUD_CONF0_I2S_EN3 = 0x08,
|
||||
+ HDMI_AUD_CONF0_I2S_EN2 = 0x04,
|
||||
+ HDMI_AUD_CONF0_I2S_EN1 = 0x02,
|
||||
+ HDMI_AUD_CONF0_I2S_EN0 = 0x01,
|
||||
|
||||
/* AUD_CONF1 field values */
|
||||
HDMI_AUD_CONF1_MODE_I2S = 0x00,
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
From 689875c6e561f0f658de3d9f0b965c0daae7dbab Mon Sep 17 00:00:00 2001
|
||||
From: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Mon, 5 Aug 2019 15:41:02 +0200
|
||||
Subject: [PATCH 8/8] drm/bridge: dw-hdmi-i2s: add .get_eld support
|
||||
|
||||
Provide the eld to the generic hdmi-codec driver.
|
||||
This will let the driver enforce the maximum channel number and set the
|
||||
channel allocation depending on the hdmi sink.
|
||||
|
||||
Cc: Jonas Karlman <jonas@kwiboo.se>
|
||||
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h | 1 +
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 10 ++++++++++
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
|
||||
3 files changed, 12 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h
|
||||
index 63b5756f463b..cb07dc0da5a7 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h
|
||||
@@ -14,6 +14,7 @@ struct dw_hdmi_audio_data {
|
||||
|
||||
struct dw_hdmi_i2s_audio_data {
|
||||
struct dw_hdmi *hdmi;
|
||||
+ u8 *eld;
|
||||
|
||||
void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
|
||||
u8 (*read)(struct dw_hdmi *hdmi, int offset);
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
index b8ece9c1ba2c..14d499b344c0 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
@@ -121,6 +121,15 @@ static void dw_hdmi_i2s_audio_shutdown(struct device *dev, void *data)
|
||||
dw_hdmi_audio_disable(hdmi);
|
||||
}
|
||||
|
||||
+static int dw_hdmi_i2s_get_eld(struct device *dev, void *data, uint8_t *buf,
|
||||
+ size_t len)
|
||||
+{
|
||||
+ struct dw_hdmi_i2s_audio_data *audio = data;
|
||||
+
|
||||
+ memcpy(buf, audio->eld, min(sizeof(audio->eld), len));
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int dw_hdmi_i2s_get_dai_id(struct snd_soc_component *component,
|
||||
struct device_node *endpoint)
|
||||
{
|
||||
@@ -144,6 +153,7 @@ static int dw_hdmi_i2s_get_dai_id(struct snd_soc_component *component,
|
||||
static struct hdmi_codec_ops dw_hdmi_i2s_ops = {
|
||||
.hw_params = dw_hdmi_i2s_hw_params,
|
||||
.audio_shutdown = dw_hdmi_i2s_audio_shutdown,
|
||||
+ .get_eld = dw_hdmi_i2s_get_eld,
|
||||
.get_dai_id = dw_hdmi_i2s_get_dai_id,
|
||||
};
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
index 7c53068e0177..a81063a06014 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
@@ -2782,6 +2782,7 @@ __dw_hdmi_probe(struct platform_device *pdev,
|
||||
struct dw_hdmi_i2s_audio_data audio;
|
||||
|
||||
audio.hdmi = hdmi;
|
||||
+ audio.eld = hdmi->connector.eld;
|
||||
audio.write = hdmi_writeb;
|
||||
audio.read = hdmi_readb;
|
||||
hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
From 95dcad22559d65838826e0f635041037e2407076 Mon Sep 17 00:00:00 2001
|
||||
From: Corentin Labbe <clabbe@baylibre.com>
|
||||
Date: Thu, 25 Jul 2019 19:42:53 +0000
|
||||
Subject: [PATCH 1/4] dt-bindings: crypto: Add DT bindings documentation for
|
||||
amlogic-crypto
|
||||
|
||||
This patch adds documentation for Device-Tree bindings for the
|
||||
Amlogic GXL cryptographic offloader driver.
|
||||
|
||||
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
|
||||
---
|
||||
.../bindings/crypto/amlogic-gxl-crypto.yaml | 45 +++++++++++++++++++
|
||||
1 file changed, 45 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/crypto/amlogic-gxl-crypto.yaml
|
||||
|
||||
diff --git a/Documentation/devicetree/bindings/crypto/amlogic-gxl-crypto.yaml b/Documentation/devicetree/bindings/crypto/amlogic-gxl-crypto.yaml
|
||||
new file mode 100644
|
||||
index 000000000000..41265e57c00b
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/crypto/amlogic-gxl-crypto.yaml
|
||||
@@ -0,0 +1,45 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0
|
||||
+%YAML 1.2
|
||||
+---
|
||||
+$id: http://devicetree.org/schemas/crypto/amlogic-gxl-crypto.yaml#
|
||||
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
+
|
||||
+title: Amlogic GXL Cryptographic Offloader
|
||||
+
|
||||
+maintainers:
|
||||
+ - Corentin Labbe <clabbe@baylibre.com>
|
||||
+
|
||||
+properties:
|
||||
+ compatible:
|
||||
+ oneOf:
|
||||
+ - const: amlogic,gxl-crypto
|
||||
+
|
||||
+ reg:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ interrupts:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ clocks:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ clock-names:
|
||||
+ const: blkmv
|
||||
+
|
||||
+required:
|
||||
+ - compatible
|
||||
+ - reg
|
||||
+ - interrupts
|
||||
+ - clocks
|
||||
+ - clock-names
|
||||
+
|
||||
+examples:
|
||||
+ - |
|
||||
+ crypto: crypto@c883e000 {
|
||||
+ compatible = "amlogic,gxl-crypto";
|
||||
+ reg = <0x0 0xc883e000 0x0 0x36>;
|
||||
+ interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
|
||||
+ clocks = <&clkc CLKID_BLKMV>;
|
||||
+ clock-names = "blkmv";
|
||||
+ };
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,961 +0,0 @@
|
|||
From a79f8713e99873f1ac7c0e54d0ab9e8f1f5f982a Mon Sep 17 00:00:00 2001
|
||||
From: Corentin Labbe <clabbe@baylibre.com>
|
||||
Date: Thu, 25 Jul 2019 19:42:54 +0000
|
||||
Subject: [PATCH 2/4] crypto: amlogic: Add crypto accelerator for amlogic GXL
|
||||
|
||||
This patch adds support for the amlogic GXL cryptographic offloader present
|
||||
on GXL SoCs.
|
||||
|
||||
This driver supports AES cipher in CBC/ECB mode.
|
||||
|
||||
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
|
||||
---
|
||||
drivers/crypto/Kconfig | 2 +
|
||||
drivers/crypto/Makefile | 1 +
|
||||
drivers/crypto/amlogic/Kconfig | 24 ++
|
||||
drivers/crypto/amlogic/Makefile | 2 +
|
||||
drivers/crypto/amlogic/amlogic-cipher.c | 358 ++++++++++++++++++++++++
|
||||
drivers/crypto/amlogic/amlogic-core.c | 326 +++++++++++++++++++++
|
||||
drivers/crypto/amlogic/amlogic.h | 172 ++++++++++++
|
||||
7 files changed, 885 insertions(+)
|
||||
create mode 100644 drivers/crypto/amlogic/Kconfig
|
||||
create mode 100644 drivers/crypto/amlogic/Makefile
|
||||
create mode 100644 drivers/crypto/amlogic/amlogic-cipher.c
|
||||
create mode 100644 drivers/crypto/amlogic/amlogic-core.c
|
||||
create mode 100644 drivers/crypto/amlogic/amlogic.h
|
||||
|
||||
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
|
||||
index 603413f28fa3..3b14afbcf092 100644
|
||||
--- a/drivers/crypto/Kconfig
|
||||
+++ b/drivers/crypto/Kconfig
|
||||
@@ -785,4 +785,6 @@ config CRYPTO_DEV_CCREE
|
||||
|
||||
source "drivers/crypto/hisilicon/Kconfig"
|
||||
|
||||
+source "drivers/crypto/amlogic/Kconfig"
|
||||
+
|
||||
endif # CRYPTO_HW
|
||||
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
|
||||
index afc4753b5d28..9919fbe0e1d4 100644
|
||||
--- a/drivers/crypto/Makefile
|
||||
+++ b/drivers/crypto/Makefile
|
||||
@@ -48,3 +48,4 @@ obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
|
||||
obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
|
||||
obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
|
||||
obj-y += hisilicon/
|
||||
+obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
|
||||
diff --git a/drivers/crypto/amlogic/Kconfig b/drivers/crypto/amlogic/Kconfig
|
||||
new file mode 100644
|
||||
index 000000000000..9c4bf96afeb3
|
||||
--- /dev/null
|
||||
+++ b/drivers/crypto/amlogic/Kconfig
|
||||
@@ -0,0 +1,24 @@
|
||||
+config CRYPTO_DEV_AMLOGIC_GXL
|
||||
+ tristate "Support for amlogic cryptographic offloader"
|
||||
+ default y if ARCH_MESON
|
||||
+ select CRYPTO_BLKCIPHER
|
||||
+ select CRYPTO_ENGINE
|
||||
+ select CRYPTO_ECB
|
||||
+ select CRYPTO_CBC
|
||||
+ select CRYPTO_AES
|
||||
+ help
|
||||
+ Select y here for having support for the cryptographic offloader
|
||||
+ availlable on Amlogic GXL SoC.
|
||||
+ This hardware handle AES ciphers in ECB/CBC mode.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here: the module
|
||||
+ will be called amlogic-crypto.
|
||||
+
|
||||
+config CRYPTO_DEV_AMLOGIC_GXL_DEBUG
|
||||
+ bool "Enabled amlogic stats"
|
||||
+ depends on CRYPTO_DEV_AMLOGIC_GXL
|
||||
+ depends on DEBUG_FS
|
||||
+ help
|
||||
+ Say y to enabled amlogic-crypto debug stats.
|
||||
+ This will create /sys/kernel/debug/gxl-crypto/stats for displaying
|
||||
+ the number of requests per flow and per algorithm.
|
||||
diff --git a/drivers/crypto/amlogic/Makefile b/drivers/crypto/amlogic/Makefile
|
||||
new file mode 100644
|
||||
index 000000000000..0ec472c5562e
|
||||
--- /dev/null
|
||||
+++ b/drivers/crypto/amlogic/Makefile
|
||||
@@ -0,0 +1,2 @@
|
||||
+obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic-crypto.o
|
||||
+amlogic-crypto-y := amlogic-core.o amlogic-cipher.o
|
||||
diff --git a/drivers/crypto/amlogic/amlogic-cipher.c b/drivers/crypto/amlogic/amlogic-cipher.c
|
||||
new file mode 100644
|
||||
index 000000000000..84e65b4e9ba9
|
||||
--- /dev/null
|
||||
+++ b/drivers/crypto/amlogic/amlogic-cipher.c
|
||||
@@ -0,0 +1,358 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * amlogic-cipher.c - hardware cryptographic offloader for Amlogic GXL SoC
|
||||
+ *
|
||||
+ * Copyright (C) 2018-2019 Corentin LABBE <clabbe@baylibre.com>
|
||||
+ *
|
||||
+ * This file add support for AES cipher with 128,192,256 bits keysize in
|
||||
+ * CBC and ECB mode.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/crypto.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <crypto/scatterwalk.h>
|
||||
+#include <linux/scatterlist.h>
|
||||
+#include <linux/dma-mapping.h>
|
||||
+#include <crypto/internal/skcipher.h>
|
||||
+#include "amlogic.h"
|
||||
+
|
||||
+static int get_engine_number(struct meson_dev *mc)
|
||||
+{
|
||||
+ return atomic_inc_return(&mc->flow) % MAXFLOW;
|
||||
+}
|
||||
+
|
||||
+static int meson_cipher(struct skcipher_request *areq)
|
||||
+{
|
||||
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
|
||||
+ struct meson_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
|
||||
+ struct meson_cipher_req_ctx *rctx = skcipher_request_ctx(areq);
|
||||
+ struct meson_dev *mc = op->mc;
|
||||
+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
|
||||
+ struct meson_alg_template *algt;
|
||||
+ int flow = rctx->flow;
|
||||
+ unsigned int todo, eat, len;
|
||||
+ struct scatterlist *src_sg = areq->src;
|
||||
+ struct scatterlist *dst_sg = areq->dst;
|
||||
+ struct meson_desc *desc;
|
||||
+ bool need_fallback = false;
|
||||
+ int nr_sgs, nr_sgd;
|
||||
+ int i, err = 0;
|
||||
+ unsigned int keyivlen, ivsize, offset, tloffset;
|
||||
+ dma_addr_t phykeyiv;
|
||||
+ void *backup_iv = NULL, *bkeyiv;
|
||||
+
|
||||
+ algt = container_of(alg, struct meson_alg_template, alg.skcipher);
|
||||
+
|
||||
+ dev_dbg(mc->dev, "%s %s %u %x IV(%u) key=%u flow=%d\n", __func__,
|
||||
+ crypto_tfm_alg_name(areq->base.tfm),
|
||||
+ areq->cryptlen,
|
||||
+ rctx->op_dir, crypto_skcipher_ivsize(tfm),
|
||||
+ op->keylen, flow);
|
||||
+
|
||||
+ if (areq->cryptlen == 0)
|
||||
+ need_fallback = true;
|
||||
+
|
||||
+ if (sg_nents(src_sg) != sg_nents(dst_sg))
|
||||
+ need_fallback = true;
|
||||
+
|
||||
+ /* KEY/IV descriptors use 3 desc */
|
||||
+ if (sg_nents(src_sg) > MAXDESC - 3 || sg_nents(dst_sg) > MAXDESC - 3)
|
||||
+ need_fallback = true;
|
||||
+
|
||||
+ while (src_sg && dst_sg && !need_fallback) {
|
||||
+ if ((src_sg->length % 16) != 0)
|
||||
+ need_fallback = true;
|
||||
+ if ((dst_sg->length % 16) != 0)
|
||||
+ need_fallback = true;
|
||||
+ if (src_sg->length != dst_sg->length)
|
||||
+ need_fallback = true;
|
||||
+ if (!IS_ALIGNED(src_sg->offset, sizeof(u32)))
|
||||
+ need_fallback = true;
|
||||
+ if (!IS_ALIGNED(dst_sg->offset, sizeof(u32)))
|
||||
+ need_fallback = true;
|
||||
+ src_sg = sg_next(src_sg);
|
||||
+ dst_sg = sg_next(dst_sg);
|
||||
+ }
|
||||
+
|
||||
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
|
||||
+ algt->stat_req++;
|
||||
+#endif
|
||||
+
|
||||
+ if (need_fallback) {
|
||||
+ SYNC_SKCIPHER_REQUEST_ON_STACK(req, op->fallback_tfm);
|
||||
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
|
||||
+ algt->stat_fb++;
|
||||
+#endif
|
||||
+ skcipher_request_set_sync_tfm(req, op->fallback_tfm);
|
||||
+ skcipher_request_set_callback(req, areq->base.flags, NULL,
|
||||
+ NULL);
|
||||
+ skcipher_request_set_crypt(req, areq->src, areq->dst,
|
||||
+ areq->cryptlen, areq->iv);
|
||||
+ if (rctx->op_dir == MESON_DECRYPT)
|
||||
+ err = crypto_skcipher_decrypt(req);
|
||||
+ else
|
||||
+ err = crypto_skcipher_encrypt(req);
|
||||
+ skcipher_request_zero(req);
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * The hardware expect a list of meson_desc structures.
|
||||
+ * The 2 first structures store key
|
||||
+ * The third stores IV
|
||||
+ */
|
||||
+ bkeyiv = kzalloc(48, GFP_KERNEL | GFP_DMA);
|
||||
+ if (!bkeyiv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ memcpy(bkeyiv, op->key, op->keylen);
|
||||
+ keyivlen = op->keylen;
|
||||
+
|
||||
+ ivsize = crypto_skcipher_ivsize(tfm);
|
||||
+ if (areq->iv && ivsize > 0) {
|
||||
+ if (ivsize > areq->cryptlen) {
|
||||
+ dev_err(mc->dev, "invalid ivsize=%d vs len=%d\n", ivsize, areq->cryptlen);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ memcpy(bkeyiv + 32, areq->iv, ivsize);
|
||||
+ keyivlen = 48;
|
||||
+ if (rctx->op_dir == MESON_DECRYPT) {
|
||||
+ backup_iv = kzalloc(ivsize, GFP_KERNEL);
|
||||
+ if (!backup_iv) {
|
||||
+ err = -ENOMEM;
|
||||
+ goto theend;
|
||||
+ }
|
||||
+ offset = areq->cryptlen - ivsize;
|
||||
+ scatterwalk_map_and_copy(backup_iv, areq->src, offset,
|
||||
+ ivsize, 0);
|
||||
+ }
|
||||
+ }
|
||||
+ if (keyivlen == 24)
|
||||
+ keyivlen = 32;
|
||||
+
|
||||
+ phykeyiv = dma_map_single(mc->dev, bkeyiv, keyivlen,
|
||||
+ DMA_TO_DEVICE);
|
||||
+ if (dma_mapping_error(mc->dev, phykeyiv)) {
|
||||
+ dev_err(mc->dev, "Cannot DMA MAP KEY IV\n");
|
||||
+ return -EFAULT;
|
||||
+ }
|
||||
+
|
||||
+ tloffset = 0;
|
||||
+ eat = 0;
|
||||
+ i = 0;
|
||||
+ while (keyivlen > eat) {
|
||||
+ desc = &mc->chanlist[flow].tl[tloffset];
|
||||
+ memset(desc, 0, sizeof(struct meson_desc));
|
||||
+ todo = min(keyivlen - eat, 16u);
|
||||
+ desc->t_src = phykeyiv + i * 16;
|
||||
+ desc->t_dst = i * 16;
|
||||
+ desc->len = 16;
|
||||
+ desc->mode = MODE_KEY;
|
||||
+ desc->owner = 1;
|
||||
+ eat += todo;
|
||||
+ i++;
|
||||
+ tloffset++;
|
||||
+ }
|
||||
+
|
||||
+ if (areq->src == areq->dst) {
|
||||
+ nr_sgs = dma_map_sg(mc->dev, areq->src, sg_nents(areq->src),
|
||||
+ DMA_BIDIRECTIONAL);
|
||||
+ if (nr_sgs < 0) {
|
||||
+ dev_err(mc->dev, "Invalid SG count %d\n", nr_sgs);
|
||||
+ err = -EINVAL;
|
||||
+ goto theend;
|
||||
+ }
|
||||
+ nr_sgd = nr_sgs;
|
||||
+ } else {
|
||||
+ nr_sgs = dma_map_sg(mc->dev, areq->src, sg_nents(areq->src),
|
||||
+ DMA_TO_DEVICE);
|
||||
+ if (nr_sgs < 0 || nr_sgs > MAXDESC - 3) {
|
||||
+ dev_err(mc->dev, "Invalid SG count %d\n", nr_sgs);
|
||||
+ err = -EINVAL;
|
||||
+ goto theend;
|
||||
+ }
|
||||
+ nr_sgd = dma_map_sg(mc->dev, areq->dst, sg_nents(areq->dst),
|
||||
+ DMA_FROM_DEVICE);
|
||||
+ if (nr_sgd < 0 || nr_sgd > MAXDESC - 3) {
|
||||
+ dev_err(mc->dev, "Invalid SG count %d\n", nr_sgd);
|
||||
+ err = -EINVAL;
|
||||
+ goto theend;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
|
||||
+ mc->chanlist[flow].stat_req++;
|
||||
+#endif
|
||||
+ src_sg = areq->src;
|
||||
+ dst_sg = areq->dst;
|
||||
+ len = areq->cryptlen;
|
||||
+ while (src_sg) {
|
||||
+ desc = &mc->chanlist[flow].tl[tloffset];
|
||||
+ memset(desc, 0, sizeof(struct meson_desc));
|
||||
+
|
||||
+ desc->t_src = sg_dma_address(src_sg);
|
||||
+ desc->t_dst = sg_dma_address(dst_sg);
|
||||
+ todo = min(len, sg_dma_len(src_sg));
|
||||
+ desc->owner = 1;
|
||||
+ desc->len = todo;
|
||||
+ desc->mode = op->keymode;
|
||||
+ desc->op_mode = algt->blockmode;
|
||||
+ desc->enc = rctx->op_dir;
|
||||
+ len -= todo;
|
||||
+
|
||||
+ if (!sg_next(src_sg))
|
||||
+ desc->eoc = 1;
|
||||
+ tloffset++;
|
||||
+ src_sg = sg_next(src_sg);
|
||||
+ dst_sg = sg_next(dst_sg);
|
||||
+ }
|
||||
+
|
||||
+ reinit_completion(&mc->chanlist[flow].complete);
|
||||
+ mc->chanlist[flow].status = 0;
|
||||
+ writel(mc->chanlist[flow].t_phy | 2, mc->base + (flow << 2));
|
||||
+ wait_for_completion_interruptible_timeout(&mc->chanlist[flow].complete,
|
||||
+ msecs_to_jiffies(500));
|
||||
+ if (mc->chanlist[flow].status == 0) {
|
||||
+ dev_err(mc->dev, "DMA timeout for flow %d\n", flow);
|
||||
+ err = -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ dma_unmap_single(mc->dev, phykeyiv, keyivlen, DMA_TO_DEVICE);
|
||||
+
|
||||
+ if (areq->src == areq->dst) {
|
||||
+ dma_unmap_sg(mc->dev, areq->src, nr_sgs, DMA_BIDIRECTIONAL);
|
||||
+ } else {
|
||||
+ dma_unmap_sg(mc->dev, areq->src, nr_sgs, DMA_TO_DEVICE);
|
||||
+ dma_unmap_sg(mc->dev, areq->dst, nr_sgd, DMA_FROM_DEVICE);
|
||||
+ }
|
||||
+
|
||||
+ if (areq->iv && ivsize > 0) {
|
||||
+ if (rctx->op_dir == MESON_DECRYPT) {
|
||||
+ memcpy(areq->iv, backup_iv, ivsize);
|
||||
+ kzfree(backup_iv);
|
||||
+ } else {
|
||||
+ scatterwalk_map_and_copy(areq->iv, areq->dst,
|
||||
+ areq->cryptlen - ivsize,
|
||||
+ ivsize, 0);
|
||||
+ }
|
||||
+ }
|
||||
+theend:
|
||||
+ kzfree(bkeyiv);
|
||||
+
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static int handle_cipher_request(struct crypto_engine *engine,
|
||||
+ void *areq)
|
||||
+{
|
||||
+ int err;
|
||||
+ struct skcipher_request *breq = container_of(areq, struct skcipher_request, base);
|
||||
+
|
||||
+ err = meson_cipher(breq);
|
||||
+ crypto_finalize_skcipher_request(engine, breq, err);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int meson_skdecrypt(struct skcipher_request *areq)
|
||||
+{
|
||||
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
|
||||
+ struct meson_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
|
||||
+ struct meson_cipher_req_ctx *rctx = skcipher_request_ctx(areq);
|
||||
+ int e = get_engine_number(op->mc);
|
||||
+ struct crypto_engine *engine = op->mc->chanlist[e].engine;
|
||||
+
|
||||
+ rctx->op_dir = MESON_DECRYPT;
|
||||
+ rctx->flow = e;
|
||||
+
|
||||
+ return crypto_transfer_skcipher_request_to_engine(engine, areq);
|
||||
+}
|
||||
+
|
||||
+int meson_skencrypt(struct skcipher_request *areq)
|
||||
+{
|
||||
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
|
||||
+ struct meson_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
|
||||
+ struct meson_cipher_req_ctx *rctx = skcipher_request_ctx(areq);
|
||||
+ int e = get_engine_number(op->mc);
|
||||
+ struct crypto_engine *engine = op->mc->chanlist[e].engine;
|
||||
+
|
||||
+ rctx->op_dir = MESON_ENCRYPT;
|
||||
+ rctx->flow = e;
|
||||
+
|
||||
+ return crypto_transfer_skcipher_request_to_engine(engine, areq);
|
||||
+}
|
||||
+
|
||||
+int meson_cipher_init(struct crypto_tfm *tfm)
|
||||
+{
|
||||
+ struct meson_cipher_tfm_ctx *op = crypto_tfm_ctx(tfm);
|
||||
+ struct meson_alg_template *algt;
|
||||
+ const char *name = crypto_tfm_alg_name(tfm);
|
||||
+ struct crypto_skcipher *sktfm = __crypto_skcipher_cast(tfm);
|
||||
+ struct skcipher_alg *alg = crypto_skcipher_alg(sktfm);
|
||||
+
|
||||
+ memset(op, 0, sizeof(struct meson_cipher_tfm_ctx));
|
||||
+
|
||||
+ algt = container_of(alg, struct meson_alg_template, alg.skcipher);
|
||||
+ op->mc = algt->mc;
|
||||
+
|
||||
+ sktfm->reqsize = sizeof(struct meson_cipher_req_ctx);
|
||||
+
|
||||
+ op->fallback_tfm = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
|
||||
+ if (IS_ERR(op->fallback_tfm)) {
|
||||
+ dev_err(op->mc->dev, "ERROR: Cannot allocate fallback for %s %ld\n",
|
||||
+ name, PTR_ERR(op->fallback_tfm));
|
||||
+ return PTR_ERR(op->fallback_tfm);
|
||||
+ }
|
||||
+
|
||||
+ op->enginectx.op.do_one_request = handle_cipher_request;
|
||||
+ op->enginectx.op.prepare_request = NULL;
|
||||
+ op->enginectx.op.unprepare_request = NULL;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+void meson_cipher_exit(struct crypto_tfm *tfm)
|
||||
+{
|
||||
+ struct meson_cipher_tfm_ctx *op = crypto_tfm_ctx(tfm);
|
||||
+
|
||||
+ if (op->key) {
|
||||
+ memzero_explicit(op->key, op->keylen);
|
||||
+ kfree(op->key);
|
||||
+ }
|
||||
+ crypto_free_sync_skcipher(op->fallback_tfm);
|
||||
+}
|
||||
+
|
||||
+int meson_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
|
||||
+ unsigned int keylen)
|
||||
+{
|
||||
+ struct meson_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
|
||||
+ struct meson_dev *mc = op->mc;
|
||||
+
|
||||
+ switch (keylen) {
|
||||
+ case 128 / 8:
|
||||
+ op->keymode = MODE_AES_128;
|
||||
+ break;
|
||||
+ case 192 / 8:
|
||||
+ op->keymode = MODE_AES_192;
|
||||
+ break;
|
||||
+ case 256 / 8:
|
||||
+ op->keymode = MODE_AES_256;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_dbg(mc->dev, "ERROR: Invalid keylen %u\n", keylen);
|
||||
+ crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ if (op->key) {
|
||||
+ memzero_explicit(op->key, op->keylen);
|
||||
+ kfree(op->key);
|
||||
+ }
|
||||
+ op->keylen = keylen;
|
||||
+ op->key = kmalloc(keylen, GFP_KERNEL | GFP_DMA);
|
||||
+ if (!op->key)
|
||||
+ return -ENOMEM;
|
||||
+ memcpy(op->key, key, keylen);
|
||||
+
|
||||
+ return crypto_sync_skcipher_setkey(op->fallback_tfm, key, keylen);
|
||||
+}
|
||||
diff --git a/drivers/crypto/amlogic/amlogic-core.c b/drivers/crypto/amlogic/amlogic-core.c
|
||||
new file mode 100644
|
||||
index 000000000000..94f6e5a520bb
|
||||
--- /dev/null
|
||||
+++ b/drivers/crypto/amlogic/amlogic-core.c
|
||||
@@ -0,0 +1,326 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * amlgoic-core.c - hardware cryptographic offloader for Amlogic GXL SoC
|
||||
+ *
|
||||
+ * Copyright (C) 2018-2019 Corentin Labbe <clabbe@baylibre.com>
|
||||
+ *
|
||||
+ * Core file which registers crypto algorithms supported by the hardware.
|
||||
+ */
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/crypto.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/irq.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <crypto/internal/skcipher.h>
|
||||
+#include <linux/dma-mapping.h>
|
||||
+
|
||||
+#include "amlogic.h"
|
||||
+
|
||||
+static irqreturn_t meson_irq_handler(int irq, void *data)
|
||||
+{
|
||||
+ struct meson_dev *mc = (struct meson_dev *)data;
|
||||
+ int flow;
|
||||
+ u32 p;
|
||||
+
|
||||
+ for (flow = 0; flow < MAXFLOW; flow++) {
|
||||
+ if (mc->irqs[flow] == irq) {
|
||||
+ p = readl(mc->base + ((0x04 + flow) << 2));
|
||||
+ if (p) {
|
||||
+ writel_relaxed(0xF, mc->base + ((0x4 + flow) << 2));
|
||||
+ mc->chanlist[flow].status = 1;
|
||||
+ complete(&mc->chanlist[flow].complete);
|
||||
+ return IRQ_HANDLED;
|
||||
+ }
|
||||
+ dev_err(mc->dev, "%s %d Got irq for flow %d but ctrl is empty\n", __func__, irq, flow);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ dev_err(mc->dev, "%s %d from unknown irq\n", __func__, irq);
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+static struct meson_alg_template mc_algs[] = {
|
||||
+{
|
||||
+ .type = CRYPTO_ALG_TYPE_SKCIPHER,
|
||||
+ .blockmode = MESON_OPMODE_CBC,
|
||||
+ .alg.skcipher = {
|
||||
+ .base = {
|
||||
+ .cra_name = "cbc(aes)",
|
||||
+ .cra_driver_name = "cbc-aes-meson",
|
||||
+ .cra_priority = 400,
|
||||
+ .cra_blocksize = AES_BLOCK_SIZE,
|
||||
+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
|
||||
+ CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
|
||||
+ .cra_ctxsize = sizeof(struct meson_cipher_tfm_ctx),
|
||||
+ .cra_module = THIS_MODULE,
|
||||
+ .cra_alignmask = 0xf,
|
||||
+ .cra_init = meson_cipher_init,
|
||||
+ .cra_exit = meson_cipher_exit,
|
||||
+ },
|
||||
+ .min_keysize = AES_MIN_KEY_SIZE,
|
||||
+ .max_keysize = AES_MAX_KEY_SIZE,
|
||||
+ .ivsize = AES_BLOCK_SIZE,
|
||||
+ .setkey = meson_aes_setkey,
|
||||
+ .encrypt = meson_skencrypt,
|
||||
+ .decrypt = meson_skdecrypt,
|
||||
+ }
|
||||
+},
|
||||
+{
|
||||
+ .type = CRYPTO_ALG_TYPE_SKCIPHER,
|
||||
+ .blockmode = MESON_OPMODE_ECB,
|
||||
+ .alg.skcipher = {
|
||||
+ .base = {
|
||||
+ .cra_name = "ecb(aes)",
|
||||
+ .cra_driver_name = "ecb-aes-meson",
|
||||
+ .cra_priority = 400,
|
||||
+ .cra_blocksize = AES_BLOCK_SIZE,
|
||||
+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
|
||||
+ CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
|
||||
+ .cra_ctxsize = sizeof(struct meson_cipher_tfm_ctx),
|
||||
+ .cra_module = THIS_MODULE,
|
||||
+ .cra_alignmask = 0xf,
|
||||
+ .cra_init = meson_cipher_init,
|
||||
+ .cra_exit = meson_cipher_exit,
|
||||
+ },
|
||||
+ .min_keysize = AES_MIN_KEY_SIZE,
|
||||
+ .max_keysize = AES_MAX_KEY_SIZE,
|
||||
+ .setkey = meson_aes_setkey,
|
||||
+ .encrypt = meson_skencrypt,
|
||||
+ .decrypt = meson_skdecrypt,
|
||||
+ }
|
||||
+},
|
||||
+};
|
||||
+
|
||||
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
|
||||
+static int meson_dbgfs_read(struct seq_file *seq, void *v)
|
||||
+{
|
||||
+ struct meson_dev *mc = seq->private;
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < MAXFLOW; i++)
|
||||
+ seq_printf(seq, "Channel %d: req %lu\n", i, mc->chanlist[i].stat_req);
|
||||
+
|
||||
+ for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
|
||||
+ switch (mc_algs[i].type) {
|
||||
+ case CRYPTO_ALG_TYPE_SKCIPHER:
|
||||
+ seq_printf(seq, "%s %s %lu %lu\n",
|
||||
+ mc_algs[i].alg.skcipher.base.cra_driver_name,
|
||||
+ mc_algs[i].alg.skcipher.base.cra_name,
|
||||
+ mc_algs[i].stat_req, mc_algs[i].stat_fb);
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int meson_dbgfs_open(struct inode *inode, struct file *file)
|
||||
+{
|
||||
+ return single_open(file, meson_dbgfs_read, inode->i_private);
|
||||
+}
|
||||
+
|
||||
+static const struct file_operations meson_debugfs_fops = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .open = meson_dbgfs_open,
|
||||
+ .read = seq_read,
|
||||
+ .llseek = seq_lseek,
|
||||
+ .release = single_release,
|
||||
+};
|
||||
+#endif
|
||||
+
|
||||
+static int meson_crypto_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct resource *res;
|
||||
+ struct meson_dev *mc;
|
||||
+ int err, i;
|
||||
+
|
||||
+ if (!pdev->dev.of_node)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
|
||||
+ if (!mc)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ mc->dev = &pdev->dev;
|
||||
+ platform_set_drvdata(pdev, mc);
|
||||
+
|
||||
+ dev_info(mc->dev, "GXL crypto driver v1.1\n");
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ mc->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(mc->base)) {
|
||||
+ err = PTR_ERR(mc->base);
|
||||
+ dev_err(&pdev->dev, "Cannot request MMIO err=%d\n", err);
|
||||
+ return err;
|
||||
+ }
|
||||
+ mc->busclk = devm_clk_get(&pdev->dev, "blkmv");
|
||||
+ if (IS_ERR(mc->busclk)) {
|
||||
+ err = PTR_ERR(mc->busclk);
|
||||
+ dev_err(&pdev->dev, "Cannot get core clock err=%d\n", err);
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ mc->irqs = devm_kcalloc(mc->dev, MAXFLOW, sizeof(int), GFP_KERNEL);
|
||||
+ for (i = 0; i < MAXFLOW; i++) {
|
||||
+ mc->irqs[i] = platform_get_irq(pdev, i);
|
||||
+ if (mc->irqs[i] < 0) {
|
||||
+ dev_err(mc->dev, "Cannot get IRQ for flow %d\n", i);
|
||||
+ return mc->irqs[i];
|
||||
+ }
|
||||
+
|
||||
+ err = devm_request_irq(&pdev->dev, mc->irqs[i], meson_irq_handler, 0,
|
||||
+ "gxl-crypto", mc);
|
||||
+ if (err < 0) {
|
||||
+ dev_err(mc->dev, "Cannot request IRQ for flow %d\n", i);
|
||||
+ return err;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ mc->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
|
||||
+ if (IS_ERR(mc->reset)) {
|
||||
+ if (PTR_ERR(mc->reset) == -EPROBE_DEFER)
|
||||
+ return PTR_ERR(mc->reset);
|
||||
+ dev_info(&pdev->dev, "No reset control found\n");
|
||||
+ mc->reset = NULL;
|
||||
+ }
|
||||
+
|
||||
+ err = clk_prepare_enable(mc->busclk);
|
||||
+ if (err != 0) {
|
||||
+ dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ err = reset_control_deassert(mc->reset);
|
||||
+ if (err) {
|
||||
+ dev_err(&pdev->dev, "Cannot deassert reset control\n");
|
||||
+ goto error_clk;
|
||||
+ }
|
||||
+
|
||||
+ mc->chanlist = devm_kcalloc(mc->dev, MAXFLOW,
|
||||
+ sizeof(struct meson_flow), GFP_KERNEL);
|
||||
+ if (!mc->chanlist) {
|
||||
+ err = -ENOMEM;
|
||||
+ goto error_flow;
|
||||
+ }
|
||||
+
|
||||
+ for (i = 0; i < MAXFLOW; i++) {
|
||||
+ init_completion(&mc->chanlist[i].complete);
|
||||
+
|
||||
+ mc->chanlist[i].engine = crypto_engine_alloc_init(mc->dev, 1);
|
||||
+ if (!mc->chanlist[i].engine) {
|
||||
+ dev_err(mc->dev, "Cannot allocate engine\n");
|
||||
+ i--;
|
||||
+ goto error_engine;
|
||||
+ }
|
||||
+ err = crypto_engine_start(mc->chanlist[i].engine);
|
||||
+ if (err) {
|
||||
+ dev_err(mc->dev, "Cannot request engine\n");
|
||||
+ goto error_engine;
|
||||
+ }
|
||||
+ mc->chanlist[i].tl = dma_alloc_coherent(mc->dev,
|
||||
+ sizeof(struct meson_desc) * MAXDESC,
|
||||
+ &mc->chanlist[i].t_phy,
|
||||
+ GFP_KERNEL);
|
||||
+ if (!mc->chanlist[i].tl) {
|
||||
+ dev_err(mc->dev, "Cannot get DMA memory for task %d\n",
|
||||
+ i);
|
||||
+ err = -ENOMEM;
|
||||
+ goto error_engine;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
|
||||
+ mc->dbgfs_dir = debugfs_create_dir("gxl-crypto", NULL);
|
||||
+ debugfs_create_file("stats", 0444, mc->dbgfs_dir, mc, &meson_debugfs_fops);
|
||||
+#endif
|
||||
+ for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
|
||||
+ mc_algs[i].mc = mc;
|
||||
+ switch (mc_algs[i].type) {
|
||||
+ case CRYPTO_ALG_TYPE_SKCIPHER:
|
||||
+ err = crypto_register_skcipher(&mc_algs[i].alg.skcipher);
|
||||
+ if (err) {
|
||||
+ dev_err(mc->dev, "Fail to register %s\n",
|
||||
+ mc_algs[i].alg.skcipher.base.cra_name);
|
||||
+ mc_algs[i].mc = NULL;
|
||||
+ goto error_alg;
|
||||
+ }
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+error_alg:
|
||||
+ i--;
|
||||
+ for (; i >= 0; i--) {
|
||||
+ switch (mc_algs[i].type) {
|
||||
+ case CRYPTO_ALG_TYPE_SKCIPHER:
|
||||
+ if (mc_algs[i].mc)
|
||||
+ crypto_unregister_skcipher(&mc_algs[i].alg.skcipher);
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
|
||||
+ debugfs_remove_recursive(mc->dbgfs_dir);
|
||||
+#endif
|
||||
+ i = MAXFLOW;
|
||||
+error_engine:
|
||||
+ while (i >= 0) {
|
||||
+ if (mc->chanlist[i].tl)
|
||||
+ dma_free_coherent(mc->dev, sizeof(struct meson_desc) * MAXDESC,
|
||||
+ mc->chanlist[i].tl, mc->chanlist[i].t_phy);
|
||||
+ i--;
|
||||
+ }
|
||||
+error_flow:
|
||||
+ reset_control_assert(mc->reset);
|
||||
+error_clk:
|
||||
+ clk_disable_unprepare(mc->busclk);
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static int meson_crypto_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct meson_dev *mc = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
|
||||
+ switch (mc_algs[i].type) {
|
||||
+ case CRYPTO_ALG_TYPE_SKCIPHER:
|
||||
+ if (mc_algs[i].mc)
|
||||
+ crypto_unregister_skcipher(&mc_algs[i].alg.skcipher);
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
|
||||
+ debugfs_remove_recursive(mc->dbgfs_dir);
|
||||
+#endif
|
||||
+
|
||||
+ reset_control_assert(mc->reset);
|
||||
+ clk_disable_unprepare(mc->busclk);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id meson_crypto_of_match_table[] = {
|
||||
+ { .compatible = "amlogic,gxl-crypto", },
|
||||
+ {}
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, meson_crypto_of_match_table);
|
||||
+
|
||||
+static struct platform_driver meson_crypto_driver = {
|
||||
+ .probe = meson_crypto_probe,
|
||||
+ .remove = meson_crypto_remove,
|
||||
+ .driver = {
|
||||
+ .name = "gxl-crypto",
|
||||
+ .of_match_table = meson_crypto_of_match_table,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(meson_crypto_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Amlogic GXL cryptographic offloader");
|
||||
+MODULE_LICENSE("GPL");
|
||||
+MODULE_AUTHOR("Corentin Labbe <clabbe@baylibre.com>");
|
||||
diff --git a/drivers/crypto/amlogic/amlogic.h b/drivers/crypto/amlogic/amlogic.h
|
||||
new file mode 100644
|
||||
index 000000000000..23891cc58d7f
|
||||
--- /dev/null
|
||||
+++ b/drivers/crypto/amlogic/amlogic.h
|
||||
@@ -0,0 +1,172 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 */
|
||||
+/*
|
||||
+ * amlogic.h - hardware cryptographic offloader for Amlogic SoC
|
||||
+ *
|
||||
+ * Copyright (C) 2018-2019 Corentin LABBE <clabbe@baylibre.com>
|
||||
+ */
|
||||
+#include <crypto/aes.h>
|
||||
+#include <crypto/engine.h>
|
||||
+#include <crypto/skcipher.h>
|
||||
+#include <linux/debugfs.h>
|
||||
+#include <linux/crypto.h>
|
||||
+#include <linux/scatterlist.h>
|
||||
+
|
||||
+#define MODE_KEY 1
|
||||
+#define MODE_AES_128 0x8
|
||||
+#define MODE_AES_192 0x9
|
||||
+#define MODE_AES_256 0xa
|
||||
+
|
||||
+#define MESON_DECRYPT 0
|
||||
+#define MESON_ENCRYPT 1
|
||||
+
|
||||
+#define MESON_OPMODE_ECB 0
|
||||
+#define MESON_OPMODE_CBC 1
|
||||
+
|
||||
+#define MAXFLOW 2
|
||||
+
|
||||
+#define MAXDESC 64
|
||||
+
|
||||
+/*
|
||||
+ * struct meson_desc - Descriptor for DMA operations
|
||||
+ * Note that without datasheet, some are unknown
|
||||
+ * @len: length of data to operate
|
||||
+ * @irq: Ignored by hardware
|
||||
+ * @eoc: End of descriptor
|
||||
+ * @loop: Unknown
|
||||
+ * @mode: Type of algorithm (AES, SHA)
|
||||
+ * @begin: Unknown
|
||||
+ * @end: Unknown
|
||||
+ * @op_mode: Blockmode (CBC, ECB)
|
||||
+ * @block: Unknown
|
||||
+ * @error: Unknown
|
||||
+ * @owner: owner of the descriptor, 1 own by HW
|
||||
+ * @t_src: Physical address of data to read
|
||||
+ * @t_dst: Physical address of data to write
|
||||
+ */
|
||||
+struct meson_desc {
|
||||
+ union {
|
||||
+ u32 t_status;
|
||||
+ struct {
|
||||
+ u32 len:17;
|
||||
+ u32 irq:1;
|
||||
+ u32 eoc:1;
|
||||
+ u32 loop:1;
|
||||
+ u32 mode:4;
|
||||
+ u32 begin:1;
|
||||
+ u32 end:1;
|
||||
+ u32 op_mode:2;
|
||||
+ u32 enc:1;
|
||||
+ u32 block:1;
|
||||
+ u32 error:1;
|
||||
+ u32 owner:1;
|
||||
+ };
|
||||
+ };
|
||||
+ u32 t_src;
|
||||
+ u32 t_dst;
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
+ * struct meson_flow - Information used by each flow
|
||||
+ * @engine: ptr to the crypto_engine for this flow
|
||||
+ * @keylen: keylen for this flow operation
|
||||
+ * @complete: completion for the current task on this flow
|
||||
+ * @status: set to 1 by interrupt if task is done
|
||||
+ * @t_phy: Physical address of task
|
||||
+ * @tl: pointer to the current ce_task for this flow
|
||||
+ * @stat_req: number of request done by this flow
|
||||
+ */
|
||||
+struct meson_flow {
|
||||
+ struct crypto_engine *engine;
|
||||
+ struct completion complete;
|
||||
+ int status;
|
||||
+ unsigned int keylen;
|
||||
+ dma_addr_t t_phy;
|
||||
+ struct meson_desc *tl;
|
||||
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
|
||||
+ unsigned long stat_req;
|
||||
+#endif
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
+ * struct meson_dev - main container for all this driver information
|
||||
+ * @base: base address of amlogic-crypto
|
||||
+ * @busclk: bus clock for amlogic-crypto
|
||||
+ * @reset: pointer to reset controller
|
||||
+ * @dev: the platform device
|
||||
+ * @chanlist: array of all flow
|
||||
+ * @flow: flow to use in next request
|
||||
+ * @irqs: IRQ numbers for amlogic-crypto
|
||||
+ * @dbgfs_dir: Debugfs dentry for statistic directory
|
||||
+ * @dbgfs_stats: Debugfs dentry for statistic counters
|
||||
+ */
|
||||
+struct meson_dev {
|
||||
+ void __iomem *base;
|
||||
+ struct clk *busclk;
|
||||
+ struct reset_control *reset;
|
||||
+ struct device *dev;
|
||||
+ struct meson_flow *chanlist;
|
||||
+ atomic_t flow;
|
||||
+ int *irqs;
|
||||
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
|
||||
+ struct dentry *dbgfs_dir;
|
||||
+#endif
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
+ * struct meson_cipher_req_ctx - context for a skcipher request
|
||||
+ * @op_dir: direction (encrypt vs decrypt) for this request
|
||||
+ * @flow: the flow to use for this request
|
||||
+ */
|
||||
+struct meson_cipher_req_ctx {
|
||||
+ u32 op_dir;
|
||||
+ int flow;
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
+ * struct meson_cipher_tfm_ctx - context for a skcipher TFM
|
||||
+ * @enginectx: crypto_engine used by this TFM
|
||||
+ * @key: pointer to key data
|
||||
+ * @keylen: len of the key
|
||||
+ * @keymode: The keymode(type and size of key) associated with this TFM
|
||||
+ * @mc: pointer to the private data of driver handling this TFM
|
||||
+ * @fallback_tfm: pointer to the fallback TFM
|
||||
+ */
|
||||
+struct meson_cipher_tfm_ctx {
|
||||
+ struct crypto_engine_ctx enginectx;
|
||||
+ u32 *key;
|
||||
+ u32 keylen;
|
||||
+ u32 keymode;
|
||||
+ struct meson_dev *mc;
|
||||
+ struct crypto_sync_skcipher *fallback_tfm;
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
+ * struct meson_alg_template - crypto_alg template
|
||||
+ * @type: the CRYPTO_ALG_TYPE for this template
|
||||
+ * @blockmode: the type of block operation
|
||||
+ * @mc: pointer to the meson_dev structure associated with this template
|
||||
+ * @alg: one of sub struct must be used
|
||||
+ * @stat_req: number of request done on this template
|
||||
+ * @stat_fb: total of all data len done on this template
|
||||
+ */
|
||||
+struct meson_alg_template {
|
||||
+ u32 type;
|
||||
+ u32 blockmode;
|
||||
+ union {
|
||||
+ struct skcipher_alg skcipher;
|
||||
+ } alg;
|
||||
+ struct meson_dev *mc;
|
||||
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
|
||||
+ unsigned long stat_req;
|
||||
+ unsigned long stat_fb;
|
||||
+#endif
|
||||
+};
|
||||
+
|
||||
+int meson_enqueue(struct crypto_async_request *areq, u32 type);
|
||||
+
|
||||
+int meson_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
|
||||
+ unsigned int keylen);
|
||||
+int meson_cipher_init(struct crypto_tfm *tfm);
|
||||
+void meson_cipher_exit(struct crypto_tfm *tfm);
|
||||
+int meson_skdecrypt(struct skcipher_request *areq);
|
||||
+int meson_skencrypt(struct skcipher_request *areq);
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
From ea26c1dd64b66cd5917fdf4b416d7d04c4590c7a Mon Sep 17 00:00:00 2001
|
||||
From: Corentin Labbe <clabbe@baylibre.com>
|
||||
Date: Thu, 25 Jul 2019 19:42:55 +0000
|
||||
Subject: [PATCH 3/4] MAINTAINERS: Add myself as maintainer of amlogic crypto
|
||||
|
||||
I will maintain the amlogic crypto driver.
|
||||
|
||||
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
|
||||
---
|
||||
MAINTAINERS | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
diff --git a/MAINTAINERS b/MAINTAINERS
|
||||
index a2c343ee3b2c..277a3f020959 100644
|
||||
--- a/MAINTAINERS
|
||||
+++ b/MAINTAINERS
|
||||
@@ -1445,6 +1445,13 @@ F: drivers/mmc/host/meson*
|
||||
F: drivers/soc/amlogic/
|
||||
N: meson
|
||||
|
||||
+ARM/Amlogic Meson SoC Crypto Drivers
|
||||
+M: Corentin Labbe <clabbe@baylibre.com>
|
||||
+L: linux-crypto@vger.kernel.org
|
||||
+S: Maintained
|
||||
+F: drivers/crypto/amlogic/
|
||||
+F: Documentation/devicetree/bindings/crypto/amlogic*
|
||||
+
|
||||
ARM/Amlogic Meson SoC Sound Drivers
|
||||
M: Jerome Brunet <jbrunet@baylibre.com>
|
||||
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
From e71297718cc4a387e6f062ce44d9d187747cf129 Mon Sep 17 00:00:00 2001
|
||||
From: Corentin Labbe <clabbe@baylibre.com>
|
||||
Date: Thu, 25 Jul 2019 19:42:56 +0000
|
||||
Subject: [PATCH 4/4] ARM64: dts: amlogic: adds crypto hardware node
|
||||
|
||||
This patch adds the GXL crypto hardware node for all GXL SoCs.
|
||||
|
||||
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
|
||||
---
|
||||
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 11 +++++++++++
|
||||
1 file changed, 11 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
|
||||
index a09c53aaa0e8..905771a463f9 100644
|
||||
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
|
||||
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
|
||||
@@ -36,6 +36,17 @@
|
||||
phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ crypto: crypto@c883e000 {
|
||||
+ compatible = "amlogic,gxl-crypto";
|
||||
+ reg = <0x0 0xc883e000 0x0 0x36>;
|
||||
+ interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
|
||||
+ clocks = <&clkc CLKID_BLKMV>;
|
||||
+ clock-names = "blkmv";
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
};
|
||||
};
|
||||
|
||||
--
|
||||
2.20.1
|
||||
|
||||
125
patch/kernel/meson64-current/add_audio_sample_channel.patch
Normal file
125
patch/kernel/meson64-current/add_audio_sample_channel.patch
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
From patchwork Wed Sep 11 08:26:46 2019
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v3] drm: bridge/dw_hdmi: add audio sample channel status setting
|
||||
From: Cheng-Yi Chiang <cychiang@chromium.org>
|
||||
X-Patchwork-Id: 330283
|
||||
Message-Id: <20190911082646.134347-1-cychiang@chromium.org>
|
||||
To: linux-kernel@vger.kernel.org
|
||||
Cc: alsa-devel@alsa-project.org, kuninori.morimoto.gx@renesas.com,
|
||||
Neil Armstrong <narmstrong@baylibre.com>, airlied@linux.ie,
|
||||
dri-devel@lists.freedesktop.org, cain.cai@rock-chips.com,
|
||||
Laurent.pinchart@ideasonboard.com, Yakir Yang <ykk@rock-chips.com>,
|
||||
sam@ravnborg.org, Jerome Brunet <jbrunet@baylibre.com>,
|
||||
zhengxing@rock-chips.com, linux-rockchip@lists.infradead.org,
|
||||
dgreid@chromium.org, cychiang@chromium.org, tzungbi@chromium.org,
|
||||
Jonas Karlman <jonas@kwiboo.se>, jeffy.chen@rock-chips.com,
|
||||
eddie.cai@rock-chips.com, linux-arm-kernel@lists.infradead.org,
|
||||
Jernej Skrabec <jernej.skrabec@siol.net>, dianders@chromium.org,
|
||||
enric.balletbo@collabora.com, kuankuan.y@gmail.com
|
||||
Date: Wed, 11 Sep 2019 16:26:46 +0800
|
||||
|
||||
From: Yakir Yang <ykk@rock-chips.com>
|
||||
|
||||
When transmitting IEC60985 linear PCM audio, we configure the
|
||||
Aduio Sample Channel Status information in the IEC60958 frame.
|
||||
The status bit is already available in iec.status of hdmi_codec_params.
|
||||
|
||||
This fix the issue that audio does not come out on some monitors
|
||||
(e.g. LG 22CV241)
|
||||
|
||||
Note that these registers are only for interfaces:
|
||||
I2S audio interface, General Purpose Audio (GPA), or AHB audio DMA
|
||||
(AHBAUDDMA).
|
||||
For S/PDIF interface this information comes from the stream.
|
||||
|
||||
Currently this function dw_hdmi_set_channel_status is only called
|
||||
from dw-hdmi-i2s-audio in I2S setup.
|
||||
|
||||
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
|
||||
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
|
||||
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
|
||||
Change from v2 to v3:
|
||||
1. Reuse what is already set in iec.status in hw_param.
|
||||
2. Remove all useless definition of registers and values.
|
||||
3. Note that the original sampling frequency is not written to
|
||||
the channel status as we reuse create_iec958_consumer in pcm_iec958.c.
|
||||
Without that it can still play audio fine.
|
||||
|
||||
.../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 +
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 20 +++++++++++++++++++
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 2 ++
|
||||
include/drm/bridge/dw_hdmi.h | 1 +
|
||||
4 files changed, 24 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
index 34d8e837555f..20f4f92dd866 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
|
||||
@@ -102,6 +102,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
|
||||
}
|
||||
|
||||
dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
|
||||
+ dw_hdmi_set_channel_status(hdmi, hparms->iec.status);
|
||||
dw_hdmi_set_channel_count(hdmi, hparms->channels);
|
||||
dw_hdmi_set_channel_allocation(hdmi, hparms->cea.channel_allocation);
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
index bd65d0479683..aa7efd4da1c8 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
@@ -582,6 +582,26 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
|
||||
return n;
|
||||
}
|
||||
|
||||
+/*
|
||||
+ * When transmitting IEC60958 linear PCM audio, these registers allow to
|
||||
+ * configure the channel status information of all the channel status
|
||||
+ * bits in the IEC60958 frame. For the moment this configuration is only
|
||||
+ * used when the I2S audio interface, General Purpose Audio (GPA),
|
||||
+ * or AHB audio DMA (AHBAUDDMA) interface is active
|
||||
+ * (for S/PDIF interface this information comes from the stream).
|
||||
+ */
|
||||
+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
|
||||
+ u8 *channel_status)
|
||||
+{
|
||||
+ /*
|
||||
+ * Set channel status register for frequency and word length.
|
||||
+ * Use default values for other registers.
|
||||
+ */
|
||||
+ hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
|
||||
+ hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
|
||||
+
|
||||
static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
|
||||
unsigned long pixel_clk, unsigned int sample_rate)
|
||||
{
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
index 6988f12d89d9..fcff5059db24 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
@@ -158,6 +158,8 @@
|
||||
#define HDMI_FC_SPDDEVICEINF 0x1062
|
||||
#define HDMI_FC_AUDSCONF 0x1063
|
||||
#define HDMI_FC_AUDSSTAT 0x1064
|
||||
+#define HDMI_FC_AUDSCHNLS7 0x106e
|
||||
+#define HDMI_FC_AUDSCHNLS8 0x106f
|
||||
#define HDMI_FC_DATACH0FILL 0x1070
|
||||
#define HDMI_FC_DATACH1FILL 0x1071
|
||||
#define HDMI_FC_DATACH2FILL 0x1072
|
||||
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
|
||||
index cf528c289857..4b3e863c4f8a 100644
|
||||
--- a/include/drm/bridge/dw_hdmi.h
|
||||
+++ b/include/drm/bridge/dw_hdmi.h
|
||||
@@ -156,6 +156,7 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
|
||||
|
||||
void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
|
||||
void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt);
|
||||
+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status);
|
||||
void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca);
|
||||
void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
|
||||
void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
From 12c5dbdae16c4cd2d9914b7a4e31275f3d2070c6 Mon Sep 17 00:00:00 2001
|
||||
From: balbes150 <balbes-150@yandex.ru>
|
||||
Date: Mon, 18 Mar 2019 17:40:57 +0300
|
||||
Subject: [PATCH 69/91] fix
|
||||
|
||||
---
|
||||
drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c | 1 +
|
||||
drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c | 1 +
|
||||
drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 2 ++
|
||||
include/linux/mmc/sdio_ids.h | 1 +
|
||||
4 files changed, 5 insertions(+)
|
||||
|
||||
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
|
||||
index d64bf23..0e80530 100644
|
||||
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
|
||||
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
|
||||
@@ -982,6 +982,7 @@ static const struct sdio_device_id brcmf_sdmmc_ids[] = {
|
||||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43455),
|
||||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4354),
|
||||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4356),
|
||||
+ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4359),
|
||||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_CYPRESS_4373),
|
||||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_CYPRESS_43012),
|
||||
{ /* end: all zeroes */ }
|
||||
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
|
||||
index 22534bf..1461794 100644
|
||||
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
|
||||
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
|
||||
@@ -1348,6 +1348,7 @@ bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
|
||||
switch (pub->chip) {
|
||||
case BRCM_CC_4354_CHIP_ID:
|
||||
case BRCM_CC_4356_CHIP_ID:
|
||||
+ case BRCM_CC_4359_CHIP_ID:
|
||||
case BRCM_CC_4345_CHIP_ID:
|
||||
/* explicitly check SR engine enable bit */
|
||||
pmu_cc3_mask = BIT(2);
|
||||
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
|
||||
index 0cd5b8d..7809aa1 100644
|
||||
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
|
||||
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
|
||||
@@ -624,6 +624,7 @@ BRCMF_FW_DEF(43430A1, "brcmfmac43430-sdio");
|
||||
BRCMF_FW_DEF(43455, "brcmfmac43455-sdio");
|
||||
BRCMF_FW_DEF(4354, "brcmfmac4354-sdio");
|
||||
BRCMF_FW_DEF(4356, "brcmfmac4356-sdio");
|
||||
+BRCMF_FW_DEF(4359, "brcmfmac4359-sdio");
|
||||
BRCMF_FW_DEF(4373, "brcmfmac4373-sdio");
|
||||
BRCMF_FW_DEF(43012, "brcmfmac43012-sdio");
|
||||
|
||||
@@ -645,6 +646,7 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
|
||||
BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
|
||||
+ BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
|
||||
BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373),
|
||||
BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012)
|
||||
};
|
||||
diff --git a/include/linux/mmc/sdio_ids.h b/include/linux/mmc/sdio_ids.h
|
||||
index 4332199..93a5ac7 100644
|
||||
--- a/include/linux/mmc/sdio_ids.h
|
||||
+++ b/include/linux/mmc/sdio_ids.h
|
||||
@@ -41,6 +41,7 @@
|
||||
#define SDIO_DEVICE_ID_BROADCOM_43455 0xa9bf
|
||||
#define SDIO_DEVICE_ID_BROADCOM_4354 0x4354
|
||||
#define SDIO_DEVICE_ID_BROADCOM_4356 0x4356
|
||||
+#define SDIO_DEVICE_ID_BROADCOM_4359 0x4359
|
||||
#define SDIO_DEVICE_ID_CYPRESS_4373 0x4373
|
||||
#define SDIO_DEVICE_ID_CYPRESS_43012 43012
|
||||
|
||||
--
|
||||
2.7.4
|
||||
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
From 198ba00ac6a46645a083baad7ddca790a3a1cb94 Mon Sep 17 00:00:00 2001
|
||||
From: Nick <nick@khadas.com>
|
||||
Date: Mon, 25 Mar 2019 10:58:49 +0800
|
||||
Subject: [PATCH 78/91] VIM1: fixup btbcm
|
||||
|
||||
---
|
||||
drivers/bluetooth/btbcm.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/bluetooth/btbcm.c b/drivers/bluetooth/btbcm.c
|
||||
index d5d6e6e..244ca4d 100644
|
||||
--- a/drivers/bluetooth/btbcm.c
|
||||
+++ b/drivers/bluetooth/btbcm.c
|
||||
@@ -337,7 +337,7 @@ static const struct bcm_subver_table bcm_uart_subver_table[] = {
|
||||
{ 0x6109, "BCM4335C0" }, /* 003.001.009 */
|
||||
{ 0x610c, "BCM4354" }, /* 003.001.012 */
|
||||
{ 0x2122, "BCM4343A0" }, /* 001.001.034 */
|
||||
- { 0x2209, "BCM43430A1" }, /* 001.002.009 */
|
||||
+ { 0x2209, "BCM43438A1" }, /* 001.002.009 */
|
||||
{ 0x6119, "BCM4345C0" }, /* 003.001.025 */
|
||||
{ 0x230f, "BCM4356A2" }, /* 001.003.015 */
|
||||
{ 0x220e, "BCM20702A1" }, /* 001.002.014 */
|
||||
--
|
||||
2.7.4
|
||||
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
|
||||
index 1cc9dc6..9f48dff 100644
|
||||
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
|
||||
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
|
||||
@@ -16,6 +16,7 @@
|
||||
|
||||
aliases {
|
||||
serial0 = &uart_AO;
|
||||
+ serial1 = &uart_A;
|
||||
ethernet0 = ðmac;
|
||||
};
|
||||
|
||||
@@ -290,6 +355,12 @@
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
+&uart_A {
|
||||
+ status = "disabled";
|
||||
+ pinctrl-0 = <&uart_a_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+};
|
||||
+
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
phy-supply = <&usb_otg_pwr>;
|
||||
|
|
@ -1,8 +1,8 @@
|
|||
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
|
||||
index c3c875a73..55c7dd3f4 100644
|
||||
index 0916dcb..cbc03df 100644
|
||||
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
|
||||
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
|
||||
@@ -135,6 +135,32 @@
|
||||
@@ -116,6 +116,32 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -32,6 +32,6 @@ index c3c875a73..55c7dd3f4 100644
|
|||
+ spi-max-frequency = <500000>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
71
patch/kernel/meson64-current/drm_bridge_reuse_DDC.patch
Normal file
71
patch/kernel/meson64-current/drm_bridge_reuse_DDC.patch
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
From patchwork Wed Oct 2 19:44:06 2019
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v2] drm/bridge: dw-hdmi: Refuse DDC/CI transfers on the internal I2C controller
|
||||
From: Matthias Kaehlcke <mka@chromium.org>
|
||||
X-Patchwork-Id: 334046
|
||||
Message-Id: <20191002124354.v2.1.I709dfec496f5f0b44a7b61dcd4937924da8d8382@changeid>
|
||||
To: Archit Taneja <architt@codeaurora.org>, Andrzej Hajda <a.hajda@samsung.com>,
|
||||
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
|
||||
David Airlie <airlied@linux.ie>
|
||||
Cc: Jernej Skrabec <jernej.skrabec@siol.net>,
|
||||
Tzung-Bi Shih <tzungbi@chromium.org>,
|
||||
Neil Armstrong <narmstrong@baylibre.com>,
|
||||
Sean Paul <sean@poorly.run>, Douglas Anderson <dianders@chromium.org>,
|
||||
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
|
||||
Matthias Kaehlcke <mka@chromium.org>, Cheng-Yi Chiang <cychiang@chromium.org>,
|
||||
Yakir Yang <kuankuan.y@gmail.com>, Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Wed, 2 Oct 2019 12:44:06 -0700
|
||||
|
||||
The DDC/CI protocol involves sending a multi-byte request to the
|
||||
display via I2C, which is typically followed by a multi-byte
|
||||
response. The internal I2C controller only allows single byte
|
||||
reads/writes or reads of 8 sequential bytes, hence DDC/CI is not
|
||||
supported when the internal I2C controller is used. The I2C
|
||||
transfers complete without errors, however the data in the response
|
||||
is garbage. Abort transfers to/from slave address 0x37 (DDC) with
|
||||
-EOPNOTSUPP, to make it evident that the communication is failing.
|
||||
|
||||
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
|
||||
Reviewed-by: Douglas Anderson <dianders@chromium.org>
|
||||
Reviewed-by: Sean Paul <sean@poorly.run>
|
||||
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
---
|
||||
Sorry for the delay with sending v2, I completely forgot about this patch ...
|
||||
|
||||
Changes in v2:
|
||||
- updated comment with 'TOFIX' entry as requested by Neil
|
||||
- added Neil's 'Acked-by' tag
|
||||
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
index 52d220a70362..ac24bceaf415 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
@@ -41,6 +41,7 @@
|
||||
|
||||
#include <media/cec-notifier.h>
|
||||
|
||||
+#define DDC_CI_ADDR 0x37
|
||||
#define DDC_SEGMENT_ADDR 0x30
|
||||
|
||||
#define HDMI_EDID_LEN 512
|
||||
@@ -439,6 +440,15 @@ static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
|
||||
u8 addr = msgs[0].addr;
|
||||
int i, ret = 0;
|
||||
|
||||
+ if (addr == DDC_CI_ADDR)
|
||||
+ /*
|
||||
+ * The internal I2C controller does not support the multi-byte
|
||||
+ * read and write operations needed for DDC/CI.
|
||||
+ * TOFIX: Blacklist the DDC/CI address until we filter out
|
||||
+ * unsupported I2C operations.
|
||||
+ */
|
||||
+ return -EOPNOTSUPP;
|
||||
+
|
||||
dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
|
|
@ -6,8 +6,7 @@ Subject: [PATCH] general: meson64 overlays
|
|||
Signed-off-by: Zhang Ning <832666+zhangn1985@users.noreply.github.com>
|
||||
---
|
||||
arch/arm64/boot/dts/amlogic/Makefile | 2 ++
|
||||
arch/arm64/boot/dts/amlogic/Makefile.rej | 8 +++++
|
||||
arch/arm64/boot/dts/amlogic/overlay/Makefile | 20 ++++++++++++
|
||||
arch/arm64/boot/dts/amlogic/overlay/Makefile | 20 ++++++++++++
|
||||
.../dts/amlogic/overlay/README.meson-overlays | 20 ++++++++++++
|
||||
.../dts/amlogic/overlay/meson-fixup.scr-cmd | 4 +++
|
||||
.../boot/dts/amlogic/overlay/meson-i2cA.dts | 17 ++++++++++
|
||||
|
|
@ -18,7 +17,6 @@ Signed-off-by: Zhang Ning <832666+zhangn1985@users.noreply.github.com>
|
|||
.../dts/amlogic/overlay/meson-w1AB-gpio.dts | 32 +++++++++++++++++++
|
||||
scripts/Makefile.lib | 3 ++
|
||||
12 files changed, 165 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/amlogic/Makefile.rej
|
||||
create mode 100644 arch/arm64/boot/dts/amlogic/overlay/Makefile
|
||||
create mode 100644 arch/arm64/boot/dts/amlogic/overlay/README.meson-overlays
|
||||
create mode 100644 arch/arm64/boot/dts/amlogic/overlay/meson-fixup.scr-cmd
|
||||
|
|
@ -34,25 +32,11 @@ index 07b861f..9d12b15 100644
|
|||
--- a/arch/arm64/boot/dts/amlogic/Makefile
|
||||
+++ b/arch/arm64/boot/dts/amlogic/Makefile
|
||||
@@ -32,3 +32,5 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
|
||||
+
|
||||
+subdir-y := $(dts-dirs) overlay
|
||||
diff --git a/arch/arm64/boot/dts/amlogic/Makefile.rej b/arch/arm64/boot/dts/amlogic/Makefile.rej
|
||||
new file mode 100644
|
||||
index 000000000000..5a34b7af8dac
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/amlogic/Makefile.rej
|
||||
@@ -0,0 +1,8 @@
|
||||
+--- arch/arm64/boot/dts/amlogic/Makefile
|
||||
++++ arch/arm64/boot/dts/amlogic/Makefile
|
||||
+@@ -26,3 +26,5 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
|
||||
+ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
|
||||
+ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
|
||||
+ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
|
||||
++
|
||||
++subdir-y := $(dts-dirs) overlay
|
||||
diff --git a/arch/arm64/boot/dts/amlogic/overlay/Makefile b/arch/arm64/boot/dts/amlogic/overlay/Makefile
|
||||
new file mode 100644
|
||||
index 000000000000..8630fd1a182d
|
||||
|
|
|
|||
|
|
@ -0,0 +1,103 @@
|
|||
From c669757a7564c19d042bc5ac18199bb6f3f4e928 Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Date: Fri, 27 Sep 2019 15:16:38 +0200
|
||||
Subject: [PATCH] dwc3: add parkmode_disable_ss_quirk for G12A
|
||||
|
||||
Could you validate this fixes the following issue ?
|
||||
[ 221.141621] xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command.
|
||||
[ 221.157631] xhci-hcd xhci-hcd.0.auto: Host halt failed, -110
|
||||
[ 221.157635] xhci-hcd xhci-hcd.0.auto: xHCI host controller not responding, assume dead
|
||||
[ 221.159901] xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command.
|
||||
[ 221.159961] hub 2-1.1:1.0: hub_ext_port_status failed (err = -22)
|
||||
[ 221.160076] xhci-hcd xhci-hcd.0.auto: HC died; cleaning up
|
||||
[ 221.165946] usb 2-1.1-port1: cannot reset (err = -22)
|
||||
|
||||
Cc: Tim <elatllat@gmail.com>
|
||||
CC: Dongjin Kim <tobetter@gmail.com>
|
||||
Cc: Jianxin Pan <jianxin.pan@amlogic.com>
|
||||
CC: linux-amlogic@lists.infradead.org
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
---
|
||||
Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
|
||||
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 1 +
|
||||
drivers/usb/dwc3/core.c | 5 +++++
|
||||
drivers/usb/dwc3/core.h | 4 ++++
|
||||
4 files changed, 12 insertions(+)
|
||||
|
||||
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
|
||||
index 66780a47ad859..c977a3ba2f35c 100644
|
||||
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
|
||||
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
|
||||
@@ -75,6 +75,8 @@ Optional properties:
|
||||
from P0 to P1/P2/P3 without delay.
|
||||
- snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check
|
||||
during HS transmit.
|
||||
+ - snps,parkmode-disable-ss-quirk: when set, all SuperSpeed bus instances in
|
||||
+ park mode are disabled.
|
||||
- snps,dis_metastability_quirk: when set, disable metastability workaround.
|
||||
CAUTION: use only if you are absolutely sure of it.
|
||||
- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
|
||||
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
|
||||
index 852cf9cf121b8..139f24975c0e1 100644
|
||||
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
|
||||
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
|
||||
@@ -2401,6 +2401,7 @@
|
||||
dr_mode = "host";
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,quirk-frame-length-adjustment;
|
||||
+ snps,parkmode-disable-ss-quirk;
|
||||
};
|
||||
};
|
||||
|
||||
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
|
||||
index c9bb93a2c81e2..f64dba17a50db 100644
|
||||
--- a/drivers/usb/dwc3/core.c
|
||||
+++ b/drivers/usb/dwc3/core.c
|
||||
@@ -983,6 +983,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
|
||||
if (dwc->dis_tx_ipgap_linecheck_quirk)
|
||||
reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
|
||||
|
||||
+ if (dwc->parkmode_disable_ss_quirk)
|
||||
+ reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
|
||||
+
|
||||
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
|
||||
}
|
||||
|
||||
@@ -1294,6 +1297,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
|
||||
"snps,dis-del-phy-power-chg-quirk");
|
||||
dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
|
||||
"snps,dis-tx-ipgap-linecheck-quirk");
|
||||
+ dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
|
||||
+ "snps,parkmode-disable-ss-quirk");
|
||||
|
||||
dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
|
||||
"snps,tx_de_emphasis_quirk");
|
||||
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
|
||||
index 3dd783b889cb9..ab071163b3b82 100644
|
||||
--- a/drivers/usb/dwc3/core.h
|
||||
+++ b/drivers/usb/dwc3/core.h
|
||||
@@ -249,6 +249,7 @@
|
||||
#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
|
||||
|
||||
/* Global User Control 1 Register */
|
||||
+#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
|
||||
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
|
||||
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
|
||||
|
||||
@@ -1022,6 +1023,8 @@ struct dwc3_scratchpad_array {
|
||||
* change quirk.
|
||||
* @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
|
||||
* check during HS transmit.
|
||||
+ * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
|
||||
+ * instances in park mode.
|
||||
* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
|
||||
* @tx_de_emphasis: Tx de-emphasis value
|
||||
* 0 - -6dB de-emphasis
|
||||
@@ -1211,6 +1214,7 @@ struct dwc3 {
|
||||
unsigned dis_u2_freeclk_exists_quirk:1;
|
||||
unsigned dis_del_phy_power_chg_quirk:1;
|
||||
unsigned dis_tx_ipgap_linecheck_quirk:1;
|
||||
+ unsigned parkmode_disable_ss_quirk:1;
|
||||
|
||||
unsigned tx_de_emphasis_quirk:1;
|
||||
unsigned tx_de_emphasis:2;
|
||||
|
|
@ -0,0 +1,404 @@
|
|||
From patchwork Mon Oct 7 19:21:48 2019
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v2,1/4] drm/bridge: dw-hdmi: Add Dynamic Range and Mastering InfoFrame support
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
X-Patchwork-Id: 334756
|
||||
Message-Id: <HE1PR06MB4011D7B916CBF8B740ACC45FAC9B0@HE1PR06MB4011.eurprd06.prod.outlook.com>
|
||||
To: Andrzej Hajda <a.hajda@samsung.com>, Neil Armstrong <narmstrong@baylibre.com>
|
||||
Cc: Jernej Skrabec <jernej.skrabec@siol.net>, Jonas Karlman <jonas@kwiboo.se>,
|
||||
Kevin Hilman <khilman@baylibre.com>,
|
||||
"dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
|
||||
Maxime Ripard <mripard@kernel.org>,
|
||||
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
|
||||
Chen-Yu Tsai <wens@csie.org>,
|
||||
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
|
||||
"zhengyang@rock-chips.com" <zhengyang@rock-chips.com>
|
||||
Date: Mon, 7 Oct 2019 19:21:48 +0000
|
||||
|
||||
Add support for configuring Dynamic Range and Mastering InfoFrame from
|
||||
the hdr_output_metadata connector property.
|
||||
|
||||
This patch adds a use_drm_infoframe flag to dw_hdmi_plat_data that platform
|
||||
drivers use to signal when Dynamic Range and Mastering infoframes is supported.
|
||||
This flag is needed because Amlogic GXBB and GXL report same DW-HDMI version,
|
||||
and only GXL support DRM InfoFrame.
|
||||
|
||||
These changes were based on work done by Zheng Yang <zhengyang@rock-chips.com>
|
||||
to support DRM InfoFrame on the Rockchip 4.4 BSP kernel at [1] and [2]
|
||||
|
||||
[1] https://github.com/rockchip-linux/kernel/tree/develop-4.4
|
||||
[2] https://github.com/rockchip-linux/kernel/commit/d1943fde81ff41d7cca87f4a42f03992e90bddd5
|
||||
|
||||
Cc: Zheng Yang <zhengyang@rock-chips.com>
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 81 +++++++++++++++++++++++
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 37 +++++++++++
|
||||
include/drm/bridge/dw_hdmi.h | 1 +
|
||||
3 files changed, 119 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
index a15fbf71b9d7..fdc29869d75a 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
@@ -25,6 +25,7 @@
|
||||
#include <uapi/linux/videodev2.h>
|
||||
|
||||
#include <drm/bridge/dw_hdmi.h>
|
||||
+#include <drm/drm_atomic.h>
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#include <drm/drm_bridge.h>
|
||||
#include <drm/drm_edid.h>
|
||||
@@ -1743,6 +1744,41 @@ static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
|
||||
HDMI_FC_DATAUTO0_VSD_MASK);
|
||||
}
|
||||
|
||||
+static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi)
|
||||
+{
|
||||
+ const struct drm_connector_state *conn_state = hdmi->connector.state;
|
||||
+ struct hdmi_drm_infoframe frame;
|
||||
+ u8 buffer[30];
|
||||
+ ssize_t err;
|
||||
+ int i;
|
||||
+
|
||||
+ if (!hdmi->plat_data->use_drm_infoframe)
|
||||
+ return;
|
||||
+
|
||||
+ hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
|
||||
+ HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
|
||||
+
|
||||
+ err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
|
||||
+ if (err < 0)
|
||||
+ return;
|
||||
+
|
||||
+ err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
|
||||
+ if (err < 0) {
|
||||
+ dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
|
||||
+ hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
|
||||
+
|
||||
+ for (i = 0; i < frame.length; i++)
|
||||
+ hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
|
||||
+
|
||||
+ hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
|
||||
+ hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
|
||||
+ HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
|
||||
+}
|
||||
+
|
||||
static void hdmi_av_composer(struct dw_hdmi *hdmi,
|
||||
const struct drm_display_mode *mode)
|
||||
{
|
||||
@@ -2064,6 +2100,7 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
|
||||
/* HDMI Initialization Step F - Configure AVI InfoFrame */
|
||||
hdmi_config_AVI(hdmi, mode);
|
||||
hdmi_config_vendor_specific_infoframe(hdmi, mode);
|
||||
+ hdmi_config_drm_infoframe(hdmi);
|
||||
} else {
|
||||
dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
|
||||
}
|
||||
@@ -2230,6 +2267,45 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static bool hdr_metadata_equal(const struct drm_connector_state *old_state,
|
||||
+ const struct drm_connector_state *new_state)
|
||||
+{
|
||||
+ struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
|
||||
+ struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
|
||||
+
|
||||
+ if (!old_blob || !new_blob)
|
||||
+ return old_blob == new_blob;
|
||||
+
|
||||
+ if (old_blob->length != new_blob->length)
|
||||
+ return false;
|
||||
+
|
||||
+ return !memcmp(old_blob->data, new_blob->data, old_blob->length);
|
||||
+}
|
||||
+
|
||||
+static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
|
||||
+ struct drm_atomic_state *state)
|
||||
+{
|
||||
+ struct drm_connector_state *old_state =
|
||||
+ drm_atomic_get_old_connector_state(state, connector);
|
||||
+ struct drm_connector_state *new_state =
|
||||
+ drm_atomic_get_new_connector_state(state, connector);
|
||||
+ struct drm_crtc *crtc = new_state->crtc;
|
||||
+ struct drm_crtc_state *crtc_state;
|
||||
+
|
||||
+ if (!crtc)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (!hdr_metadata_equal(old_state, new_state)) {
|
||||
+ crtc_state = drm_atomic_get_crtc_state(state, crtc);
|
||||
+ if (IS_ERR(crtc_state))
|
||||
+ return PTR_ERR(crtc_state);
|
||||
+
|
||||
+ crtc_state->mode_changed = true;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static void dw_hdmi_connector_force(struct drm_connector *connector)
|
||||
{
|
||||
struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
|
||||
@@ -2254,6 +2330,7 @@ static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
|
||||
|
||||
static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
|
||||
.get_modes = dw_hdmi_connector_get_modes,
|
||||
+ .atomic_check = dw_hdmi_connector_atomic_check,
|
||||
};
|
||||
|
||||
static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
|
||||
@@ -2274,6 +2351,10 @@ static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
|
||||
DRM_MODE_CONNECTOR_HDMIA,
|
||||
hdmi->ddc);
|
||||
|
||||
+ if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
|
||||
+ drm_object_attach_property(&connector->base,
|
||||
+ connector->dev->mode_config.hdr_output_metadata_property, 0);
|
||||
+
|
||||
drm_connector_attach_encoder(connector, encoder);
|
||||
|
||||
cec_fill_conn_info_from_drm(&conn_info, connector);
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
index fcff5059db24..1999db05bc3b 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
|
||||
@@ -254,6 +254,7 @@
|
||||
#define HDMI_FC_POL2 0x10DB
|
||||
#define HDMI_FC_PRCONF 0x10E0
|
||||
#define HDMI_FC_SCRAMBLER_CTRL 0x10E1
|
||||
+#define HDMI_FC_PACKET_TX_EN 0x10E3
|
||||
|
||||
#define HDMI_FC_GMD_STAT 0x1100
|
||||
#define HDMI_FC_GMD_EN 0x1101
|
||||
@@ -289,6 +290,37 @@
|
||||
#define HDMI_FC_GMD_PB26 0x111F
|
||||
#define HDMI_FC_GMD_PB27 0x1120
|
||||
|
||||
+#define HDMI_FC_DRM_UP 0x1167
|
||||
+#define HDMI_FC_DRM_HB0 0x1168
|
||||
+#define HDMI_FC_DRM_HB1 0x1169
|
||||
+#define HDMI_FC_DRM_PB0 0x116A
|
||||
+#define HDMI_FC_DRM_PB1 0x116B
|
||||
+#define HDMI_FC_DRM_PB2 0x116C
|
||||
+#define HDMI_FC_DRM_PB3 0x116D
|
||||
+#define HDMI_FC_DRM_PB4 0x116E
|
||||
+#define HDMI_FC_DRM_PB5 0x116F
|
||||
+#define HDMI_FC_DRM_PB6 0x1170
|
||||
+#define HDMI_FC_DRM_PB7 0x1171
|
||||
+#define HDMI_FC_DRM_PB8 0x1172
|
||||
+#define HDMI_FC_DRM_PB9 0x1173
|
||||
+#define HDMI_FC_DRM_PB10 0x1174
|
||||
+#define HDMI_FC_DRM_PB11 0x1175
|
||||
+#define HDMI_FC_DRM_PB12 0x1176
|
||||
+#define HDMI_FC_DRM_PB13 0x1177
|
||||
+#define HDMI_FC_DRM_PB14 0x1178
|
||||
+#define HDMI_FC_DRM_PB15 0x1179
|
||||
+#define HDMI_FC_DRM_PB16 0x117A
|
||||
+#define HDMI_FC_DRM_PB17 0x117B
|
||||
+#define HDMI_FC_DRM_PB18 0x117C
|
||||
+#define HDMI_FC_DRM_PB19 0x117D
|
||||
+#define HDMI_FC_DRM_PB20 0x117E
|
||||
+#define HDMI_FC_DRM_PB21 0x117F
|
||||
+#define HDMI_FC_DRM_PB22 0x1180
|
||||
+#define HDMI_FC_DRM_PB23 0x1181
|
||||
+#define HDMI_FC_DRM_PB24 0x1182
|
||||
+#define HDMI_FC_DRM_PB25 0x1183
|
||||
+#define HDMI_FC_DRM_PB26 0x1184
|
||||
+
|
||||
#define HDMI_FC_DBGFORCE 0x1200
|
||||
#define HDMI_FC_DBGAUD0CH0 0x1201
|
||||
#define HDMI_FC_DBGAUD1CH0 0x1202
|
||||
@@ -744,6 +776,11 @@ enum {
|
||||
HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
|
||||
HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
|
||||
|
||||
+/* FC_PACKET_TX_EN field values */
|
||||
+ HDMI_FC_PACKET_TX_EN_DRM_MASK = 0x80,
|
||||
+ HDMI_FC_PACKET_TX_EN_DRM_ENABLE = 0x80,
|
||||
+ HDMI_FC_PACKET_TX_EN_DRM_DISABLE = 0x00,
|
||||
+
|
||||
/* FC_AVICONF0-FC_AVICONF3 field values */
|
||||
HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
|
||||
HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
|
||||
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
|
||||
index 4b3e863c4f8a..fbf3812c4326 100644
|
||||
--- a/include/drm/bridge/dw_hdmi.h
|
||||
+++ b/include/drm/bridge/dw_hdmi.h
|
||||
@@ -126,6 +126,7 @@ struct dw_hdmi_plat_data {
|
||||
const struct drm_display_mode *mode);
|
||||
unsigned long input_bus_format;
|
||||
unsigned long input_bus_encoding;
|
||||
+ bool use_drm_infoframe;
|
||||
|
||||
/* Vendor PHY support */
|
||||
const struct dw_hdmi_phy_ops *phy_ops;
|
||||
|
||||
From patchwork Mon Oct 7 19:21:49 2019
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v2,2/4] drm/rockchip: Enable DRM InfoFrame support on RK3328 and RK3399
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
X-Patchwork-Id: 334758
|
||||
Message-Id: <HE1PR06MB4011C9579CA6BBCD96C87810AC9B0@HE1PR06MB4011.eurprd06.prod.outlook.com>
|
||||
To: Andrzej Hajda <a.hajda@samsung.com>, Neil Armstrong <narmstrong@baylibre.com>
|
||||
Cc: Jernej Skrabec <jernej.skrabec@siol.net>, Jonas Karlman <jonas@kwiboo.se>,
|
||||
Kevin Hilman <khilman@baylibre.com>,
|
||||
"dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
|
||||
Maxime Ripard <mripard@kernel.org>,
|
||||
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
|
||||
Chen-Yu Tsai <wens@csie.org>,
|
||||
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
|
||||
"zhengyang@rock-chips.com" <zhengyang@rock-chips.com>
|
||||
Date: Mon, 7 Oct 2019 19:21:49 +0000
|
||||
|
||||
This patch enables Dynamic Range and Mastering InfoFrame on RK3328 and RK3399.
|
||||
|
||||
Cc: Sandy Huang <hjc@rock-chips.com>
|
||||
Cc: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
|
||||
---
|
||||
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
||||
index 906891b03a38..7f56d8c3491d 100644
|
||||
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
||||
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
||||
@@ -450,6 +450,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
|
||||
.phy_ops = &rk3328_hdmi_phy_ops,
|
||||
.phy_name = "inno_dw_hdmi_phy2",
|
||||
.phy_force_vendor = true,
|
||||
+ .use_drm_infoframe = true,
|
||||
};
|
||||
|
||||
static struct rockchip_hdmi_chip_data rk3399_chip_data = {
|
||||
@@ -464,6 +465,7 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
|
||||
.cur_ctr = rockchip_cur_ctr,
|
||||
.phy_config = rockchip_phy_config,
|
||||
.phy_data = &rk3399_chip_data,
|
||||
+ .use_drm_infoframe = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
|
||||
|
||||
From patchwork Mon Oct 7 19:21:50 2019
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v2,3/4] drm/meson: Enable DRM InfoFrame support on GXL, GXM and G12A
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
X-Patchwork-Id: 334759
|
||||
Message-Id: <HE1PR06MB4011BB614A49253FD074BCCBAC9B0@HE1PR06MB4011.eurprd06.prod.outlook.com>
|
||||
To: Andrzej Hajda <a.hajda@samsung.com>, Neil Armstrong <narmstrong@baylibre.com>
|
||||
Cc: Jernej Skrabec <jernej.skrabec@siol.net>, Jonas Karlman <jonas@kwiboo.se>,
|
||||
Kevin Hilman <khilman@baylibre.com>,
|
||||
"dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
|
||||
Maxime Ripard <mripard@kernel.org>,
|
||||
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
|
||||
Chen-Yu Tsai <wens@csie.org>,
|
||||
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
|
||||
"zhengyang@rock-chips.com" <zhengyang@rock-chips.com>
|
||||
Date: Mon, 7 Oct 2019 19:21:50 +0000
|
||||
|
||||
This patch enables Dynamic Range and Mastering InfoFrame on GXL, GXM and G12A.
|
||||
|
||||
Cc: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
---
|
||||
drivers/gpu/drm/meson/meson_dw_hdmi.c | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
|
||||
index 022286dc6ab2..3bb7ffe5fc39 100644
|
||||
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
|
||||
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
|
||||
@@ -977,6 +977,11 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
|
||||
dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
|
||||
dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709;
|
||||
|
||||
+ if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
|
||||
+ dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
|
||||
+ dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
|
||||
+ dw_plat_data->use_drm_infoframe = true;
|
||||
+
|
||||
platform_set_drvdata(pdev, meson_dw_hdmi);
|
||||
|
||||
meson_dw_hdmi->hdmi = dw_hdmi_bind(pdev, encoder,
|
||||
|
||||
From patchwork Mon Oct 7 19:21:51 2019
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v2,4/4] drm/sun4i: Enable DRM InfoFrame support on H6
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
X-Patchwork-Id: 334757
|
||||
Message-Id: <HE1PR06MB40119DBC0DAE7BA251DF7074AC9B0@HE1PR06MB4011.eurprd06.prod.outlook.com>
|
||||
To: Andrzej Hajda <a.hajda@samsung.com>, Neil Armstrong <narmstrong@baylibre.com>
|
||||
Cc: Jernej Skrabec <jernej.skrabec@siol.net>, Jonas Karlman <jonas@kwiboo.se>,
|
||||
Maxime Ripard <maxime.ripard@bootlin.com>,
|
||||
Kevin Hilman <khilman@baylibre.com>,
|
||||
"dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
|
||||
Maxime Ripard <mripard@kernel.org>,
|
||||
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
|
||||
Chen-Yu Tsai <wens@csie.org>,
|
||||
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
|
||||
"zhengyang@rock-chips.com" <zhengyang@rock-chips.com>
|
||||
Date: Mon, 7 Oct 2019 19:21:51 +0000
|
||||
|
||||
This patch enables Dynamic Range and Mastering InfoFrame on H6.
|
||||
|
||||
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
Cc: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
|
||||
---
|
||||
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 2 ++
|
||||
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 +
|
||||
2 files changed, 3 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
|
||||
index a44dca4b0219..e8a317d5ba19 100644
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
|
||||
@@ -226,6 +226,7 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
|
||||
sun8i_hdmi_phy_init(hdmi->phy);
|
||||
|
||||
plat_data->mode_valid = hdmi->quirks->mode_valid;
|
||||
+ plat_data->use_drm_infoframe = hdmi->quirks->use_drm_infoframe;
|
||||
sun8i_hdmi_phy_set_ops(hdmi->phy, plat_data);
|
||||
|
||||
platform_set_drvdata(pdev, hdmi);
|
||||
@@ -300,6 +301,7 @@ static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
|
||||
|
||||
static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
|
||||
.mode_valid = sun8i_dw_hdmi_mode_valid_h6,
|
||||
+ .use_drm_infoframe = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
|
||||
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
|
||||
index d707c9171824..8e64945167e9 100644
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
|
||||
@@ -179,6 +179,7 @@ struct sun8i_dw_hdmi_quirks {
|
||||
enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
|
||||
const struct drm_display_mode *mode);
|
||||
unsigned int set_rate : 1;
|
||||
+ unsigned int use_drm_infoframe : 1;
|
||||
};
|
||||
|
||||
struct sun8i_dw_hdmi {
|
||||
1945
patch/kernel/meson64-current/patch-5.4.1-2.patch
Normal file
1945
patch/kernel/meson64-current/patch-5.4.1-2.patch
Normal file
File diff suppressed because it is too large
Load diff
3227
patch/kernel/meson64-current/patch-5.4.2-3.patch
Normal file
3227
patch/kernel/meson64-current/patch-5.4.2-3.patch
Normal file
File diff suppressed because it is too large
Load diff
6230
patch/kernel/meson64-current/patch-5.4.3-4.patch
Normal file
6230
patch/kernel/meson64-current/patch-5.4.3-4.patch
Normal file
File diff suppressed because it is too large
Load diff
2510
patch/kernel/meson64-current/patch-5.4.4-5.patch
Normal file
2510
patch/kernel/meson64-current/patch-5.4.4-5.patch
Normal file
File diff suppressed because it is too large
Load diff
3420
patch/kernel/meson64-current/patch-5.4.5-6.patch
Normal file
3420
patch/kernel/meson64-current/patch-5.4.5-6.patch
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -1,26 +0,0 @@
|
|||
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
|
||||
index c9bb93a2c..8252923d8 100644
|
||||
--- a/drivers/usb/dwc3/core.c
|
||||
+++ b/drivers/usb/dwc3/core.c
|
||||
@@ -983,6 +983,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
|
||||
if (dwc->dis_tx_ipgap_linecheck_quirk)
|
||||
reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
|
||||
|
||||
+ reg |= (DWC3_GUCTL_NAKPERENHHS | DWC3_GUCTL_PARKMODEDISABLESS);
|
||||
+
|
||||
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
|
||||
}
|
||||
|
||||
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
|
||||
index 3dd783b88..ff09d19ee 100644
|
||||
--- a/drivers/usb/dwc3/core.h
|
||||
+++ b/drivers/usb/dwc3/core.h
|
||||
@@ -247,6 +247,8 @@
|
||||
|
||||
/* Global User Control Register */
|
||||
#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
|
||||
+#define DWC3_GUCTL_PARKMODEDISABLESS BIT(17)
|
||||
+#define DWC3_GUCTL_NAKPERENHHS BIT(18)
|
||||
|
||||
/* Global User Control 1 Register */
|
||||
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
From patchwork Wed Aug 28 13:23:11 2019
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [RESEND] drm/meson: vclk: use the correct G12A frac max value
|
||||
From: Neil Armstrong <narmstrong@baylibre.com>
|
||||
X-Patchwork-Id: 327555
|
||||
Message-Id: <20190828132311.23881-1-narmstrong@baylibre.com>
|
||||
To: dri-devel@lists.freedesktop.org
|
||||
Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
|
||||
linux-arm-kernel@lists.infradead.org,
|
||||
Neil Armstrong <narmstrong@baylibre.com>
|
||||
Date: Wed, 28 Aug 2019 15:23:11 +0200
|
||||
|
||||
When calculating the HDMI PLL settings for a DMT mode PHY frequency,
|
||||
use the correct max fractional PLL value for G12A VPU.
|
||||
|
||||
With this fix, we can finally setup the 1024x768-60 mode.
|
||||
|
||||
Fixes: 202b9808f8ed ("drm/meson: Add G12A Video Clock setup")
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
|
||||
---
|
||||
Fixed typo in commit log, 1024x76 => 1024x768
|
||||
|
||||
drivers/gpu/drm/meson/meson_vclk.c | 9 +++++++--
|
||||
1 file changed, 7 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
|
||||
index ac491a781952..f690793ae2d5 100644
|
||||
--- a/drivers/gpu/drm/meson/meson_vclk.c
|
||||
+++ b/drivers/gpu/drm/meson/meson_vclk.c
|
||||
@@ -638,13 +638,18 @@ static bool meson_hdmi_pll_validate_params(struct meson_drm *priv,
|
||||
if (frac >= HDMI_FRAC_MAX_GXBB)
|
||||
return false;
|
||||
} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
|
||||
- meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) ||
|
||||
- meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
|
||||
+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
|
||||
/* Empiric supported min/max dividers */
|
||||
if (m < 106 || m > 247)
|
||||
return false;
|
||||
if (frac >= HDMI_FRAC_MAX_GXL)
|
||||
return false;
|
||||
+ } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
|
||||
+ /* Empiric supported min/max dividers */
|
||||
+ if (m < 106 || m > 247)
|
||||
+ return false;
|
||||
+ if (frac >= HDMI_FRAC_MAX_G12A)
|
||||
+ return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
From 6cae25f4c3f9d4f124fceaa0350af3e181e027ea Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Date: Mon, 2 Jul 2018 12:21:55 +0200
|
||||
Subject: [PATCH] drm: bridge: dw-hdmi: Use AUTO CTS setup mode when non-AHB
|
||||
audio
|
||||
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 41 ++++++++++++++---------
|
||||
1 file changed, 26 insertions(+), 15 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
index 5971976284bf..1fc12708dbb5 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
@@ -430,8 +430,12 @@ static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
|
||||
/* nshift factor = 0 */
|
||||
hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
|
||||
|
||||
- hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
|
||||
- HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
|
||||
+ /* Use Auto CTS mode with CTS is unknown */
|
||||
+ if (cts)
|
||||
+ hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
|
||||
+ HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
|
||||
+ else
|
||||
+ hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
|
||||
hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
|
||||
hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
|
||||
|
||||
@@ -501,24 +505,31 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
|
||||
{
|
||||
unsigned long ftdms = pixel_clk;
|
||||
unsigned int n, cts;
|
||||
+ u8 config3;
|
||||
u64 tmp;
|
||||
|
||||
n = hdmi_compute_n(sample_rate, pixel_clk);
|
||||
|
||||
- /*
|
||||
- * Compute the CTS value from the N value. Note that CTS and N
|
||||
- * can be up to 20 bits in total, so we need 64-bit math. Also
|
||||
- * note that our TDMS clock is not fully accurate; it is accurate
|
||||
- * to kHz. This can introduce an unnecessary remainder in the
|
||||
- * calculation below, so we don't try to warn about that.
|
||||
- */
|
||||
- tmp = (u64)ftdms * n;
|
||||
- do_div(tmp, 128 * sample_rate);
|
||||
- cts = tmp;
|
||||
+ config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
|
||||
|
||||
- dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
|
||||
- __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
|
||||
- n, cts);
|
||||
+ if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
|
||||
+ /*
|
||||
+ * Compute the CTS value from the N value. Note that CTS and N
|
||||
+ * can be up to 20 bits in total, so we need 64-bit math. Also
|
||||
+ * note that our TDMS clock is not fully accurate; it is
|
||||
+ * accurate to kHz. This can introduce an unnecessary remainder
|
||||
+ * in the calculation below, so we don't try to warn about that.
|
||||
+ */
|
||||
+ tmp = (u64)ftdms * n;
|
||||
+ do_div(tmp, 128 * sample_rate);
|
||||
+ cts = tmp;
|
||||
+
|
||||
+ dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
|
||||
+ __func__, sample_rate,
|
||||
+ ftdms / 1000000, (ftdms / 1000) % 1000,
|
||||
+ n, cts);
|
||||
+ } else
|
||||
+ cts = 0;
|
||||
|
||||
spin_lock_irq(&hdmi->audio_lock);
|
||||
hdmi->audio_n = n;
|
||||
1
patch/kernel/meson64-dev
Symbolic link
1
patch/kernel/meson64-dev
Symbolic link
|
|
@ -0,0 +1 @@
|
|||
meson64-current
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
From 1cde4e7f788b4ace414c0d6274686a5812425a13 Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Date: Mon, 20 May 2019 15:37:49 +0200
|
||||
Subject: [PATCH 1/5] drm/bridge: dw-hdmi: allow ycbcr420 modes for >= 0x200a
|
||||
|
||||
Now the DW-HDMI Controller supports the HDMI2.0 modes, enable support
|
||||
for these modes in the connector if the platform supports them.
|
||||
We limit these modes to DW-HDMI IP version >= 0x200a which
|
||||
are designed to support HDMI2.0 display modes.
|
||||
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Tested-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 ++++++
|
||||
include/drm/bridge/dw_hdmi.h | 1 +
|
||||
2 files changed, 7 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
index c6490949d9db..8c273270d7ea 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
@@ -2719,6 +2719,12 @@ __dw_hdmi_probe(struct platform_device *pdev,
|
||||
hdmi->bridge.of_node = pdev->dev.of_node;
|
||||
#endif
|
||||
|
||||
+ if (hdmi->version >= 0x200a)
|
||||
+ hdmi->connector.ycbcr_420_allowed =
|
||||
+ hdmi->plat_data->ycbcr_420_allowed;
|
||||
+ else
|
||||
+ hdmi->connector.ycbcr_420_allowed = false;
|
||||
+
|
||||
memset(&pdevinfo, 0, sizeof(pdevinfo));
|
||||
pdevinfo.parent = dev;
|
||||
pdevinfo.id = PLATFORM_DEVID_AUTO;
|
||||
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
|
||||
index c402364aec0d..04e63ed29417 100644
|
||||
--- a/include/drm/bridge/dw_hdmi.h
|
||||
+++ b/include/drm/bridge/dw_hdmi.h
|
||||
@@ -126,6 +126,7 @@ struct dw_hdmi_plat_data {
|
||||
const struct drm_display_mode *mode);
|
||||
unsigned long input_bus_format;
|
||||
unsigned long input_bus_encoding;
|
||||
+ bool ycbcr_420_allowed;
|
||||
|
||||
/* Vendor PHY support */
|
||||
const struct dw_hdmi_phy_ops *phy_ops;
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
From 057c57825bba67e0d72c19d76a11de9da803db30 Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Date: Mon, 20 May 2019 15:37:50 +0200
|
||||
Subject: [PATCH 2/5] drm/bridge: add encoder support to specify bridge input
|
||||
format
|
||||
|
||||
This patch adds a new format_set() callback to the bridge ops permitting
|
||||
the encoder to specify the new input format and encoding.
|
||||
|
||||
This allows supporting the very specific HDMI2.0 YUV420 output mode
|
||||
when the bridge cannot convert from RGB or YUV444 to YUV420.
|
||||
|
||||
In this case, the encode must downsample before the bridge and must
|
||||
specify the bridge the new input bus format differs.
|
||||
|
||||
This will also help supporting the YUV420 mode where the bridge cannot
|
||||
downsample, and also support 10bit, 12bit and 16bit output modes
|
||||
when the bridge cannot convert between different bit depths.
|
||||
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
---
|
||||
drivers/gpu/drm/drm_bridge.c | 35 +++++++++++++++++++++++++++++++++++
|
||||
include/drm/drm_bridge.h | 19 +++++++++++++++++++
|
||||
2 files changed, 54 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
|
||||
index cba537c99e43..a4458dbfe302 100644
|
||||
--- a/drivers/gpu/drm/drm_bridge.c
|
||||
+++ b/drivers/gpu/drm/drm_bridge.c
|
||||
@@ -307,6 +307,41 @@ void drm_bridge_mode_set(struct drm_bridge *bridge,
|
||||
}
|
||||
EXPORT_SYMBOL(drm_bridge_mode_set);
|
||||
|
||||
+/**
|
||||
+ * drm_bridge_format_set - setup with proposed input format and encoding for
|
||||
+ * all bridges in the encoder chain
|
||||
+ * @bridge: bridge control structure
|
||||
+ * @input_bus_format: proposed input bus format for the bridge
|
||||
+ * @input_encoding: proposed input encoding for this bridge
|
||||
+ *
|
||||
+ * Calls &drm_bridge_funcs.format_set op for all the bridges in the
|
||||
+ * encoder chain, starting from the first bridge to the last.
|
||||
+ *
|
||||
+ * Note: the bridge passed should be the one closest to the encoder
|
||||
+ *
|
||||
+ * RETURNS:
|
||||
+ * true on success, false if one of the bridge cannot handle the format
|
||||
+ */
|
||||
+bool drm_bridge_format_set(struct drm_bridge *bridge,
|
||||
+ const u32 input_bus_format,
|
||||
+ const u32 input_encoding)
|
||||
+{
|
||||
+ bool ret = true;
|
||||
+
|
||||
+ if (!bridge)
|
||||
+ return true;
|
||||
+
|
||||
+ if (bridge->funcs->format_set)
|
||||
+ ret = bridge->funcs->format_set(bridge, input_bus_format,
|
||||
+ input_encoding);
|
||||
+ if (!ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ return drm_bridge_format_set(bridge->next, input_bus_format,
|
||||
+ input_encoding);
|
||||
+}
|
||||
+EXPORT_SYMBOL(drm_bridge_format_set);
|
||||
+
|
||||
/**
|
||||
* drm_bridge_pre_enable - prepares for enabling all
|
||||
* bridges in the encoder chain
|
||||
diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
|
||||
index 7616f6562fe4..161026c9b908 100644
|
||||
--- a/include/drm/drm_bridge.h
|
||||
+++ b/include/drm/drm_bridge.h
|
||||
@@ -198,6 +198,22 @@ struct drm_bridge_funcs {
|
||||
void (*mode_set)(struct drm_bridge *bridge,
|
||||
const struct drm_display_mode *mode,
|
||||
const struct drm_display_mode *adjusted_mode);
|
||||
+
|
||||
+ /**
|
||||
+ * @format_set:
|
||||
+ *
|
||||
+ * This callback should configure the bridge for the given input bus
|
||||
+ * format and encoding. It is called after the @format_set callback
|
||||
+ * for the preceding element in the display pipeline has been called
|
||||
+ * already. If the bridge is the first element then this would be
|
||||
+ * &drm_encoder_helper_funcs.format_set. The display pipe (i.e.
|
||||
+ * clocks and timing signals) is off when this function is called.
|
||||
+ *
|
||||
+ * @returns: true in success, false is a bridge refuses the format
|
||||
+ */
|
||||
+ bool (*format_set)(struct drm_bridge *bridge,
|
||||
+ const u32 input_bus_format,
|
||||
+ const u32 input_encoding);
|
||||
/**
|
||||
* @pre_enable:
|
||||
*
|
||||
@@ -416,6 +432,9 @@ void drm_bridge_post_disable(struct drm_bridge *bridge);
|
||||
void drm_bridge_mode_set(struct drm_bridge *bridge,
|
||||
const struct drm_display_mode *mode,
|
||||
const struct drm_display_mode *adjusted_mode);
|
||||
+bool drm_bridge_format_set(struct drm_bridge *bridge,
|
||||
+ const u32 input_bus_format,
|
||||
+ const u32 input_encoding);
|
||||
void drm_bridge_pre_enable(struct drm_bridge *bridge);
|
||||
void drm_bridge_enable(struct drm_bridge *bridge);
|
||||
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,209 +0,0 @@
|
|||
From e42e927075a310f92aa5b2d7861c5ddde84a704a Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Date: Mon, 20 May 2019 15:37:51 +0200
|
||||
Subject: [PATCH 3/5] drm/bridge: dw-hdmi: Add support for dynamic output
|
||||
format setup
|
||||
|
||||
In order to support the HDMI2.0 YUV420, YUV422 and the 10bit, 12bit and
|
||||
16bits outpu use cases, add support for the recently introduced bridge
|
||||
callback format_set().
|
||||
|
||||
This callback will setup the new input format and encoding from encoder,
|
||||
then these information will be used instead of the default ones
|
||||
in the dw_hdmi_setup() function.
|
||||
|
||||
To determine the output bus format, has been added :
|
||||
- support for the connector display_info bus_formats, where a fixed
|
||||
output bus format can be enforced by the encoder
|
||||
- support for synami output bus format depending on the input format,
|
||||
especially the YUV420 input bus format, enforcing YUV420 as output
|
||||
with the correct bit depth
|
||||
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 121 ++++++++++++++++++++--
|
||||
1 file changed, 112 insertions(+), 9 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
index 8c273270d7ea..eb02191d9f88 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
@@ -100,6 +100,8 @@ struct hdmi_vmode {
|
||||
};
|
||||
|
||||
struct hdmi_data_info {
|
||||
+ unsigned int bridge_in_bus_format;
|
||||
+ unsigned int bridge_in_encoding;
|
||||
unsigned int enc_in_bus_format;
|
||||
unsigned int enc_out_bus_format;
|
||||
unsigned int enc_in_encoding;
|
||||
@@ -1909,8 +1911,51 @@ static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
|
||||
HDMI_IH_MUTE_FC_STAT2);
|
||||
}
|
||||
|
||||
+/*
|
||||
+ * The DW-HDMI CSC can only interpolate and decimate from 4:2:2 to 4:4:4/RGB
|
||||
+ * and from 4:4:4/RGB to 4:2:2.
|
||||
+ * Default to RGB output except if 4:2:0 as input, which CSC cannot convert.
|
||||
+ */
|
||||
+static unsigned long dw_hdmi_determine_output_bus_format(struct dw_hdmi *hdmi)
|
||||
+{
|
||||
+ unsigned int depth = hdmi_bus_fmt_color_depth(
|
||||
+ hdmi->hdmi_data.enc_in_bus_format);
|
||||
+ bool is_420 = hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_in_bus_format);
|
||||
+ unsigned long fmt = MEDIA_BUS_FMT_RGB888_1X24;
|
||||
+
|
||||
+ switch (depth) {
|
||||
+ case 8:
|
||||
+ if (is_420)
|
||||
+ fmt = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
|
||||
+ else
|
||||
+ fmt = MEDIA_BUS_FMT_RGB888_1X24;
|
||||
+ break;
|
||||
+ case 10:
|
||||
+ if (is_420)
|
||||
+ fmt = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
|
||||
+ else
|
||||
+ fmt = MEDIA_BUS_FMT_RGB101010_1X30;
|
||||
+ break;
|
||||
+ case 12:
|
||||
+ if (is_420)
|
||||
+ fmt = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
|
||||
+ else
|
||||
+ fmt = MEDIA_BUS_FMT_RGB121212_1X36;
|
||||
+ break;
|
||||
+ case 16:
|
||||
+ if (is_420)
|
||||
+ fmt = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
|
||||
+ else
|
||||
+ fmt = MEDIA_BUS_FMT_RGB161616_1X48;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return fmt;
|
||||
+}
|
||||
+
|
||||
static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
|
||||
{
|
||||
+ struct drm_display_info *display = &hdmi->connector.display_info;
|
||||
int ret;
|
||||
|
||||
hdmi_disable_overflow_interrupts(hdmi);
|
||||
@@ -1924,9 +1969,9 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
|
||||
}
|
||||
|
||||
if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
|
||||
- (hdmi->vic == 21) || (hdmi->vic == 22) ||
|
||||
- (hdmi->vic == 2) || (hdmi->vic == 3) ||
|
||||
- (hdmi->vic == 17) || (hdmi->vic == 18))
|
||||
+ (hdmi->vic == 21) || (hdmi->vic == 22) ||
|
||||
+ (hdmi->vic == 2) || (hdmi->vic == 3) ||
|
||||
+ (hdmi->vic == 17) || (hdmi->vic == 18))
|
||||
hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
|
||||
else
|
||||
hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
|
||||
@@ -1934,22 +1979,29 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
|
||||
hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
|
||||
hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
|
||||
|
||||
- /* TOFIX: Get input format from plat data or fallback to RGB888 */
|
||||
- if (hdmi->plat_data->input_bus_format)
|
||||
+ if (hdmi->hdmi_data.bridge_in_bus_format)
|
||||
+ hdmi->hdmi_data.enc_in_bus_format =
|
||||
+ hdmi->hdmi_data.bridge_in_bus_format;
|
||||
+ else if (hdmi->plat_data->input_bus_format)
|
||||
hdmi->hdmi_data.enc_in_bus_format =
|
||||
hdmi->plat_data->input_bus_format;
|
||||
else
|
||||
hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
|
||||
|
||||
- /* TOFIX: Get input encoding from plat data or fallback to none */
|
||||
- if (hdmi->plat_data->input_bus_encoding)
|
||||
+ if (hdmi->hdmi_data.bridge_in_encoding)
|
||||
+ hdmi->hdmi_data.enc_in_encoding =
|
||||
+ hdmi->hdmi_data.bridge_in_encoding;
|
||||
+ else if (hdmi->plat_data->input_bus_encoding)
|
||||
hdmi->hdmi_data.enc_in_encoding =
|
||||
hdmi->plat_data->input_bus_encoding;
|
||||
else
|
||||
hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
|
||||
|
||||
- /* TOFIX: Default to RGB888 output format */
|
||||
- hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
|
||||
+ if (display->num_bus_formats)
|
||||
+ hdmi->hdmi_data.enc_out_bus_format = display->bus_formats[0];
|
||||
+ else
|
||||
+ hdmi->hdmi_data.enc_out_bus_format =
|
||||
+ dw_hdmi_determine_output_bus_format(hdmi);
|
||||
|
||||
hdmi->hdmi_data.pix_repet_factor = 0;
|
||||
hdmi->hdmi_data.hdcp_enable = 0;
|
||||
@@ -2211,6 +2263,56 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
|
||||
return mode_status;
|
||||
}
|
||||
|
||||
+static bool dw_hdmi_drm_bridge_format_set(struct drm_bridge *bridge,
|
||||
+ const u32 input_bus_format,
|
||||
+ const u32 input_encoding)
|
||||
+{
|
||||
+ struct dw_hdmi *hdmi = bridge->driver_private;
|
||||
+
|
||||
+ /* Filter supported input bus formats */
|
||||
+ switch (input_bus_format) {
|
||||
+ case MEDIA_BUS_FMT_RGB888_1X24:
|
||||
+ case MEDIA_BUS_FMT_RGB101010_1X30:
|
||||
+ case MEDIA_BUS_FMT_RGB121212_1X36:
|
||||
+ case MEDIA_BUS_FMT_RGB161616_1X48:
|
||||
+ case MEDIA_BUS_FMT_YUV8_1X24:
|
||||
+ case MEDIA_BUS_FMT_YUV10_1X30:
|
||||
+ case MEDIA_BUS_FMT_YUV12_1X36:
|
||||
+ case MEDIA_BUS_FMT_YUV16_1X48:
|
||||
+ case MEDIA_BUS_FMT_UYVY8_1X16:
|
||||
+ case MEDIA_BUS_FMT_UYVY10_1X20:
|
||||
+ case MEDIA_BUS_FMT_UYVY12_1X24:
|
||||
+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
|
||||
+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
|
||||
+ case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
|
||||
+ case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_dbg(hdmi->dev, "Unsupported Input bus format %x\n",
|
||||
+ input_bus_format);
|
||||
+ return false;
|
||||
+ }
|
||||
+
|
||||
+ /* Filter supported input bus encoding */
|
||||
+ switch (input_encoding) {
|
||||
+ case V4L2_YCBCR_ENC_DEFAULT:
|
||||
+ case V4L2_YCBCR_ENC_601:
|
||||
+ case V4L2_YCBCR_ENC_709:
|
||||
+ case V4L2_YCBCR_ENC_XV601:
|
||||
+ case V4L2_YCBCR_ENC_XV709:
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_dbg(hdmi->dev, "Unsupported Input encoding %x\n",
|
||||
+ input_bus_format);
|
||||
+ return false;
|
||||
+ }
|
||||
+
|
||||
+ hdmi->hdmi_data.bridge_in_bus_format = input_bus_format;
|
||||
+ hdmi->hdmi_data.bridge_in_encoding = input_encoding;
|
||||
+
|
||||
+ return true;
|
||||
+}
|
||||
+
|
||||
static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
|
||||
const struct drm_display_mode *orig_mode,
|
||||
const struct drm_display_mode *mode)
|
||||
@@ -2253,6 +2355,7 @@ static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
|
||||
.disable = dw_hdmi_bridge_disable,
|
||||
.mode_set = dw_hdmi_bridge_mode_set,
|
||||
.mode_valid = dw_hdmi_bridge_mode_valid,
|
||||
+ .format_set = dw_hdmi_drm_bridge_format_set,
|
||||
};
|
||||
|
||||
static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,570 +0,0 @@
|
|||
From e04bc0e4e7ea1f75e9d99f830a3e48bde08f976f Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Date: Mon, 20 May 2019 15:37:52 +0200
|
||||
Subject: [PATCH 4/5] drm/meson: Add YUV420 output support
|
||||
|
||||
This patch adds support for the YUV420 output from the Amlogic Meson SoCs
|
||||
Video Processing Unit to the HDMI Controller.
|
||||
|
||||
The YUV420 is obtained by generating a YUV444 pixel stream like
|
||||
the classic HDMI display modes, but then the Video Encoder output
|
||||
can be configured to down-sample the YUV444 pixel stream to a YUV420
|
||||
stream.
|
||||
In addition if pixel stream down-sampling, the Y Cb Cr components must
|
||||
also be mapped differently to align with the HDMI2.0 specifications.
|
||||
|
||||
This mode needs a different clock generation scheme since the TMDS PHY
|
||||
clock must match the 10x ration with the YUV420 pixel clock, but
|
||||
the video encoder must run at 2x the pixel clock.
|
||||
|
||||
This patch adds the TMDS PHY clock value in all the video clock setup
|
||||
in order to better support these specific uses cases and switch
|
||||
to the Common Clock framework for clocks handling in the future.
|
||||
|
||||
When 420 is needed, it calls drm_bridge_format_set() for notify the
|
||||
bridge the input format has changed to YUV420.
|
||||
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
|
||||
---
|
||||
drivers/gpu/drm/meson/meson_dw_hdmi.c | 100 +++++++++++++++++++-----
|
||||
drivers/gpu/drm/meson/meson_vclk.c | 93 ++++++++++++++++------
|
||||
drivers/gpu/drm/meson/meson_vclk.h | 7 +-
|
||||
drivers/gpu/drm/meson/meson_venc.c | 6 +-
|
||||
drivers/gpu/drm/meson/meson_venc.h | 11 +++
|
||||
drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +-
|
||||
6 files changed, 174 insertions(+), 46 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
|
||||
index df3f9ddd2234..2ccee05de04a 100644
|
||||
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
|
||||
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
|
||||
@@ -147,6 +147,7 @@ struct meson_dw_hdmi {
|
||||
struct regulator *hdmi_supply;
|
||||
u32 irq_stat;
|
||||
struct dw_hdmi *hdmi;
|
||||
+ unsigned long input_bus_format;
|
||||
};
|
||||
#define encoder_to_meson_dw_hdmi(x) \
|
||||
container_of(x, struct meson_dw_hdmi, encoder)
|
||||
@@ -296,6 +297,10 @@ static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi,
|
||||
struct meson_drm *priv = dw_hdmi->priv;
|
||||
unsigned int pixel_clock = mode->clock;
|
||||
|
||||
+ /* For 420, pixel clock is half unlike venc clock */
|
||||
+ if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24)
|
||||
+ pixel_clock /= 2;
|
||||
+
|
||||
if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
|
||||
dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) {
|
||||
if (pixel_clock >= 371250) {
|
||||
@@ -371,25 +376,36 @@ static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi,
|
||||
{
|
||||
struct meson_drm *priv = dw_hdmi->priv;
|
||||
int vic = drm_match_cea_mode(mode);
|
||||
+ unsigned int phy_freq;
|
||||
unsigned int vclk_freq;
|
||||
unsigned int venc_freq;
|
||||
unsigned int hdmi_freq;
|
||||
|
||||
vclk_freq = mode->clock;
|
||||
|
||||
+ /* For 420, pixel clock is half unlike venc clock */
|
||||
+ if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24)
|
||||
+ vclk_freq /= 2;
|
||||
+
|
||||
+ /* TMDS clock is pixel_clock * 10 */
|
||||
+ phy_freq = vclk_freq * 10;
|
||||
+
|
||||
if (!vic) {
|
||||
- meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, vclk_freq,
|
||||
- vclk_freq, vclk_freq, false);
|
||||
+ meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, phy_freq,
|
||||
+ vclk_freq, vclk_freq, vclk_freq, false);
|
||||
return;
|
||||
}
|
||||
|
||||
+ /* 480i/576i needs global pixel doubling */
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
|
||||
vclk_freq *= 2;
|
||||
|
||||
venc_freq = vclk_freq;
|
||||
hdmi_freq = vclk_freq;
|
||||
|
||||
- if (meson_venc_hdmi_venc_repeat(vic))
|
||||
+ /* VENC double pixels for 1080i, 720p and YUV420 modes */
|
||||
+ if (meson_venc_hdmi_venc_repeat(vic) ||
|
||||
+ dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24)
|
||||
venc_freq *= 2;
|
||||
|
||||
vclk_freq = max(venc_freq, hdmi_freq);
|
||||
@@ -397,11 +413,11 @@ static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi,
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
|
||||
venc_freq /= 2;
|
||||
|
||||
- DRM_DEBUG_DRIVER("vclk:%d venc=%d hdmi=%d enci=%d\n",
|
||||
- vclk_freq, venc_freq, hdmi_freq,
|
||||
+ DRM_DEBUG_DRIVER("vclk:%d phy=%d venc=%d hdmi=%d enci=%d\n",
|
||||
+ phy_freq, vclk_freq, venc_freq, hdmi_freq,
|
||||
priv->venc.hdmi_use_enci);
|
||||
|
||||
- meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, vclk_freq,
|
||||
+ meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, phy_freq, vclk_freq,
|
||||
venc_freq, hdmi_freq, priv->venc.hdmi_use_enci);
|
||||
}
|
||||
|
||||
@@ -434,8 +450,9 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
|
||||
/* Enable normal output to PHY */
|
||||
dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
|
||||
|
||||
- /* TMDS pattern setup (TOFIX Handle the YUV420 case) */
|
||||
- if (mode->clock > 340000) {
|
||||
+ /* TMDS pattern setup */
|
||||
+ if (mode->clock > 340000 &&
|
||||
+ dw_hdmi->input_bus_format == MEDIA_BUS_FMT_YUV8_1X24) {
|
||||
dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
|
||||
0);
|
||||
dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
|
||||
@@ -610,6 +627,8 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
|
||||
const struct drm_display_mode *mode)
|
||||
{
|
||||
struct meson_drm *priv = connector->dev->dev_private;
|
||||
+ bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
|
||||
+ unsigned int phy_freq;
|
||||
unsigned int vclk_freq;
|
||||
unsigned int venc_freq;
|
||||
unsigned int hdmi_freq;
|
||||
@@ -618,9 +637,11 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
|
||||
|
||||
DRM_DEBUG_DRIVER("Modeline " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));
|
||||
|
||||
- /* If sink max TMDS clock, we reject the mode */
|
||||
+ /* If sink does not support 540MHz, reject the non-420 HDMI2 modes */
|
||||
if (connector->display_info.max_tmds_clock &&
|
||||
- mode->clock > connector->display_info.max_tmds_clock)
|
||||
+ mode->clock > connector->display_info.max_tmds_clock &&
|
||||
+ !drm_mode_is_420_only(&connector->display_info, mode) &&
|
||||
+ !drm_mode_is_420_also(&connector->display_info, mode))
|
||||
return MODE_BAD;
|
||||
|
||||
/* Check against non-VIC supported modes */
|
||||
@@ -636,6 +657,15 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
|
||||
|
||||
vclk_freq = mode->clock;
|
||||
|
||||
+ /* For 420, pixel clock is half unlike venc clock */
|
||||
+ if (drm_mode_is_420_only(&connector->display_info, mode) ||
|
||||
+ (!is_hdmi2_sink &&
|
||||
+ drm_mode_is_420_also(&connector->display_info, mode)))
|
||||
+ vclk_freq /= 2;
|
||||
+
|
||||
+ /* TMDS clock is pixel_clock * 10 */
|
||||
+ phy_freq = vclk_freq * 10;
|
||||
+
|
||||
/* 480i/576i needs global pixel doubling */
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
|
||||
vclk_freq *= 2;
|
||||
@@ -643,8 +673,11 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
|
||||
venc_freq = vclk_freq;
|
||||
hdmi_freq = vclk_freq;
|
||||
|
||||
- /* VENC double pixels for 1080i and 720p modes */
|
||||
- if (meson_venc_hdmi_venc_repeat(vic))
|
||||
+ /* VENC double pixels for 1080i, 720p and YUV420 modes */
|
||||
+ if (meson_venc_hdmi_venc_repeat(vic) ||
|
||||
+ drm_mode_is_420_only(&connector->display_info, mode) ||
|
||||
+ (!is_hdmi2_sink &&
|
||||
+ drm_mode_is_420_also(&connector->display_info, mode)))
|
||||
venc_freq *= 2;
|
||||
|
||||
vclk_freq = max(venc_freq, hdmi_freq);
|
||||
@@ -652,10 +685,10 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
|
||||
venc_freq /= 2;
|
||||
|
||||
- dev_dbg(connector->dev->dev, "%s: vclk:%d venc=%d hdmi=%d\n", __func__,
|
||||
- vclk_freq, venc_freq, hdmi_freq);
|
||||
+ dev_dbg(connector->dev->dev, "%s: vclk:%d phy=%d venc=%d hdmi=%d\n",
|
||||
+ __func__, phy_freq, vclk_freq, venc_freq, hdmi_freq);
|
||||
|
||||
- return meson_vclk_vic_supported_freq(vclk_freq);
|
||||
+ return meson_vclk_vic_supported_freq(phy_freq, vclk_freq);
|
||||
}
|
||||
|
||||
/* Encoder */
|
||||
@@ -673,6 +706,24 @@ static int meson_venc_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
+ struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder);
|
||||
+ struct drm_display_info *info = &conn_state->connector->display_info;
|
||||
+ struct drm_display_mode *mode = &crtc_state->mode;
|
||||
+ bool is_hdmi2_sink =
|
||||
+ conn_state->connector->display_info.hdmi.scdc.supported;
|
||||
+
|
||||
+ if (drm_mode_is_420_only(info, mode) ||
|
||||
+ (!is_hdmi2_sink && drm_mode_is_420_also(info, mode)))
|
||||
+ dw_hdmi->input_bus_format = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
|
||||
+ else
|
||||
+ dw_hdmi->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
|
||||
+
|
||||
+ /* Specify the encoder output format to the bridge */
|
||||
+ if (!drm_bridge_format_set(encoder->bridge,
|
||||
+ dw_hdmi->input_bus_format,
|
||||
+ V4L2_YCBCR_ENC_709))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -710,17 +761,29 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder,
|
||||
struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder);
|
||||
struct meson_drm *priv = dw_hdmi->priv;
|
||||
int vic = drm_match_cea_mode(mode);
|
||||
+ unsigned int ycrcb_map = MESON_VENC_MAP_CB_Y_CR;
|
||||
+ bool yuv420_mode = false;
|
||||
|
||||
DRM_DEBUG_DRIVER("\"%s\" vic %d\n", mode->name, vic);
|
||||
|
||||
+ if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24) {
|
||||
+ ycrcb_map = MESON_VENC_MAP_CR_Y_CB;
|
||||
+ yuv420_mode = true;
|
||||
+ }
|
||||
+
|
||||
/* VENC + VENC-DVI Mode setup */
|
||||
- meson_venc_hdmi_mode_set(priv, vic, mode);
|
||||
+ meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, yuv420_mode, mode);
|
||||
|
||||
/* VCLK Set clock */
|
||||
dw_hdmi_set_vclk(dw_hdmi, mode);
|
||||
|
||||
- /* Setup YUV444 to HDMI-TX, no 10bit diphering */
|
||||
- writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
|
||||
+ if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24)
|
||||
+ /* Setup YUV420 to HDMI-TX, no 10bit diphering */
|
||||
+ writel_relaxed(2 | (2 << 2),
|
||||
+ priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
|
||||
+ else
|
||||
+ /* Setup YUV444 to HDMI-TX, no 10bit diphering */
|
||||
+ writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs
|
||||
@@ -965,6 +1028,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
|
||||
dw_plat_data->phy_data = meson_dw_hdmi;
|
||||
dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
|
||||
dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709;
|
||||
+ dw_plat_data->ycbcr_420_allowed = true;
|
||||
|
||||
platform_set_drvdata(pdev, meson_dw_hdmi);
|
||||
|
||||
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
|
||||
index 26732f038d19..72100869f879 100644
|
||||
--- a/drivers/gpu/drm/meson/meson_vclk.c
|
||||
+++ b/drivers/gpu/drm/meson/meson_vclk.c
|
||||
@@ -352,12 +352,17 @@ enum {
|
||||
/* 2970 /1 /1 /1 /5 /2 => /1 /1 */
|
||||
MESON_VCLK_HDMI_297000,
|
||||
/* 5940 /1 /1 /2 /5 /1 => /1 /1 */
|
||||
- MESON_VCLK_HDMI_594000
|
||||
+ MESON_VCLK_HDMI_594000,
|
||||
+/* 2970 /1 /1 /1 /5 /1 => /1 /2 */
|
||||
+ MESON_VCLK_HDMI_594000_YUV420,
|
||||
};
|
||||
|
||||
struct meson_vclk_params {
|
||||
+ unsigned int pll_freq;
|
||||
+ unsigned int phy_freq;
|
||||
+ unsigned int vclk_freq;
|
||||
+ unsigned int venc_freq;
|
||||
unsigned int pixel_freq;
|
||||
- unsigned int pll_base_freq;
|
||||
unsigned int pll_od1;
|
||||
unsigned int pll_od2;
|
||||
unsigned int pll_od3;
|
||||
@@ -365,8 +370,11 @@ struct meson_vclk_params {
|
||||
unsigned int vclk_div;
|
||||
} params[] = {
|
||||
[MESON_VCLK_HDMI_ENCI_54000] = {
|
||||
+ .pll_freq = 4320000,
|
||||
+ .phy_freq = 270000,
|
||||
+ .vclk_freq = 54000,
|
||||
+ .venc_freq = 54000,
|
||||
.pixel_freq = 54000,
|
||||
- .pll_base_freq = 4320000,
|
||||
.pll_od1 = 4,
|
||||
.pll_od2 = 4,
|
||||
.pll_od3 = 1,
|
||||
@@ -374,8 +382,11 @@ struct meson_vclk_params {
|
||||
.vclk_div = 1,
|
||||
},
|
||||
[MESON_VCLK_HDMI_DDR_54000] = {
|
||||
- .pixel_freq = 54000,
|
||||
- .pll_base_freq = 4320000,
|
||||
+ .pll_freq = 4320000,
|
||||
+ .phy_freq = 270000,
|
||||
+ .vclk_freq = 54000,
|
||||
+ .venc_freq = 54000,
|
||||
+ .pixel_freq = 27000,
|
||||
.pll_od1 = 4,
|
||||
.pll_od2 = 4,
|
||||
.pll_od3 = 1,
|
||||
@@ -383,8 +394,11 @@ struct meson_vclk_params {
|
||||
.vclk_div = 1,
|
||||
},
|
||||
[MESON_VCLK_HDMI_DDR_148500] = {
|
||||
- .pixel_freq = 148500,
|
||||
- .pll_base_freq = 2970000,
|
||||
+ .pll_freq = 2970000,
|
||||
+ .phy_freq = 742500,
|
||||
+ .vclk_freq = 148500,
|
||||
+ .venc_freq = 148500,
|
||||
+ .pixel_freq = 74250,
|
||||
.pll_od1 = 4,
|
||||
.pll_od2 = 1,
|
||||
.pll_od3 = 1,
|
||||
@@ -392,8 +406,11 @@ struct meson_vclk_params {
|
||||
.vclk_div = 1,
|
||||
},
|
||||
[MESON_VCLK_HDMI_74250] = {
|
||||
+ .pll_freq = 2970000,
|
||||
+ .phy_freq = 742500,
|
||||
+ .vclk_freq = 74250,
|
||||
+ .venc_freq = 74250,
|
||||
.pixel_freq = 74250,
|
||||
- .pll_base_freq = 2970000,
|
||||
.pll_od1 = 2,
|
||||
.pll_od2 = 2,
|
||||
.pll_od3 = 2,
|
||||
@@ -401,8 +418,11 @@ struct meson_vclk_params {
|
||||
.vclk_div = 1,
|
||||
},
|
||||
[MESON_VCLK_HDMI_148500] = {
|
||||
+ .pll_freq = 2970000,
|
||||
+ .phy_freq = 1485000,
|
||||
+ .vclk_freq = 148500,
|
||||
+ .venc_freq = 148500,
|
||||
.pixel_freq = 148500,
|
||||
- .pll_base_freq = 2970000,
|
||||
.pll_od1 = 1,
|
||||
.pll_od2 = 2,
|
||||
.pll_od3 = 2,
|
||||
@@ -410,8 +430,11 @@ struct meson_vclk_params {
|
||||
.vclk_div = 1,
|
||||
},
|
||||
[MESON_VCLK_HDMI_297000] = {
|
||||
+ .pll_freq = 5940000,
|
||||
+ .phy_freq = 2970000,
|
||||
+ .venc_freq = 297000,
|
||||
+ .vclk_freq = 297000,
|
||||
.pixel_freq = 297000,
|
||||
- .pll_base_freq = 5940000,
|
||||
.pll_od1 = 2,
|
||||
.pll_od2 = 1,
|
||||
.pll_od3 = 1,
|
||||
@@ -419,14 +442,29 @@ struct meson_vclk_params {
|
||||
.vclk_div = 2,
|
||||
},
|
||||
[MESON_VCLK_HDMI_594000] = {
|
||||
+ .pll_freq = 5940000,
|
||||
+ .phy_freq = 5940000,
|
||||
+ .venc_freq = 594000,
|
||||
+ .vclk_freq = 594000,
|
||||
.pixel_freq = 594000,
|
||||
- .pll_base_freq = 5940000,
|
||||
.pll_od1 = 1,
|
||||
.pll_od2 = 1,
|
||||
.pll_od3 = 2,
|
||||
.vid_pll_div = VID_PLL_DIV_5,
|
||||
.vclk_div = 1,
|
||||
},
|
||||
+ [MESON_VCLK_HDMI_594000_YUV420] = {
|
||||
+ .pll_freq = 5940000,
|
||||
+ .phy_freq = 2970000,
|
||||
+ .venc_freq = 594000,
|
||||
+ .vclk_freq = 594000,
|
||||
+ .pixel_freq = 297000,
|
||||
+ .pll_od1 = 2,
|
||||
+ .pll_od2 = 1,
|
||||
+ .pll_od3 = 1,
|
||||
+ .vid_pll_div = VID_PLL_DIV_5,
|
||||
+ .vclk_div = 1,
|
||||
+ },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
@@ -693,6 +731,7 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv,
|
||||
unsigned int od, m, frac, od1, od2, od3;
|
||||
|
||||
if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {
|
||||
+ /* OD2 goes to the PHY, and needs to be *10, so keep OD3=1 */
|
||||
od3 = 1;
|
||||
if (od < 4) {
|
||||
od1 = 2;
|
||||
@@ -715,21 +754,28 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv,
|
||||
}
|
||||
|
||||
enum drm_mode_status
|
||||
-meson_vclk_vic_supported_freq(unsigned int freq)
|
||||
+meson_vclk_vic_supported_freq(unsigned int phy_freq,
|
||||
+ unsigned int vclk_freq)
|
||||
{
|
||||
int i;
|
||||
|
||||
- DRM_DEBUG_DRIVER("freq = %d\n", freq);
|
||||
+ DRM_DEBUG_DRIVER("phy_freq = %d vclk_freq = %d\n",
|
||||
+ phy_freq, vclk_freq);
|
||||
|
||||
for (i = 0 ; params[i].pixel_freq ; ++i) {
|
||||
DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n",
|
||||
i, params[i].pixel_freq,
|
||||
FREQ_1000_1001(params[i].pixel_freq));
|
||||
+ DRM_DEBUG_DRIVER("i = %d phy_freq = %d alt = %d\n",
|
||||
+ i, params[i].phy_freq,
|
||||
+ FREQ_1000_1001(params[i].phy_freq/10)*10);
|
||||
/* Match strict frequency */
|
||||
- if (freq == params[i].pixel_freq)
|
||||
+ if (phy_freq == params[i].phy_freq &&
|
||||
+ vclk_freq == params[i].vclk_freq)
|
||||
return MODE_OK;
|
||||
/* Match 1000/1001 variant */
|
||||
- if (freq == FREQ_1000_1001(params[i].pixel_freq))
|
||||
+ if (phy_freq == (FREQ_1000_1001(params[i].phy_freq/10)*10) &&
|
||||
+ vclk_freq == FREQ_1000_1001(params[i].vclk_freq))
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
@@ -957,8 +1003,9 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
|
||||
}
|
||||
|
||||
void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
|
||||
- unsigned int vclk_freq, unsigned int venc_freq,
|
||||
- unsigned int dac_freq, bool hdmi_use_enci)
|
||||
+ unsigned int phy_freq, unsigned int vclk_freq,
|
||||
+ unsigned int venc_freq, unsigned int dac_freq,
|
||||
+ bool hdmi_use_enci)
|
||||
{
|
||||
bool vic_alternate_clock = false;
|
||||
unsigned int freq;
|
||||
@@ -977,7 +1024,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
|
||||
* - venc_div = 1
|
||||
* - encp encoder
|
||||
*/
|
||||
- meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0,
|
||||
+ meson_vclk_set(priv, phy_freq, 0, 0, 0,
|
||||
VID_PLL_DIV_5, 2, 1, 1, false, false);
|
||||
return;
|
||||
}
|
||||
@@ -999,9 +1046,11 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
|
||||
}
|
||||
|
||||
for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
|
||||
- if (vclk_freq == params[freq].pixel_freq ||
|
||||
- vclk_freq == FREQ_1000_1001(params[freq].pixel_freq)) {
|
||||
- if (vclk_freq != params[freq].pixel_freq)
|
||||
+ if ((phy_freq == params[freq].phy_freq ||
|
||||
+ phy_freq == FREQ_1000_1001(params[freq].phy_freq/10)*10) &&
|
||||
+ (vclk_freq == params[freq].vclk_freq ||
|
||||
+ vclk_freq == FREQ_1000_1001(params[freq].vclk_freq))) {
|
||||
+ if (vclk_freq != params[freq].vclk_freq)
|
||||
vic_alternate_clock = true;
|
||||
else
|
||||
vic_alternate_clock = false;
|
||||
@@ -1030,7 +1079,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
|
||||
return;
|
||||
}
|
||||
|
||||
- meson_vclk_set(priv, params[freq].pll_base_freq,
|
||||
+ meson_vclk_set(priv, params[freq].pll_freq,
|
||||
params[freq].pll_od1, params[freq].pll_od2,
|
||||
params[freq].pll_od3, params[freq].vid_pll_div,
|
||||
params[freq].vclk_div, hdmi_tx_div, venc_div,
|
||||
diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/meson_vclk.h
|
||||
index ed993d20abda..3523d804a008 100644
|
||||
--- a/drivers/gpu/drm/meson/meson_vclk.h
|
||||
+++ b/drivers/gpu/drm/meson/meson_vclk.h
|
||||
@@ -21,10 +21,11 @@ enum {
|
||||
enum drm_mode_status
|
||||
meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq);
|
||||
enum drm_mode_status
|
||||
-meson_vclk_vic_supported_freq(unsigned int freq);
|
||||
+meson_vclk_vic_supported_freq(unsigned int phy_freq, unsigned int vclk_freq);
|
||||
|
||||
void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
|
||||
- unsigned int vclk_freq, unsigned int venc_freq,
|
||||
- unsigned int dac_freq, bool hdmi_use_enci);
|
||||
+ unsigned int phy_freq, unsigned int vclk_freq,
|
||||
+ unsigned int venc_freq, unsigned int dac_freq,
|
||||
+ bool hdmi_use_enci);
|
||||
|
||||
#endif /* __MESON_VCLK_H */
|
||||
diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
|
||||
index 7b7a0d8d737c..5710b5bcfe99 100644
|
||||
--- a/drivers/gpu/drm/meson/meson_venc.c
|
||||
+++ b/drivers/gpu/drm/meson/meson_venc.c
|
||||
@@ -946,6 +946,8 @@ bool meson_venc_hdmi_venc_repeat(int vic)
|
||||
EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat);
|
||||
|
||||
void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
|
||||
+ unsigned int ycrcb_map,
|
||||
+ bool yuv420_mode,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
union meson_hdmi_venc_mode *vmode = NULL;
|
||||
@@ -1496,8 +1498,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
|
||||
writel_relaxed((use_enci ? 1 : 2) |
|
||||
(mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) |
|
||||
(mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) |
|
||||
- 4 << 5 |
|
||||
- (venc_repeat ? 1 << 8 : 0) |
|
||||
+ (ycrcb_map << 5) |
|
||||
+ (venc_repeat || yuv420_mode ? 1 << 8 : 0) |
|
||||
(hdmi_repeat ? 1 << 12 : 0),
|
||||
priv->io_base + _REG(VPU_HDMI_SETTING));
|
||||
|
||||
diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h
|
||||
index 985642a1678e..2d0b71f99402 100644
|
||||
--- a/drivers/gpu/drm/meson/meson_venc.h
|
||||
+++ b/drivers/gpu/drm/meson/meson_venc.h
|
||||
@@ -21,6 +21,15 @@ enum {
|
||||
MESON_VENC_MODE_HDMI,
|
||||
};
|
||||
|
||||
+enum {
|
||||
+ MESON_VENC_MAP_CR_Y_CB = 0,
|
||||
+ MESON_VENC_MAP_Y_CB_CR,
|
||||
+ MESON_VENC_MAP_Y_CR_CB,
|
||||
+ MESON_VENC_MAP_CB_CR_Y,
|
||||
+ MESON_VENC_MAP_CB_Y_CR,
|
||||
+ MESON_VENC_MAP_CR_CB_Y,
|
||||
+};
|
||||
+
|
||||
struct meson_cvbs_enci_mode {
|
||||
unsigned int mode_tag;
|
||||
unsigned int hso_begin; /* HSO begin position */
|
||||
@@ -58,6 +67,8 @@ extern struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc;
|
||||
void meson_venci_cvbs_mode_set(struct meson_drm *priv,
|
||||
struct meson_cvbs_enci_mode *mode);
|
||||
void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
|
||||
+ unsigned int ycrcb_map,
|
||||
+ bool yuv420_mode,
|
||||
struct drm_display_mode *mode);
|
||||
unsigned int meson_venci_get_field(struct meson_drm *priv);
|
||||
|
||||
diff --git a/drivers/gpu/drm/meson/meson_venc_cvbs.c b/drivers/gpu/drm/meson/meson_venc_cvbs.c
|
||||
index 6313a519f257..60d58d6ba1e7 100644
|
||||
--- a/drivers/gpu/drm/meson/meson_venc_cvbs.c
|
||||
+++ b/drivers/gpu/drm/meson/meson_venc_cvbs.c
|
||||
@@ -206,7 +206,8 @@ static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder,
|
||||
/* Setup 27MHz vclk2 for ENCI and VDAC */
|
||||
meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS,
|
||||
MESON_VCLK_CVBS, MESON_VCLK_CVBS,
|
||||
- MESON_VCLK_CVBS, true);
|
||||
+ MESON_VCLK_CVBS, MESON_VCLK_CVBS,
|
||||
+ true);
|
||||
break;
|
||||
}
|
||||
}
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,49 +0,0 @@
|
|||
From e57152836dde170a9da301a2e3d8b70bd6666c0b Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Date: Mon, 20 May 2019 15:37:53 +0200
|
||||
Subject: [PATCH 5/5] drm/meson: Output in YUV444 if sink supports it
|
||||
|
||||
With the YUV420 handling, we can dynamically setup the HDMI output
|
||||
pixel format depending on the mode and connector info.
|
||||
So now, we can output in YUV444, which is the native video pipeline
|
||||
format, directly to the HDMI Sink if it's supported without
|
||||
necessarily involving the HDMI Controller CSC.
|
||||
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
|
||||
---
|
||||
drivers/gpu/drm/meson/meson_dw_hdmi.c | 13 ++++++++++++-
|
||||
1 file changed, 12 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
|
||||
index 2ccee05de04a..72416f8a6170 100644
|
||||
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
|
||||
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
|
||||
@@ -711,12 +711,23 @@ static int meson_venc_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode = &crtc_state->mode;
|
||||
bool is_hdmi2_sink =
|
||||
conn_state->connector->display_info.hdmi.scdc.supported;
|
||||
+ bool specify_out_format = false;
|
||||
+ u32 out_format;
|
||||
|
||||
if (drm_mode_is_420_only(info, mode) ||
|
||||
(!is_hdmi2_sink && drm_mode_is_420_also(info, mode)))
|
||||
dw_hdmi->input_bus_format = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
|
||||
- else
|
||||
+ else {
|
||||
dw_hdmi->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
|
||||
+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) {
|
||||
+ out_format = MEDIA_BUS_FMT_YUV8_1X24;
|
||||
+ specify_out_format = true;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* Set a connector bus format if required */
|
||||
+ drm_display_info_set_bus_formats(info, &out_format,
|
||||
+ (specify_out_format ? 1 : 0));
|
||||
|
||||
/* Specify the encoder output format to the bridge */
|
||||
if (!drm_bridge_format_set(encoder->bridge,
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,594 +0,0 @@
|
|||
From 7fd7898aab479b3dc5b377837e216456863167da Mon Sep 17 00:00:00 2001
|
||||
From: Maxime Jourdan <mjourdan@baylibre.com>
|
||||
Date: Wed, 29 Aug 2018 15:42:56 +0200
|
||||
Subject: [PATCH 03/14] media: meson: vdec: add H.264 decoding support
|
||||
|
||||
Add support for V4L2_PIX_FMT_H264
|
||||
|
||||
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
|
||||
---
|
||||
drivers/staging/media/meson/vdec/Makefile | 2 +-
|
||||
drivers/staging/media/meson/vdec/codec_h264.c | 478 ++++++++++++++++++
|
||||
drivers/staging/media/meson/vdec/codec_h264.h | 13 +
|
||||
.../staging/media/meson/vdec/vdec_platform.c | 31 ++
|
||||
4 files changed, 523 insertions(+), 1 deletion(-)
|
||||
create mode 100644 drivers/staging/media/meson/vdec/codec_h264.c
|
||||
create mode 100644 drivers/staging/media/meson/vdec/codec_h264.h
|
||||
|
||||
diff --git a/drivers/staging/media/meson/vdec/Makefile b/drivers/staging/media/meson/vdec/Makefile
|
||||
index 6bea129084b7..711d990c760e 100644
|
||||
--- a/drivers/staging/media/meson/vdec/Makefile
|
||||
+++ b/drivers/staging/media/meson/vdec/Makefile
|
||||
@@ -3,6 +3,6 @@
|
||||
|
||||
meson-vdec-objs = esparser.o vdec.o vdec_helpers.o vdec_platform.o
|
||||
meson-vdec-objs += vdec_1.o
|
||||
-meson-vdec-objs += codec_mpeg12.o
|
||||
+meson-vdec-objs += codec_mpeg12.o codec_h264.o
|
||||
|
||||
obj-$(CONFIG_VIDEO_MESON_VDEC) += meson-vdec.o
|
||||
diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
|
||||
new file mode 100644
|
||||
index 000000000000..6ac0115afaa3
|
||||
--- /dev/null
|
||||
+++ b/drivers/staging/media/meson/vdec/codec_h264.c
|
||||
@@ -0,0 +1,478 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * Copyright (C) 2018 Maxime Jourdan <maxi.jourdan@wanadoo.fr>
|
||||
+ */
|
||||
+
|
||||
+#include <media/v4l2-mem2mem.h>
|
||||
+#include <media/videobuf2-dma-contig.h>
|
||||
+
|
||||
+#include "vdec_helpers.h"
|
||||
+#include "dos_regs.h"
|
||||
+
|
||||
+#define SIZE_EXT_FW (20 * SZ_1K)
|
||||
+#define SIZE_WORKSPACE 0x1ee000
|
||||
+#define SIZE_SEI (8 * SZ_1K)
|
||||
+
|
||||
+/* Offset added by the firmware which must be substracted
|
||||
+ * from the workspace phyaddr
|
||||
+ */
|
||||
+#define WORKSPACE_BUF_OFFSET 0x1000000
|
||||
+
|
||||
+/* ISR status */
|
||||
+#define CMD_MASK GENMASK(7, 0)
|
||||
+#define CMD_SRC_CHANGE 1
|
||||
+#define CMD_FRAMES_READY 2
|
||||
+#define CMD_FATAL_ERROR 6
|
||||
+#define CMD_BAD_WIDTH 7
|
||||
+#define CMD_BAD_HEIGHT 8
|
||||
+
|
||||
+#define SEI_DATA_READY BIT(15)
|
||||
+
|
||||
+/* Picture type */
|
||||
+#define PIC_TOP_BOT 5
|
||||
+#define PIC_BOT_TOP 6
|
||||
+
|
||||
+/* Size of Motion Vector per macroblock */
|
||||
+#define MB_MV_SIZE 96
|
||||
+
|
||||
+/* Frame status data */
|
||||
+#define PIC_STRUCT_BIT 5
|
||||
+#define PIC_STRUCT_MASK GENMASK(2, 0)
|
||||
+#define BUF_IDX_MASK GENMASK(4, 0)
|
||||
+#define ERROR_FLAG BIT(9)
|
||||
+#define OFFSET_BIT 16
|
||||
+#define OFFSET_MASK GENMASK(15, 0)
|
||||
+
|
||||
+/* Bitstream parsed data */
|
||||
+#define MB_TOTAL_BIT 8
|
||||
+#define MB_TOTAL_MASK GENMASK(15, 0)
|
||||
+#define MB_WIDTH_MASK GENMASK(7, 0)
|
||||
+#define MAX_REF_BIT 24
|
||||
+#define MAX_REF_MASK GENMASK(6, 0)
|
||||
+#define AR_IDC_BIT 16
|
||||
+#define AR_IDC_MASK GENMASK(7, 0)
|
||||
+#define AR_PRESENT_FLAG BIT(0)
|
||||
+#define AR_EXTEND 0xff
|
||||
+
|
||||
+/* Buffer to send to the ESPARSER to signal End Of Stream for H.264.
|
||||
+ * This is a 16x16 encoded picture that will trigger drain firmware-side.
|
||||
+ * There is no known alternative.
|
||||
+ */
|
||||
+static const u8 eos_sequence[SZ_1K] = {
|
||||
+ 0x00, 0x00, 0x00, 0x01, 0x06, 0x05, 0xff, 0xe4, 0xdc, 0x45, 0xe9, 0xbd,
|
||||
+ 0xe6, 0xd9, 0x48, 0xb7, 0x96, 0x2c, 0xd8, 0x20, 0xd9, 0x23, 0xee, 0xef,
|
||||
+ 0x78, 0x32, 0x36, 0x34, 0x20, 0x2d, 0x20, 0x63, 0x6f, 0x72, 0x65, 0x20,
|
||||
+ 0x36, 0x37, 0x20, 0x72, 0x31, 0x31, 0x33, 0x30, 0x20, 0x38, 0x34, 0x37,
|
||||
+ 0x35, 0x39, 0x37, 0x37, 0x20, 0x2d, 0x20, 0x48, 0x2e, 0x32, 0x36, 0x34,
|
||||
+ 0x2f, 0x4d, 0x50, 0x45, 0x47, 0x2d, 0x34, 0x20, 0x41, 0x56, 0x43, 0x20,
|
||||
+ 0x63, 0x6f, 0x64, 0x65, 0x63, 0x20, 0x2d, 0x20, 0x43, 0x6f, 0x70, 0x79,
|
||||
+ 0x6c, 0x65, 0x66, 0x74, 0x20, 0x32, 0x30, 0x30, 0x33, 0x2d, 0x32, 0x30,
|
||||
+ 0x30, 0x39, 0x20, 0x2d, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f,
|
||||
+ 0x77, 0x77, 0x77, 0x2e, 0x76, 0x69, 0x64, 0x65, 0x6f, 0x6c, 0x61, 0x6e,
|
||||
+ 0x2e, 0x6f, 0x72, 0x67, 0x2f, 0x78, 0x32, 0x36, 0x34, 0x2e, 0x68, 0x74,
|
||||
+ 0x6d, 0x6c, 0x20, 0x2d, 0x20, 0x6f, 0x70, 0x74, 0x69, 0x6f, 0x6e, 0x73,
|
||||
+ 0x3a, 0x20, 0x63, 0x61, 0x62, 0x61, 0x63, 0x3d, 0x31, 0x20, 0x72, 0x65,
|
||||
+ 0x66, 0x3d, 0x31, 0x20, 0x64, 0x65, 0x62, 0x6c, 0x6f, 0x63, 0x6b, 0x3d,
|
||||
+ 0x31, 0x3a, 0x30, 0x3a, 0x30, 0x20, 0x61, 0x6e, 0x61, 0x6c, 0x79, 0x73,
|
||||
+ 0x65, 0x3d, 0x30, 0x78, 0x31, 0x3a, 0x30, 0x78, 0x31, 0x31, 0x31, 0x20,
|
||||
+ 0x6d, 0x65, 0x3d, 0x68, 0x65, 0x78, 0x20, 0x73, 0x75, 0x62, 0x6d, 0x65,
|
||||
+ 0x3d, 0x36, 0x20, 0x70, 0x73, 0x79, 0x5f, 0x72, 0x64, 0x3d, 0x31, 0x2e,
|
||||
+ 0x30, 0x3a, 0x30, 0x2e, 0x30, 0x20, 0x6d, 0x69, 0x78, 0x65, 0x64, 0x5f,
|
||||
+ 0x72, 0x65, 0x66, 0x3d, 0x30, 0x20, 0x6d, 0x65, 0x5f, 0x72, 0x61, 0x6e,
|
||||
+ 0x67, 0x65, 0x3d, 0x31, 0x36, 0x20, 0x63, 0x68, 0x72, 0x6f, 0x6d, 0x61,
|
||||
+ 0x5f, 0x6d, 0x65, 0x3d, 0x31, 0x20, 0x74, 0x72, 0x65, 0x6c, 0x6c, 0x69,
|
||||
+ 0x73, 0x3d, 0x30, 0x20, 0x38, 0x78, 0x38, 0x64, 0x63, 0x74, 0x3d, 0x30,
|
||||
+ 0x20, 0x63, 0x71, 0x6d, 0x3d, 0x30, 0x20, 0x64, 0x65, 0x61, 0x64, 0x7a,
|
||||
+ 0x6f, 0x6e, 0x65, 0x3d, 0x32, 0x31, 0x2c, 0x31, 0x31, 0x20, 0x63, 0x68,
|
||||
+ 0x72, 0x6f, 0x6d, 0x61, 0x5f, 0x71, 0x70, 0x5f, 0x6f, 0x66, 0x66, 0x73,
|
||||
+ 0x65, 0x74, 0x3d, 0x2d, 0x32, 0x20, 0x74, 0x68, 0x72, 0x65, 0x61, 0x64,
|
||||
+ 0x73, 0x3d, 0x31, 0x20, 0x6e, 0x72, 0x3d, 0x30, 0x20, 0x64, 0x65, 0x63,
|
||||
+ 0x69, 0x6d, 0x61, 0x74, 0x65, 0x3d, 0x31, 0x20, 0x6d, 0x62, 0x61, 0x66,
|
||||
+ 0x66, 0x3d, 0x30, 0x20, 0x62, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0x3d,
|
||||
+ 0x30, 0x20, 0x6b, 0x65, 0x79, 0x69, 0x6e, 0x74, 0x3d, 0x32, 0x35, 0x30,
|
||||
+ 0x20, 0x6b, 0x65, 0x79, 0x69, 0x6e, 0x74, 0x5f, 0x6d, 0x69, 0x6e, 0x3d,
|
||||
+ 0x32, 0x35, 0x20, 0x73, 0x63, 0x65, 0x6e, 0x65, 0x63, 0x75, 0x74, 0x3d,
|
||||
+ 0x34, 0x30, 0x20, 0x72, 0x63, 0x3d, 0x61, 0x62, 0x72, 0x20, 0x62, 0x69,
|
||||
+ 0x74, 0x72, 0x61, 0x74, 0x65, 0x3d, 0x31, 0x30, 0x20, 0x72, 0x61, 0x74,
|
||||
+ 0x65, 0x74, 0x6f, 0x6c, 0x3d, 0x31, 0x2e, 0x30, 0x20, 0x71, 0x63, 0x6f,
|
||||
+ 0x6d, 0x70, 0x3d, 0x30, 0x2e, 0x36, 0x30, 0x20, 0x71, 0x70, 0x6d, 0x69,
|
||||
+ 0x6e, 0x3d, 0x31, 0x30, 0x20, 0x71, 0x70, 0x6d, 0x61, 0x78, 0x3d, 0x35,
|
||||
+ 0x31, 0x20, 0x71, 0x70, 0x73, 0x74, 0x65, 0x70, 0x3d, 0x34, 0x20, 0x69,
|
||||
+ 0x70, 0x5f, 0x72, 0x61, 0x74, 0x69, 0x6f, 0x3d, 0x31, 0x2e, 0x34, 0x30,
|
||||
+ 0x20, 0x61, 0x71, 0x3d, 0x31, 0x3a, 0x31, 0x2e, 0x30, 0x30, 0x00, 0x80,
|
||||
+ 0x00, 0x00, 0x00, 0x01, 0x67, 0x4d, 0x40, 0x0a, 0x9a, 0x74, 0xf4, 0x20,
|
||||
+ 0x00, 0x00, 0x03, 0x00, 0x20, 0x00, 0x00, 0x06, 0x51, 0xe2, 0x44, 0xd4,
|
||||
+ 0x00, 0x00, 0x00, 0x01, 0x68, 0xee, 0x32, 0xc8, 0x00, 0x00, 0x00, 0x01,
|
||||
+ 0x65, 0x88, 0x80, 0x20, 0x00, 0x08, 0x7f, 0xea, 0x6a, 0xe2, 0x99, 0xb6,
|
||||
+ 0x57, 0xae, 0x49, 0x30, 0xf5, 0xfe, 0x5e, 0x46, 0x0b, 0x72, 0x44, 0xc4,
|
||||
+ 0xe1, 0xfc, 0x62, 0xda, 0xf1, 0xfb, 0xa2, 0xdb, 0xd6, 0xbe, 0x5c, 0xd7,
|
||||
+ 0x24, 0xa3, 0xf5, 0xb9, 0x2f, 0x57, 0x16, 0x49, 0x75, 0x47, 0x77, 0x09,
|
||||
+ 0x5c, 0xa1, 0xb4, 0xc3, 0x4f, 0x60, 0x2b, 0xb0, 0x0c, 0xc8, 0xd6, 0x66,
|
||||
+ 0xba, 0x9b, 0x82, 0x29, 0x33, 0x92, 0x26, 0x99, 0x31, 0x1c, 0x7f, 0x9b
|
||||
+};
|
||||
+
|
||||
+static const u8 *codec_h264_eos_sequence(u32 *len)
|
||||
+{
|
||||
+ *len = ARRAY_SIZE(eos_sequence);
|
||||
+ return eos_sequence;
|
||||
+}
|
||||
+
|
||||
+struct codec_h264 {
|
||||
+ /* H.264 decoder requires an extended firmware */
|
||||
+ void *ext_fw_vaddr;
|
||||
+ dma_addr_t ext_fw_paddr;
|
||||
+
|
||||
+ /* Buffer for the H.264 Workspace */
|
||||
+ void *workspace_vaddr;
|
||||
+ dma_addr_t workspace_paddr;
|
||||
+
|
||||
+ /* Buffer for the H.264 references MV */
|
||||
+ void *ref_vaddr;
|
||||
+ dma_addr_t ref_paddr;
|
||||
+ u32 ref_size;
|
||||
+
|
||||
+ /* Buffer for parsed SEI data */
|
||||
+ void *sei_vaddr;
|
||||
+ dma_addr_t sei_paddr;
|
||||
+
|
||||
+ u32 mb_width;
|
||||
+ u32 mb_height;
|
||||
+ u32 max_refs;
|
||||
+};
|
||||
+
|
||||
+static int codec_h264_can_recycle(struct amvdec_core *core)
|
||||
+{
|
||||
+ return !amvdec_read_dos(core, AV_SCRATCH_7) ||
|
||||
+ !amvdec_read_dos(core, AV_SCRATCH_8);
|
||||
+}
|
||||
+
|
||||
+static void codec_h264_recycle(struct amvdec_core *core, u32 buf_idx)
|
||||
+{
|
||||
+ /* Tell the decoder he can recycle this buffer.
|
||||
+ * AV_SCRATCH_8 serves the same purpose.
|
||||
+ */
|
||||
+ if (!amvdec_read_dos(core, AV_SCRATCH_7))
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_7, buf_idx + 1);
|
||||
+ else
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_8, buf_idx + 1);
|
||||
+}
|
||||
+
|
||||
+static int codec_h264_start(struct amvdec_session *sess) {
|
||||
+ u32 workspace_offset;
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+ struct codec_h264 *h264 = sess->priv;
|
||||
+
|
||||
+ /* Allocate some memory for the H.264 decoder's state */
|
||||
+ h264->workspace_vaddr = dma_alloc_coherent(core->dev, SIZE_WORKSPACE,
|
||||
+ &h264->workspace_paddr, GFP_KERNEL);
|
||||
+ if (!h264->workspace_vaddr) {
|
||||
+ dev_err(core->dev, "Failed to alloc H.264 Workspace\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ /* Allocate some memory for the H.264 SEI dump */
|
||||
+ h264->sei_vaddr = dma_alloc_coherent(core->dev, SIZE_SEI,
|
||||
+ &h264->sei_paddr, GFP_KERNEL);
|
||||
+ if (!h264->sei_vaddr) {
|
||||
+ dev_err(core->dev, "Failed to alloc H.264 SEI\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ amvdec_write_dos_bits(core, POWER_CTL_VLD, BIT(9) | BIT(6));
|
||||
+
|
||||
+ workspace_offset = h264->workspace_paddr - WORKSPACE_BUF_OFFSET;
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_1, workspace_offset);
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_G, h264->ext_fw_paddr);
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_I, h264->sei_paddr - workspace_offset);
|
||||
+
|
||||
+ /* Enable "error correction" */
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_F,
|
||||
+ (amvdec_read_dos(core, AV_SCRATCH_F) & 0xffffffc3) |
|
||||
+ BIT(4) | BIT(7));
|
||||
+
|
||||
+ amvdec_write_dos(core, MDEC_PIC_DC_THRESH, 0x404038aa);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int codec_h264_stop(struct amvdec_session *sess)
|
||||
+{
|
||||
+ struct codec_h264 *h264 = sess->priv;
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+
|
||||
+ if (h264->ext_fw_vaddr)
|
||||
+ dma_free_coherent(core->dev, SIZE_EXT_FW,
|
||||
+ h264->ext_fw_vaddr, h264->ext_fw_paddr);
|
||||
+
|
||||
+ if (h264->workspace_vaddr)
|
||||
+ dma_free_coherent(core->dev, SIZE_WORKSPACE,
|
||||
+ h264->workspace_vaddr, h264->workspace_paddr);
|
||||
+
|
||||
+ if (h264->ref_vaddr)
|
||||
+ dma_free_coherent(core->dev, h264->ref_size,
|
||||
+ h264->ref_vaddr, h264->ref_paddr);
|
||||
+
|
||||
+ if (h264->sei_vaddr)
|
||||
+ dma_free_coherent(core->dev, SIZE_SEI,
|
||||
+ h264->sei_vaddr, h264->sei_paddr);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int codec_h264_load_extended_firmware(struct amvdec_session *sess,
|
||||
+ const u8 *data, u32 len)
|
||||
+{
|
||||
+ struct codec_h264 *h264;
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+
|
||||
+ if (len < SIZE_EXT_FW)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ h264 = kzalloc(sizeof(*h264), GFP_KERNEL);
|
||||
+ if (!h264)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ h264->ext_fw_vaddr = dma_alloc_coherent(core->dev, SIZE_EXT_FW,
|
||||
+ &h264->ext_fw_paddr, GFP_KERNEL);
|
||||
+ if (!h264->ext_fw_vaddr) {
|
||||
+ dev_err(core->dev, "Failed to alloc H.264 extended fw\n");
|
||||
+ kfree(h264);
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ memcpy(h264->ext_fw_vaddr, data, SIZE_EXT_FW);
|
||||
+ sess->priv = h264;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct v4l2_fract par_table[] = {
|
||||
+ { 1, 1 }, { 1, 1 }, { 12, 11 }, { 10, 11 },
|
||||
+ { 16, 11 }, { 40, 33 }, { 24, 11 }, { 20, 11 },
|
||||
+ { 32, 11 }, { 80, 33 }, { 18, 11 }, { 15, 11 },
|
||||
+ { 64, 33 }, { 160, 99 }, { 4, 3 }, { 3, 2 },
|
||||
+ { 2, 1 }
|
||||
+};
|
||||
+
|
||||
+static void codec_h264_set_par(struct amvdec_session *sess)
|
||||
+{
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+ u32 seq_info = amvdec_read_dos(core, AV_SCRATCH_2);
|
||||
+ u32 ar_idc = (seq_info >> AR_IDC_BIT) & AR_IDC_MASK;
|
||||
+
|
||||
+ if (!(seq_info & AR_PRESENT_FLAG))
|
||||
+ return;
|
||||
+
|
||||
+ if (ar_idc == AR_EXTEND) {
|
||||
+ u32 ar_info = amvdec_read_dos(core, AV_SCRATCH_3);
|
||||
+ sess->pixelaspect.numerator = ar_info & 0xffff;
|
||||
+ sess->pixelaspect.denominator = (ar_info >> 16) & 0xffff;
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ if (ar_idc >= ARRAY_SIZE(par_table))
|
||||
+ return;
|
||||
+
|
||||
+ sess->pixelaspect = par_table[ar_idc];
|
||||
+}
|
||||
+
|
||||
+static void codec_h264_resume(struct amvdec_session *sess)
|
||||
+{
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+ struct codec_h264 *h264 = sess->priv;
|
||||
+ u32 mb_width, mb_height, mb_total;
|
||||
+
|
||||
+ amvdec_set_canvases(sess, (u32[]){ ANC0_CANVAS_ADDR, 0 },
|
||||
+ (u32[]){ 24, 0 });
|
||||
+
|
||||
+ dev_dbg(core->dev,
|
||||
+ "max_refs = %u; actual_dpb_size = %u\n",
|
||||
+ h264->max_refs, sess->num_dst_bufs);
|
||||
+
|
||||
+ /* Align to a multiple of 4 macroblocks */
|
||||
+ mb_width = ALIGN(h264->mb_width, 4);
|
||||
+ mb_height = ALIGN(h264->mb_height, 4);
|
||||
+ mb_total = mb_width * mb_height;
|
||||
+
|
||||
+ h264->ref_size = mb_total * MB_MV_SIZE * h264->max_refs;
|
||||
+ h264->ref_vaddr = dma_alloc_coherent(core->dev, h264->ref_size,
|
||||
+ &h264->ref_paddr, GFP_KERNEL);
|
||||
+ if (!h264->ref_vaddr) {
|
||||
+ dev_err(core->dev, "Failed to alloc refs (%u)\n",
|
||||
+ h264->ref_size);
|
||||
+ amvdec_abort(sess);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ /* Address to store the references' MVs */
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_1, h264->ref_paddr);
|
||||
+ /* End of ref MV */
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_4, h264->ref_paddr + h264->ref_size);
|
||||
+
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_0, (h264->max_refs << 24) |
|
||||
+ (sess->num_dst_bufs << 16) |
|
||||
+ ((h264->max_refs - 1) << 8));
|
||||
+}
|
||||
+
|
||||
+/* Configure the H.264 decoder when the parser detected a parameter set change
|
||||
+ */
|
||||
+static void codec_h264_src_change(struct amvdec_session *sess)
|
||||
+{
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+ struct codec_h264 *h264 = sess->priv;
|
||||
+ u32 parsed_info, mb_total;
|
||||
+ u32 crop_infor, crop_bottom, crop_right;
|
||||
+ u32 frame_width, frame_height;
|
||||
+
|
||||
+ sess->keyframe_found = 1;
|
||||
+
|
||||
+ parsed_info = amvdec_read_dos(core, AV_SCRATCH_1);
|
||||
+
|
||||
+ /* Total number of 16x16 macroblocks */
|
||||
+ mb_total = (parsed_info >> MB_TOTAL_BIT) & MB_TOTAL_MASK;
|
||||
+ /* Number of macroblocks per line */
|
||||
+ h264->mb_width = parsed_info & MB_WIDTH_MASK;
|
||||
+ /* Number of macroblock lines */
|
||||
+ h264->mb_height = mb_total / h264->mb_width;
|
||||
+
|
||||
+ h264->max_refs = ((parsed_info >> MAX_REF_BIT) & MAX_REF_MASK) + 1;
|
||||
+
|
||||
+ crop_infor = amvdec_read_dos(core, AV_SCRATCH_6);
|
||||
+ crop_bottom = (crop_infor & 0xff);
|
||||
+ crop_right = (crop_infor >> 16) & 0xff;
|
||||
+
|
||||
+ frame_width = h264->mb_width * 16 - crop_right;
|
||||
+ frame_height = h264->mb_height * 16 - crop_bottom;
|
||||
+
|
||||
+ dev_info(core->dev, "frame: %ux%u; crop: %u %u\n",
|
||||
+ frame_width, frame_height, crop_right, crop_bottom);
|
||||
+
|
||||
+ codec_h264_set_par(sess);
|
||||
+ amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
+ * The offset is split in half in 2 different registers
|
||||
+ */
|
||||
+static u32 get_offset_msb(struct amvdec_core *core, int frame_num)
|
||||
+{
|
||||
+ int take_msb = frame_num % 2;
|
||||
+ int reg_offset = (frame_num / 2) * 4;
|
||||
+ u32 offset_msb = amvdec_read_dos(core, AV_SCRATCH_A + reg_offset);
|
||||
+
|
||||
+ if (take_msb)
|
||||
+ return offset_msb & 0xffff0000;
|
||||
+
|
||||
+ return (offset_msb & 0x0000ffff) << 16;
|
||||
+}
|
||||
+
|
||||
+static void codec_h264_frames_ready(struct amvdec_session *sess, u32 status)
|
||||
+{
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+ int error_count;
|
||||
+ int num_frames;
|
||||
+ int i;
|
||||
+
|
||||
+ error_count = amvdec_read_dos(core, AV_SCRATCH_D);
|
||||
+ num_frames = (status >> 8) & 0xff;
|
||||
+ if (error_count) {
|
||||
+ dev_warn(core->dev,
|
||||
+ "decoder error(s) happened, count %d\n", error_count);
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_D, 0);
|
||||
+ }
|
||||
+
|
||||
+ for (i = 0; i < num_frames; i++) {
|
||||
+ u32 frame_status = amvdec_read_dos(core, AV_SCRATCH_1 + i * 4);
|
||||
+ u32 buffer_index = frame_status & BUF_IDX_MASK;
|
||||
+ u32 pic_struct = (frame_status >> PIC_STRUCT_BIT) &
|
||||
+ PIC_STRUCT_MASK;
|
||||
+ u32 offset = (frame_status >> OFFSET_BIT) & OFFSET_MASK;
|
||||
+ u32 field = V4L2_FIELD_NONE;
|
||||
+
|
||||
+ /* A buffer decode error means it was decoded,
|
||||
+ * but part of the picture will have artifacts.
|
||||
+ * Typical reason is a temporarily corrupted bitstream
|
||||
+ */
|
||||
+ if (frame_status & ERROR_FLAG)
|
||||
+ dev_dbg(core->dev, "Buffer %d decode error\n",
|
||||
+ buffer_index);
|
||||
+
|
||||
+ if (pic_struct == PIC_TOP_BOT)
|
||||
+ field = V4L2_FIELD_INTERLACED_TB;
|
||||
+ else if (pic_struct == PIC_BOT_TOP)
|
||||
+ field = V4L2_FIELD_INTERLACED_BT;
|
||||
+
|
||||
+ offset |= get_offset_msb(core, i);
|
||||
+ amvdec_dst_buf_done_idx(sess, buffer_index, offset, field);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t codec_h264_threaded_isr(struct amvdec_session *sess)
|
||||
+{
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+ u32 status;
|
||||
+ u32 size;
|
||||
+ u8 cmd;
|
||||
+
|
||||
+ status = amvdec_read_dos(core, AV_SCRATCH_0);
|
||||
+ cmd = status & CMD_MASK;
|
||||
+
|
||||
+ switch (cmd) {
|
||||
+ case CMD_SRC_CHANGE:
|
||||
+ codec_h264_src_change(sess);
|
||||
+ break;
|
||||
+ case CMD_FRAMES_READY:
|
||||
+ codec_h264_frames_ready(sess, status);
|
||||
+ break;
|
||||
+ case CMD_FATAL_ERROR:
|
||||
+ dev_err(core->dev, "H.264 decoder fatal error\n");
|
||||
+ goto abort;
|
||||
+ case CMD_BAD_WIDTH:
|
||||
+ size = (amvdec_read_dos(core, AV_SCRATCH_1) + 1) * 16;
|
||||
+ dev_err(core->dev, "Unsupported video width: %u\n", size);
|
||||
+ goto abort;
|
||||
+ case CMD_BAD_HEIGHT:
|
||||
+ size = (amvdec_read_dos(core, AV_SCRATCH_1) + 1) * 16;
|
||||
+ dev_err(core->dev, "Unsupported video height: %u\n", size);
|
||||
+ goto abort;
|
||||
+ case 0: /* Unused but not worth printing for */
|
||||
+ case 9:
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_info(core->dev, "Unexpected H264 ISR: %08X\n", cmd);
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ if (cmd && cmd != CMD_SRC_CHANGE)
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_0, 0);
|
||||
+
|
||||
+ /* Decoder has some SEI data for us ; ignore */
|
||||
+ if (amvdec_read_dos(core, AV_SCRATCH_J) & SEI_DATA_READY)
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_J, 0);
|
||||
+
|
||||
+ return IRQ_HANDLED;
|
||||
+abort:
|
||||
+ amvdec_abort(sess);
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t codec_h264_isr(struct amvdec_session *sess)
|
||||
+{
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+
|
||||
+ amvdec_write_dos(core, ASSIST_MBOX1_CLR_REG, 1);
|
||||
+
|
||||
+ return IRQ_WAKE_THREAD;
|
||||
+}
|
||||
+
|
||||
+struct amvdec_codec_ops codec_h264_ops = {
|
||||
+ .start = codec_h264_start,
|
||||
+ .stop = codec_h264_stop,
|
||||
+ .load_extended_firmware = codec_h264_load_extended_firmware,
|
||||
+ .isr = codec_h264_isr,
|
||||
+ .threaded_isr = codec_h264_threaded_isr,
|
||||
+ .can_recycle = codec_h264_can_recycle,
|
||||
+ .recycle = codec_h264_recycle,
|
||||
+ .eos_sequence = codec_h264_eos_sequence,
|
||||
+ .resume = codec_h264_resume,
|
||||
+};
|
||||
diff --git a/drivers/staging/media/meson/vdec/codec_h264.h b/drivers/staging/media/meson/vdec/codec_h264.h
|
||||
new file mode 100644
|
||||
index 000000000000..9211a11b452c
|
||||
--- /dev/null
|
||||
+++ b/drivers/staging/media/meson/vdec/codec_h264.h
|
||||
@@ -0,0 +1,13 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
+/*
|
||||
+ * Copyright (C) 2018 Maxime Jourdan <maxi.jourdan@wanadoo.fr>
|
||||
+ */
|
||||
+
|
||||
+#ifndef __MESON_VDEC_CODEC_H264_H_
|
||||
+#define __MESON_VDEC_CODEC_H264_H_
|
||||
+
|
||||
+#include "vdec.h"
|
||||
+
|
||||
+extern struct amvdec_codec_ops codec_h264_ops;
|
||||
+
|
||||
+#endif
|
||||
diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c
|
||||
index 824dbc7f46f5..579d3e48f0b2 100644
|
||||
--- a/drivers/staging/media/meson/vdec/vdec_platform.c
|
||||
+++ b/drivers/staging/media/meson/vdec/vdec_platform.c
|
||||
@@ -9,9 +9,20 @@
|
||||
|
||||
#include "vdec_1.h"
|
||||
#include "codec_mpeg12.h"
|
||||
+#include "codec_h264.h"
|
||||
|
||||
static const struct amvdec_format vdec_formats_gxbb[] = {
|
||||
{
|
||||
+ .pixfmt = V4L2_PIX_FMT_H264,
|
||||
+ .min_buffers = 2,
|
||||
+ .max_buffers = 24,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_h264_ops,
|
||||
+ .firmware_path = "meson/gxbb/vh264_mc",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
|
||||
+ }, {
|
||||
.pixfmt = V4L2_PIX_FMT_MPEG1,
|
||||
.min_buffers = 8,
|
||||
.max_buffers = 8,
|
||||
@@ -36,6 +47,16 @@ static const struct amvdec_format vdec_formats_gxbb[] = {
|
||||
|
||||
static const struct amvdec_format vdec_formats_gxl[] = {
|
||||
{
|
||||
+ .pixfmt = V4L2_PIX_FMT_H264,
|
||||
+ .min_buffers = 2,
|
||||
+ .max_buffers = 24,
|
||||
+ .max_width = 3840,
|
||||
+ .max_height = 2160,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_h264_ops,
|
||||
+ .firmware_path = "meson/gxl/vh264_mc",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
|
||||
+ }, {
|
||||
.pixfmt = V4L2_PIX_FMT_MPEG1,
|
||||
.min_buffers = 8,
|
||||
.max_buffers = 8,
|
||||
@@ -60,6 +81,16 @@ static const struct amvdec_format vdec_formats_gxl[] = {
|
||||
|
||||
static const struct amvdec_format vdec_formats_gxm[] = {
|
||||
{
|
||||
+ .pixfmt = V4L2_PIX_FMT_H264,
|
||||
+ .min_buffers = 2,
|
||||
+ .max_buffers = 24,
|
||||
+ .max_width = 3840,
|
||||
+ .max_height = 2160,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_h264_ops,
|
||||
+ .firmware_path = "meson/gxm/vh264_mc",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
|
||||
+ }, {
|
||||
.pixfmt = V4L2_PIX_FMT_MPEG1,
|
||||
.min_buffers = 8,
|
||||
.max_buffers = 8,
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,316 +0,0 @@
|
|||
From 489430ff6ba728be0086a2b4fb85592bee769f93 Mon Sep 17 00:00:00 2001
|
||||
From: Maxime Jourdan <mjourdan@baylibre.com>
|
||||
Date: Wed, 29 Aug 2018 16:01:55 +0200
|
||||
Subject: [PATCH 04/14] media: meson: vdec: add MPEG4 decoding support
|
||||
|
||||
Add support for V4L2_PIX_FMT_MPEG4, V4L2_PIX_FMT_XVID and
|
||||
V4L2_PIX_FMT_H.263
|
||||
|
||||
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
|
||||
---
|
||||
drivers/staging/media/meson/vdec/Makefile | 2 +-
|
||||
.../staging/media/meson/vdec/codec_mpeg4.c | 139 ++++++++++++++++++
|
||||
.../staging/media/meson/vdec/codec_mpeg4.h | 13 ++
|
||||
.../staging/media/meson/vdec/vdec_platform.c | 91 ++++++++++++
|
||||
4 files changed, 244 insertions(+), 1 deletion(-)
|
||||
create mode 100644 drivers/staging/media/meson/vdec/codec_mpeg4.c
|
||||
create mode 100644 drivers/staging/media/meson/vdec/codec_mpeg4.h
|
||||
|
||||
diff --git a/drivers/staging/media/meson/vdec/Makefile b/drivers/staging/media/meson/vdec/Makefile
|
||||
index 711d990c760e..f167a61acb36 100644
|
||||
--- a/drivers/staging/media/meson/vdec/Makefile
|
||||
+++ b/drivers/staging/media/meson/vdec/Makefile
|
||||
@@ -3,6 +3,6 @@
|
||||
|
||||
meson-vdec-objs = esparser.o vdec.o vdec_helpers.o vdec_platform.o
|
||||
meson-vdec-objs += vdec_1.o
|
||||
-meson-vdec-objs += codec_mpeg12.o codec_h264.o
|
||||
+meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_mpeg4.o
|
||||
|
||||
obj-$(CONFIG_VIDEO_MESON_VDEC) += meson-vdec.o
|
||||
diff --git a/drivers/staging/media/meson/vdec/codec_mpeg4.c b/drivers/staging/media/meson/vdec/codec_mpeg4.c
|
||||
new file mode 100644
|
||||
index 000000000000..1d574e576112
|
||||
--- /dev/null
|
||||
+++ b/drivers/staging/media/meson/vdec/codec_mpeg4.c
|
||||
@@ -0,0 +1,139 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * Copyright (C) 2018 Maxime Jourdan <maxi.jourdan@wanadoo.fr>
|
||||
+ */
|
||||
+
|
||||
+#include <media/v4l2-mem2mem.h>
|
||||
+#include <media/videobuf2-dma-contig.h>
|
||||
+
|
||||
+#include "vdec_helpers.h"
|
||||
+#include "dos_regs.h"
|
||||
+
|
||||
+#define SIZE_WORKSPACE SZ_1M
|
||||
+/* Offset added by firmware, to substract from workspace paddr */
|
||||
+#define DCAC_BUFF_START_IP 0x02b00000
|
||||
+
|
||||
+/* map firmware registers to known MPEG4 functions */
|
||||
+#define MREG_BUFFERIN AV_SCRATCH_8
|
||||
+#define MREG_BUFFEROUT AV_SCRATCH_9
|
||||
+#define MP4_NOT_CODED_CNT AV_SCRATCH_A
|
||||
+#define MP4_OFFSET_REG AV_SCRATCH_C
|
||||
+#define MEM_OFFSET_REG AV_SCRATCH_F
|
||||
+#define MREG_FATAL_ERROR AV_SCRATCH_L
|
||||
+
|
||||
+#define BUF_IDX_MASK GENMASK(2, 0)
|
||||
+#define INTERLACE_FLAG BIT(7)
|
||||
+#define TOP_FIELD_FIRST_FLAG BIT(6)
|
||||
+
|
||||
+struct codec_mpeg4 {
|
||||
+ /* Buffer for the MPEG4 Workspace */
|
||||
+ void *workspace_vaddr;
|
||||
+ dma_addr_t workspace_paddr;
|
||||
+};
|
||||
+
|
||||
+static int codec_mpeg4_can_recycle(struct amvdec_core *core)
|
||||
+{
|
||||
+ return !amvdec_read_dos(core, MREG_BUFFERIN);
|
||||
+}
|
||||
+
|
||||
+static void codec_mpeg4_recycle(struct amvdec_core *core, u32 buf_idx)
|
||||
+{
|
||||
+ amvdec_write_dos(core, MREG_BUFFERIN, ~BIT(buf_idx));
|
||||
+}
|
||||
+
|
||||
+static int codec_mpeg4_start(struct amvdec_session *sess) {
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+ struct codec_mpeg4 *mpeg4 = sess->priv;
|
||||
+ int ret;
|
||||
+
|
||||
+ mpeg4 = kzalloc(sizeof(*mpeg4), GFP_KERNEL);
|
||||
+ if (!mpeg4)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ /* Allocate some memory for the MPEG4 decoder's state */
|
||||
+ mpeg4->workspace_vaddr = dma_alloc_coherent(core->dev, SIZE_WORKSPACE,
|
||||
+ &mpeg4->workspace_paddr,
|
||||
+ GFP_KERNEL);
|
||||
+ if (!mpeg4->workspace_vaddr) {
|
||||
+ dev_err(core->dev, "Failed to request MPEG4 Workspace\n");
|
||||
+ ret = -ENOMEM;
|
||||
+ goto free_mpeg4;
|
||||
+ }
|
||||
+
|
||||
+ /* Canvas regs: AV_SCRATCH_0-AV_SCRATCH_4;AV_SCRATCH_G-AV_SCRATCH_J */
|
||||
+ amvdec_set_canvases(sess, (u32[]){ AV_SCRATCH_0, AV_SCRATCH_G, 0 },
|
||||
+ (u32[]){ 4, 4, 0 });
|
||||
+
|
||||
+ amvdec_write_dos(core, MEM_OFFSET_REG,
|
||||
+ mpeg4->workspace_paddr - DCAC_BUFF_START_IP);
|
||||
+ amvdec_write_dos(core, PSCALE_CTRL, 0);
|
||||
+ amvdec_write_dos(core, MP4_NOT_CODED_CNT, 0);
|
||||
+ amvdec_write_dos(core, MREG_BUFFERIN, 0);
|
||||
+ amvdec_write_dos(core, MREG_BUFFEROUT, 0);
|
||||
+ amvdec_write_dos(core, MREG_FATAL_ERROR, 0);
|
||||
+ amvdec_write_dos(core, MDEC_PIC_DC_THRESH, 0x404038aa);
|
||||
+
|
||||
+ sess->keyframe_found = 1;
|
||||
+ sess->priv = mpeg4;
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+free_mpeg4:
|
||||
+ kfree(mpeg4);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int codec_mpeg4_stop(struct amvdec_session *sess)
|
||||
+{
|
||||
+ struct codec_mpeg4 *mpeg4 = sess->priv;
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+
|
||||
+ if (mpeg4->workspace_vaddr) {
|
||||
+ dma_free_coherent(core->dev, SIZE_WORKSPACE,
|
||||
+ mpeg4->workspace_vaddr,
|
||||
+ mpeg4->workspace_paddr);
|
||||
+ mpeg4->workspace_vaddr = 0;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t codec_mpeg4_isr(struct amvdec_session *sess)
|
||||
+{
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+ u32 reg;
|
||||
+ u32 buffer_index;
|
||||
+ u32 field = V4L2_FIELD_NONE;
|
||||
+
|
||||
+ reg = amvdec_read_dos(core, MREG_FATAL_ERROR);
|
||||
+ if (reg == 1) {
|
||||
+ dev_err(core->dev, "mpeg4 fatal error\n");
|
||||
+ amvdec_abort(sess);
|
||||
+ return IRQ_HANDLED;
|
||||
+ }
|
||||
+
|
||||
+ reg = amvdec_read_dos(core, MREG_BUFFEROUT);
|
||||
+ if (!reg)
|
||||
+ goto end;
|
||||
+
|
||||
+ buffer_index = reg & BUF_IDX_MASK;
|
||||
+ if (reg & INTERLACE_FLAG)
|
||||
+ field = (reg & TOP_FIELD_FIRST_FLAG) ?
|
||||
+ V4L2_FIELD_INTERLACED_TB :
|
||||
+ V4L2_FIELD_INTERLACED_BT;
|
||||
+
|
||||
+ amvdec_dst_buf_done_idx(sess, buffer_index, -1, field);
|
||||
+ amvdec_write_dos(core, MREG_BUFFEROUT, 0);
|
||||
+
|
||||
+end:
|
||||
+ amvdec_write_dos(core, ASSIST_MBOX1_CLR_REG, 1);
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+struct amvdec_codec_ops codec_mpeg4_ops = {
|
||||
+ .start = codec_mpeg4_start,
|
||||
+ .stop = codec_mpeg4_stop,
|
||||
+ .isr = codec_mpeg4_isr,
|
||||
+ .can_recycle = codec_mpeg4_can_recycle,
|
||||
+ .recycle = codec_mpeg4_recycle,
|
||||
+};
|
||||
diff --git a/drivers/staging/media/meson/vdec/codec_mpeg4.h b/drivers/staging/media/meson/vdec/codec_mpeg4.h
|
||||
new file mode 100644
|
||||
index 000000000000..8dcdcc51fad4
|
||||
--- /dev/null
|
||||
+++ b/drivers/staging/media/meson/vdec/codec_mpeg4.h
|
||||
@@ -0,0 +1,13 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
+/*
|
||||
+ * Copyright (C) 2018 Maxime Jourdan <maxi.jourdan@wanadoo.fr>
|
||||
+ */
|
||||
+
|
||||
+#ifndef __MESON_VDEC_CODEC_MPEG4_H_
|
||||
+#define __MESON_VDEC_CODEC_MPEG4_H_
|
||||
+
|
||||
+#include "vdec.h"
|
||||
+
|
||||
+extern struct amvdec_codec_ops codec_mpeg4_ops;
|
||||
+
|
||||
+#endif
|
||||
diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c
|
||||
index 579d3e48f0b2..be307bf5bccd 100644
|
||||
--- a/drivers/staging/media/meson/vdec/vdec_platform.c
|
||||
+++ b/drivers/staging/media/meson/vdec/vdec_platform.c
|
||||
@@ -10,9 +10,40 @@
|
||||
#include "vdec_1.h"
|
||||
#include "codec_mpeg12.h"
|
||||
#include "codec_h264.h"
|
||||
+#include "codec_mpeg4.h"
|
||||
|
||||
static const struct amvdec_format vdec_formats_gxbb[] = {
|
||||
{
|
||||
+ .pixfmt = V4L2_PIX_FMT_MPEG4,
|
||||
+ .min_buffers = 8,
|
||||
+ .max_buffers = 8,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mpeg4_ops,
|
||||
+ .firmware_path = "meson/gx/vmpeg4_mc_5",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
+ .pixfmt = V4L2_PIX_FMT_H263,
|
||||
+ .min_buffers = 8,
|
||||
+ .max_buffers = 8,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mpeg4_ops,
|
||||
+ .firmware_path = "meson/gx/h263_mc",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
+ .pixfmt = V4L2_PIX_FMT_XVID,
|
||||
+ .min_buffers = 8,
|
||||
+ .max_buffers = 8,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mpeg4_ops,
|
||||
+ .firmware_path = "meson/gx/vmpeg4_mc_5",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
.pixfmt = V4L2_PIX_FMT_H264,
|
||||
.min_buffers = 2,
|
||||
.max_buffers = 24,
|
||||
@@ -47,6 +78,36 @@ static const struct amvdec_format vdec_formats_gxbb[] = {
|
||||
|
||||
static const struct amvdec_format vdec_formats_gxl[] = {
|
||||
{
|
||||
+ .pixfmt = V4L2_PIX_FMT_MPEG4,
|
||||
+ .min_buffers = 8,
|
||||
+ .max_buffers = 8,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mpeg4_ops,
|
||||
+ .firmware_path = "meson/gx/vmpeg4_mc_5",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
+ .pixfmt = V4L2_PIX_FMT_H263,
|
||||
+ .min_buffers = 8,
|
||||
+ .max_buffers = 8,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mpeg4_ops,
|
||||
+ .firmware_path = "meson/gx/h263_mc",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
+ .pixfmt = V4L2_PIX_FMT_XVID,
|
||||
+ .min_buffers = 8,
|
||||
+ .max_buffers = 8,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mpeg4_ops,
|
||||
+ .firmware_path = "meson/gx/vmpeg4_mc_5",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
.pixfmt = V4L2_PIX_FMT_H264,
|
||||
.min_buffers = 2,
|
||||
.max_buffers = 24,
|
||||
@@ -81,6 +142,36 @@ static const struct amvdec_format vdec_formats_gxl[] = {
|
||||
|
||||
static const struct amvdec_format vdec_formats_gxm[] = {
|
||||
{
|
||||
+ .pixfmt = V4L2_PIX_FMT_MPEG4,
|
||||
+ .min_buffers = 8,
|
||||
+ .max_buffers = 8,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mpeg4_ops,
|
||||
+ .firmware_path = "meson/gx/vmpeg4_mc_5",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
+ .pixfmt = V4L2_PIX_FMT_H263,
|
||||
+ .min_buffers = 8,
|
||||
+ .max_buffers = 8,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mpeg4_ops,
|
||||
+ .firmware_path = "meson/gx/h263_mc",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
+ .pixfmt = V4L2_PIX_FMT_XVID,
|
||||
+ .min_buffers = 8,
|
||||
+ .max_buffers = 8,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mpeg4_ops,
|
||||
+ .firmware_path = "meson/gx/vmpeg4_mc_5",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
.pixfmt = V4L2_PIX_FMT_H264,
|
||||
.min_buffers = 2,
|
||||
.max_buffers = 24,
|
||||
--
|
||||
2.20.1
|
||||
|
||||
|
|
@ -1,256 +0,0 @@
|
|||
From 309ecd66298c41728c7e0de45a86ee6237fed90a Mon Sep 17 00:00:00 2001
|
||||
From: Maxime Jourdan <mjourdan@baylibre.com>
|
||||
Date: Sun, 21 Oct 2018 15:14:27 +0200
|
||||
Subject: [PATCH 05/14] media: meson: vdec: add MJPEG decoding support
|
||||
|
||||
Add support for V4L2_PIX_FMT_MJPEG
|
||||
|
||||
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
|
||||
---
|
||||
drivers/staging/media/meson/vdec/Makefile | 2 +-
|
||||
.../staging/media/meson/vdec/codec_mjpeg.c | 140 ++++++++++++++++++
|
||||
.../staging/media/meson/vdec/codec_mjpeg.h | 13 ++
|
||||
.../staging/media/meson/vdec/vdec_platform.c | 31 ++++
|
||||
4 files changed, 185 insertions(+), 1 deletion(-)
|
||||
create mode 100644 drivers/staging/media/meson/vdec/codec_mjpeg.c
|
||||
create mode 100644 drivers/staging/media/meson/vdec/codec_mjpeg.h
|
||||
|
||||
diff --git a/drivers/staging/media/meson/vdec/Makefile b/drivers/staging/media/meson/vdec/Makefile
|
||||
index f167a61acb36..20c23f9015eb 100644
|
||||
--- a/drivers/staging/media/meson/vdec/Makefile
|
||||
+++ b/drivers/staging/media/meson/vdec/Makefile
|
||||
@@ -3,6 +3,6 @@
|
||||
|
||||
meson-vdec-objs = esparser.o vdec.o vdec_helpers.o vdec_platform.o
|
||||
meson-vdec-objs += vdec_1.o
|
||||
-meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_mpeg4.o
|
||||
+meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_mpeg4.o codec_mjpeg.o
|
||||
|
||||
obj-$(CONFIG_VIDEO_MESON_VDEC) += meson-vdec.o
|
||||
diff --git a/drivers/staging/media/meson/vdec/codec_mjpeg.c b/drivers/staging/media/meson/vdec/codec_mjpeg.c
|
||||
new file mode 100644
|
||||
index 000000000000..abea9e3f944c
|
||||
--- /dev/null
|
||||
+++ b/drivers/staging/media/meson/vdec/codec_mjpeg.c
|
||||
@@ -0,0 +1,140 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * Copyright (C) 2018 Maxime Jourdan <maxi.jourdan@wanadoo.fr>
|
||||
+ */
|
||||
+
|
||||
+#include <media/v4l2-mem2mem.h>
|
||||
+#include <media/videobuf2-dma-contig.h>
|
||||
+
|
||||
+#include "vdec_helpers.h"
|
||||
+#include "dos_regs.h"
|
||||
+
|
||||
+/* map FW registers to known MJPEG functions */
|
||||
+#define MREG_DECODE_PARAM AV_SCRATCH_2
|
||||
+#define MREG_TO_AMRISC AV_SCRATCH_8
|
||||
+#define MREG_FROM_AMRISC AV_SCRATCH_9
|
||||
+#define MREG_FRAME_OFFSET AV_SCRATCH_A
|
||||
+
|
||||
+static int codec_mjpeg_can_recycle(struct amvdec_core *core)
|
||||
+{
|
||||
+ return !amvdec_read_dos(core, MREG_TO_AMRISC);
|
||||
+}
|
||||
+
|
||||
+static void codec_mjpeg_recycle(struct amvdec_core *core, u32 buf_idx)
|
||||
+{
|
||||
+ amvdec_write_dos(core, MREG_TO_AMRISC, buf_idx + 1);
|
||||
+}
|
||||
+
|
||||
+/* 4 point triangle */
|
||||
+static const uint32_t filt_coef[] = {
|
||||
+ 0x20402000, 0x20402000, 0x1f3f2101, 0x1f3f2101,
|
||||
+ 0x1e3e2202, 0x1e3e2202, 0x1d3d2303, 0x1d3d2303,
|
||||
+ 0x1c3c2404, 0x1c3c2404, 0x1b3b2505, 0x1b3b2505,
|
||||
+ 0x1a3a2606, 0x1a3a2606, 0x19392707, 0x19392707,
|
||||
+ 0x18382808, 0x18382808, 0x17372909, 0x17372909,
|
||||
+ 0x16362a0a, 0x16362a0a, 0x15352b0b, 0x15352b0b,
|
||||
+ 0x14342c0c, 0x14342c0c, 0x13332d0d, 0x13332d0d,
|
||||
+ 0x12322e0e, 0x12322e0e, 0x11312f0f, 0x11312f0f,
|
||||
+ 0x10303010
|
||||
+};
|
||||
+
|
||||
+static void codec_mjpeg_init_scaler(struct amvdec_core *core)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ /* PSCALE cbus bmem enable */
|
||||
+ amvdec_write_dos(core, PSCALE_CTRL, 0xc000);
|
||||
+
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_ADDR, 0);
|
||||
+ for (i = 0; i < ARRAY_SIZE(filt_coef); ++i) {
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, filt_coef[i]);
|
||||
+ }
|
||||
+
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_ADDR, 74);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x0008);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x60000000);
|
||||
+
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_ADDR, 82);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x0008);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x60000000);
|
||||
+
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_ADDR, 78);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x0008);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x60000000);
|
||||
+
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_ADDR, 86);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x0008);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x60000000);
|
||||
+
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_ADDR, 73);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x10000);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_ADDR, 81);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x10000);
|
||||
+
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_ADDR, 77);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x10000);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_ADDR, 85);
|
||||
+ amvdec_write_dos(core, PSCALE_BMEM_DAT, 0x10000);
|
||||
+
|
||||
+ amvdec_write_dos(core, PSCALE_RST, 0x7);
|
||||
+ amvdec_write_dos(core, PSCALE_RST, 0);
|
||||
+}
|
||||
+
|
||||
+static int codec_mjpeg_start(struct amvdec_session *sess)
|
||||
+{
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_0, 12);
|
||||
+ amvdec_write_dos(core, AV_SCRATCH_1, 0x031a);
|
||||
+
|
||||
+ amvdec_set_canvases(sess, (u32[]){ AV_SCRATCH_4, 0 },
|
||||
+ (u32[]){ 4, 0 });
|
||||
+ codec_mjpeg_init_scaler(core);
|
||||
+
|
||||
+ amvdec_write_dos(core, MREG_TO_AMRISC, 0);
|
||||
+ amvdec_write_dos(core, MREG_FROM_AMRISC, 0);
|
||||
+ amvdec_write_dos(core, MCPU_INTR_MSK, 0xffff);
|
||||
+ amvdec_write_dos(core, MREG_DECODE_PARAM,
|
||||
+ (sess->height << 4) | 0x8000);
|
||||
+ amvdec_write_dos(core, VDEC_ASSIST_AMR1_INT8, 8);
|
||||
+
|
||||
+ /* Intra-only codec */
|
||||
+ sess->keyframe_found = 1;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int codec_mjpeg_stop(struct amvdec_session *sess)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t codec_mjpeg_isr(struct amvdec_session *sess)
|
||||
+{
|
||||
+ struct amvdec_core *core = sess->core;
|
||||
+ u32 reg;
|
||||
+ u32 buffer_index;
|
||||
+ u32 offset;
|
||||
+
|
||||
+ amvdec_write_dos(core, ASSIST_MBOX1_CLR_REG, 1);
|
||||
+
|
||||
+ reg = amvdec_read_dos(core, MREG_FROM_AMRISC);
|
||||
+ if (!(reg & 0x7))
|
||||
+ return IRQ_HANDLED;
|
||||
+
|
||||
+ buffer_index = ((reg & 0x7) - 1) & 3;
|
||||
+ offset = amvdec_read_dos(core, MREG_FRAME_OFFSET);
|
||||
+ amvdec_dst_buf_done_idx(sess, buffer_index, offset, V4L2_FIELD_NONE);
|
||||
+
|
||||
+ amvdec_write_dos(core, MREG_FROM_AMRISC, 0);
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+struct amvdec_codec_ops codec_mjpeg_ops = {
|
||||
+ .start = codec_mjpeg_start,
|
||||
+ .stop = codec_mjpeg_stop,
|
||||
+ .isr = codec_mjpeg_isr,
|
||||
+ .can_recycle = codec_mjpeg_can_recycle,
|
||||
+ .recycle = codec_mjpeg_recycle,
|
||||
+};
|
||||
diff --git a/drivers/staging/media/meson/vdec/codec_mjpeg.h b/drivers/staging/media/meson/vdec/codec_mjpeg.h
|
||||
new file mode 100644
|
||||
index 000000000000..364fa7ee6d9e
|
||||
--- /dev/null
|
||||
+++ b/drivers/staging/media/meson/vdec/codec_mjpeg.h
|
||||
@@ -0,0 +1,13 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
+/*
|
||||
+ * Copyright (C) 2018 Maxime Jourdan <maxi.jourdan@wanadoo.fr>
|
||||
+ */
|
||||
+
|
||||
+#ifndef __MESON_VDEC_CODEC_MJPEG_H_
|
||||
+#define __MESON_VDEC_CODEC_MJPEG_H_
|
||||
+
|
||||
+#include "vdec.h"
|
||||
+
|
||||
+extern struct amvdec_codec_ops codec_mjpeg_ops;
|
||||
+
|
||||
+#endif
|
||||
diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c
|
||||
index be307bf5bccd..fb714d74753f 100644
|
||||
--- a/drivers/staging/media/meson/vdec/vdec_platform.c
|
||||
+++ b/drivers/staging/media/meson/vdec/vdec_platform.c
|
||||
@@ -11,9 +11,20 @@
|
||||
#include "codec_mpeg12.h"
|
||||
#include "codec_h264.h"
|
||||
#include "codec_mpeg4.h"
|
||||
+#include "codec_mjpeg.h"
|
||||
|
||||
static const struct amvdec_format vdec_formats_gxbb[] = {
|
||||
{
|
||||
+ .pixfmt = V4L2_PIX_FMT_MJPEG,
|
||||
+ .min_buffers = 4,
|
||||
+ .max_buffers = 4,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mjpeg_ops,
|
||||
+ .firmware_path = "meson/gx/vmjpeg_mc",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
.pixfmt = V4L2_PIX_FMT_MPEG4,
|
||||
.min_buffers = 8,
|
||||
.max_buffers = 8,
|
||||
@@ -78,6 +89,16 @@ static const struct amvdec_format vdec_formats_gxbb[] = {
|
||||
|
||||
static const struct amvdec_format vdec_formats_gxl[] = {
|
||||
{
|
||||
+ .pixfmt = V4L2_PIX_FMT_MJPEG,
|
||||
+ .min_buffers = 4,
|
||||
+ .max_buffers = 4,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mjpeg_ops,
|
||||
+ .firmware_path = "meson/gx/vmjpeg_mc",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
.pixfmt = V4L2_PIX_FMT_MPEG4,
|
||||
.min_buffers = 8,
|
||||
.max_buffers = 8,
|
||||
@@ -142,6 +163,16 @@ static const struct amvdec_format vdec_formats_gxl[] = {
|
||||
|
||||
static const struct amvdec_format vdec_formats_gxm[] = {
|
||||
{
|
||||
+ .pixfmt = V4L2_PIX_FMT_MJPEG,
|
||||
+ .min_buffers = 4,
|
||||
+ .max_buffers = 4,
|
||||
+ .max_width = 1920,
|
||||
+ .max_height = 1080,
|
||||
+ .vdec_ops = &vdec_1_ops,
|
||||
+ .codec_ops = &codec_mjpeg_ops,
|
||||
+ .firmware_path = "meson/gx/vmjpeg_mc",
|
||||
+ .pixfmts_cap = { V4L2_PIX_FMT_YUV420M, 0 },
|
||||
+ }, {
|
||||
.pixfmt = V4L2_PIX_FMT_MPEG4,
|
||||
.min_buffers = 8,
|
||||
.max_buffers = 8,
|
||||
--
|
||||
2.20.1
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue