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Author SHA1 Message Date
Jagmn
c92fdd1161
[h3] Fix SPDIF clock multiplier settings (#1981)
There have been intermittent issues with SPDIF output on H3 & H2+ devices.
    Digging into the H2+ & H3 datasheets I encountered an important clue on
    table 8.7.2.2: s_clk needs to be 4x24.576 MHz or 4x22.5782 Mhz.
    Probably due to how SPDIF is a huge oversample of the audio frequency.

Co-authored-by: George Lander <lander@jagmn.com>
2020-05-22 00:24:33 +02:00