diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
index c2a6bedb..cdfcf0a5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
@@ -67,24 +67,6 @@
 		model = "NanoPi 4 Series";
 	};
 
-	fiq_debugger: fiq-debugger {
-		compatible = "rockchip,fiq-debugger";
-		rockchip,serial-id = <2>;
-		rockchip,signal-irq = <182>;
-		rockchip,wake-irq = <0>;
-		rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
-		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart2c_xfer>;
-	};
-
-	xin32k: xin32k {
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-		clock-output-names = "xin32k";
-		#clock-cells = <0>;
-	};
-
 	clkin_gmac: external-gmac-clock {
 		compatible = "fixed-clock";
 		clock-frequency = <125000000>;
@@ -507,16 +489,12 @@
 	//allocator = <0>;
 };
 
-&rga {
-	status = "disabled";
-};
-
 &display_subsystem {
 	status = "okay";
 };
 
 &edp {
-	status = "okay";
+	status = "disabled";
 	force-hpd;
 	/delete-property/ pinctrl-0;
 
@@ -537,29 +515,22 @@
 
 &route_edp {
 	status = "okay";
-	logo,mode = "center";
 };
 
 &cdn_dp {
-	status = "okay";
+	status = "disabled";
 	extcon = <&fusb0>;
 	phys = <&tcphy0_dp>;
 };
 
 &hdmi {
-	/* remove the hdmi_i2c_xfer */
-	pinctrl-0 = <&hdmi_cec>;
+	/* remove the hdmi_cec, reused by edp_hpd */
+	pinctrl-0 = <&hdmi_i2c_xfer>;
 	#address-cells = <1>;
 	#size-cells = <0>;
 	#sound-dai-cells = <0>;
 	status = "okay";
 	ddc-i2c-bus = <&i2c7>;
-	rockchip,defaultmode = <16>; /* CEA 1920x1080@60Hz */
-};
-
-&route_hdmi {
-	status = "okay";
-	logo,mode = "center";
 };
 
 &cif_isp0 {
@@ -932,11 +903,6 @@
 	#sound-dai-cells = <0>;
 };
 
-&i2s1 {
-	assigned-clocks = <&cru SCLK_I2S_8CH>;
-	assigned-clock-parents = <&cru SCLK_I2S1_8CH>;
-};
-
 &i2s2 {
 	#sound-dai-cells = <0>;
 	status = "okay";
@@ -946,10 +946,16 @@
 };
 
 &pcie0 {
+	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+	assigned-clock-rates = <100000000>; 
 	status = "okay";
 	ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
 	num-lanes = <4>;
-	max-link-speed = <2>;
+	vpcie3v3-supply = <&vcc3v3_sys>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqn_cpm>;
+	max-link-speed = <2>; 
 };
 
 &pwm_bl {
@@ -1147,14 +1120,6 @@
 };
 
 &pinctrl {
-	edp {
-		/delete-node/ edp-hpd;
-	};
-
-	hdmi {
-		/delete-node/ hdmi-i2c-xfer;
-	};
-
 	pmic {
 		pmic_int_l: pmic-int-l {
 			rockchip,pins = <1 21 RK_FUNC_GPIO &pcfg_pull_up>;