diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 01180849..8a66eadb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1016,4 +1016,7 @@ dtstree := $(srctree)/$(src) dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) always := $(dtb-y) +subdir-y := overlay clean-files := *.dtb + +dts-dirs += overlay diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile new file mode 100644 index 00000000..af7af653 --- /dev/null +++ b/arch/arm/boot/dts/overlay/Makefile @@ -0,0 +1,56 @@ +ifeq ($(CONFIG_OF_CONFIGFS),y) + +dtbo-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-analog-codec.dtbo \ + sun4i-a10-can.dtbo \ + sun4i-a10-i2c1.dtbo \ + sun4i-a10-i2c2.dtbo \ + sun4i-a10-nand.dtbo \ + sun4i-a10-pps-gpio.dtbo \ + sun4i-a10-pwm.dtbo \ + sun4i-a10-spdif-out.dtbo \ + sun4i-a10-spi-jedec-nor.dtbo \ + sun4i-a10-spi-spidev.dtbo \ + sun4i-a10-uart2.dtbo \ + sun4i-a10-uart3.dtbo \ + sun4i-a10-uart4.dtbo \ + sun4i-a10-uart5.dtbo \ + sun4i-a10-uart6.dtbo \ + sun4i-a10-uart7.dtbo \ + sun4i-a10-w1-gpio.dtbo + +dtbo-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-analog-codec.dtbo \ + sun7i-a20-can.dtbo \ + sun7i-a20-i2c1.dtbo \ + sun7i-a20-i2c2.dtbo \ + sun7i-a20-i2c3.dtbo \ + sun7i-a20-i2c4.dtbo \ + sun7i-a20-mmc2.dtbo \ + sun7i-a20-nand.dtbo \ + sun7i-a20-pps-gpio.dtbo \ + sun7i-a20-pwm.dtbo \ + sun7i-a20-spdif-out.dtbo \ + sun7i-a20-spi-add-cs1.dtbo \ + sun7i-a20-spi-jedec-nor.dtbo \ + sun7i-a20-spi-spidev.dtbo \ + sun7i-a20-uart2.dtbo \ + sun7i-a20-uart3.dtbo \ + sun7i-a20-uart4.dtbo \ + sun7i-a20-uart5.dtbo \ + sun7i-a20-uart6.dtbo \ + sun7i-a20-uart7.dtbo \ + sun7i-a20-w1-gpio.dtbo + +scr-$(CONFIG_MACH_SUN4I) += sun4i-a10-fixup.scr +scr-$(CONFIG_MACH_SUN7I) += sun7i-a20-fixup.scr + +dtbotxt-$(CONFIG_MACH_SUN4I) += README.sun4i-a10-overlays +dtbotxt-$(CONFIG_MACH_SUN7I) += README.sun7i-a20-overlays + +targets += $(dtbo-y) $(scr-y) $(dtbotxt-y) + +endif + +always := $(dtbo-y) $(scr-y) $(dtbotxt-y) +clean-files := *.dtbo *.scr diff --git a/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays b/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays new file mode 100644 index 00000000..adcc66f0 --- /dev/null +++ b/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays @@ -0,0 +1,253 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/User-Guide_Allwinner_overlays/ + +### Platform: + +sun4i-a10 (Allwinner A10) + +### Platform details: + +Supported pin banks: PB, PC, PD, PE, PG, PH, PI + +SPI controller 0 have 2 exposed hardware CS, +other SPI controllers have only one hardware CS +Reference: A10 User manual section 17.4.13, A10 datasheet section 5.2 + +I2C bus 0 is used for the AXP209 PMIC + +### Provided overlays: + +- analog-codec +- can +- i2c1 +- i2c2 +- nand +- pps-gpio +- pwm +- spdif-out +- spi-jedec-nor +- spi-spidev +- uart1 +- uart2 +- uart3 +- uart4 +- uart5 +- uart6 +- uart7 +- w1-gpio + +### Overlay details: + +### analog-codec + +Activates SoC analog codec driver that provides Line Out and Mic In +functionality + +## can + +Activates SoC CAN controller + +CAN pins (TX, RX): PH20, PH21 + +### i2c1 + +Activates TWI/I2C bus 1 + +I2C1 pins (SCL, SDA): PB18, PB19 + +### i2c2 + +Activates TWI/I2C bus 2 + +I2C2 pins (SCL, SDA): PB20, PB21 + +### nand + +Activates NAND controller + +This overlay should not be used until mainline MLC NAND support +allows using NAND storage reliably + +### pps-gpio + +Activates pulse-per-second GPIO client + +Parameters: + +param_pps_pin (pin) + Pin PPS source is connected to + Optional + Default: PI15 + +param_pps_falling_edge (bool) + Assert by falling edge + Optional + Default: 0 + When set (to 1), assert is indicated by a falling edge + (instead of by a rising edge) + +### pwm + +Activates hardware PWM controller + +PWM pins (PWM0, PWM1): PB2, PI3 + +Parameters: + +param_pwm_pins (string) + PWM pins activated with this overlay + Optional + Default: both + Supported values: 0, 1, both + If set to 0 only PWM0 can be used, + if set to 1 then only PWM1 can be used, + if set to both (default), both PWM0 and PWM1 can be used + +### spdif-out + +Activates SPDIF/Toslink audio output + +SPDIF pin: PB13 + +### spi-jedec-nor + +Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus +supported by the kernel SPI NOR driver + +SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 +SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 +SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 +SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 + +Parameters: + +param_spinor_spi_bus (int) + SPI bus to activate SPI NOR flash support on + Required + Supported values: 0, 1, 2 + +param_spi2_bus_pins (char) + SPI bus 2 pinmux variant + Optional + Default: a + Supported values: a, b + Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay + +param_spinor_max_freq (int) + Maximum SPI frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### spi-spidev + +Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, +where X is the bus number and Y is the CS number + +SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 +SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 +SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 +SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 + +Parameters: + +param_spidev_spi_bus (int) + SPI bus to activate mcp2515 support on + Required + Supported values: 0, 1, 2 + +param_spi2_bus_pins (char) + SPI bus 2 pinmux variant + Optional + Default: a + Supported values: a, b + Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay + +param_spidev_max_freq (int) + Maximum SPIdev frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### uart2 + +Activates serial port 2 (/dev/ttyS2) + +UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17 + +Parameters: + +param_uart2_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart3 + +Activates serial port 3 (/dev/ttyS3) + +UART 3 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 + +Parameters: + +param_uart3_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart4 + +Activates serial port 4 (/dev/ttyS4) + +UART 4 pins a (TX, RX): PG10, PG11 +UART 4 pins b (TX, RX): PH4, PH5 + +Parameters: + +param_uart4_pins (char) + Determines what pins UART 4 is exposed on + Optional + Default: a + Supported values: a, b + +### uart 5 + +Activates serial port 5 (/dev/ttyS5) + +UART 5 pins (TX, RX): PH6, PH7 + +### uart 6 + +Activates serial port 6 (/dev/ttyS6) + +UART 6 pins (TX, RX): PI12, PI13 + +### uart 7 + +Activates serial port 7 (/dev/ttyS7) + +UART 7 pins (TX, RX): PI20, PI21 + +### w1-gpio + +Activates 1-Wire GPIO master +Requires an external pull-up resistor on the data pin +or enabling the internal pull-up + +Parameters: + +param_w1_pin (pin) + Data pin for 1-Wire master + Optional + Default: PI15 + +param_w1_pin_int_pullup (bool) + Enable internal pull-up for the data pin + Optional + Default: 0 + Set to 1 to enable the pull-up + This option should not be used with multiple sensors or long wires - + please use external pull-up resistor instead diff --git a/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays new file mode 100644 index 00000000..602a2087 --- /dev/null +++ b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays @@ -0,0 +1,310 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/User-Guide_Allwinner_overlays/ + +### Platform: + +sun7i-a20 (Allwinner A20) + +### Platform details: + +Supported pin banks: PB, PC, PD, PE, PG, PH, PI + +SPI controller 0 have 2 exposed hardware CS, +other SPI controllers have only one hardware CS +Reference: A20 Datasheet sections 6.3.5.1, 1.19.2 + +I2C bus 0 is used for the AXP209 PMIC + +### Provided overlays: + +- analog-codec +- can +- i2c1 +- i2c2 +- i2c3 +- i2c4 +- mmc2 +- nand +- pps-gpio +- pwm +- spdif-out +- spi-add-cs1 +- spi-jedec-nor +- spi-spidev +- uart1 +- uart2 +- uart3 +- uart4 +- uart5 +- uart6 +- uart7 +- w1-gpio + +### Overlay details: + +### analog-codec + +Activates SoC analog codec driver that provides Line Out and Mic In +functionality + +## can + +Activates SoC CAN controller + +CAN pins (TX, RX): PH20, PH21 + +### i2c1 + +Activates TWI/I2C bus 1 + +I2C1 pins (SCL, SDA): PB18, PB19 + +### i2c2 + +Activates TWI/I2C bus 2 + +I2C2 pins (SCL, SDA): PB20, PB21 + +### i2c3 + +Activates TWI/I2C bus 3 + +I2C3 pins (SCL, SDA): PI0, PI1 + +### i2c4 + +Activates TWI/I2C bus 4 + +I2C4 pins (SCL, SDA): PI2, PI3 + +### mmc2 + +Activates SD/MMC controller 2. To be used on boards with second SD slot, eMMC +or tSD instead of NAND storage. + +MMC2 pins: PC6, PC7, PC8, PC9, PC10, PC11 + +Parameters: + +param_mmc2_cd_pin (pin) + SD/MMC 2 card detect pin + Optional + Default: PH0 + +param_mmc2_non_removable (bool) + Option for non-removable storage options on MMC 2 controller (eMMC or tSD) + Optional + Default: 0 + Set to 1 to use this option + +### nand + +Activates NAND controller + +This overlay should not be used until mainline MLC NAND support +allows using NAND storage reliably + +### pps-gpio + +Activates pulse-per-second GPIO client + +Parameters: + +param_pps_pin (pin) + Pin PPS source is connected to + Optional + Default: PI15 + +param_pps_falling_edge (bool) + Assert by falling edge + Optional + Default: 0 + When set (to 1), assert is indicated by a falling edge + (instead of by a rising edge) + +### pwm + +Activates hardware PWM controller + +PWM pins (PWM0, PWM1): PB2, PI3 + +Parameters: + +param_pwm_pins (string) + PWM pins activated with this overlay + Optional + Default: both + Supported values: 0, 1, both + If set to 0 only PWM0 can be used, + if set to 1 then only PWM1 can be used, + if set to both (default), both PWM0 and PWM1 can be used + +### spdif-out + +Activates SPDIF/Toslink audio output + +SPDIF pin: PB13 + +### spi-add-cs1 + +Activates SPI chip select 1 on SPI controller 0 +This overlay is required for using chip select 1 with other SPI overlays + +SPI 0 CS1 pin: PI14 + +### spi-jedec-nor + +Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus +supported by the kernel SPI NOR driver + +SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 +SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 +SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 +SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 + +Parameters: + +param_spinor_spi_bus (int) + SPI bus to activate SPI NOR flash support on + Required + Supported values: 0, 1, 2 + +param_spinor_spi_cs (int) + SPI chip select number for SPI NOR connected to SPI bus 0 + Optional + Default: 0 + Supported values: 0, 1 + Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay + +param_spi2_bus_pins (char) + SPI bus 2 pinmux variant + Optional + Default: a + Supported values: a, b + Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay + +param_spinor_max_freq (int) + Maximum SPI frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### spi-spidev + +Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, +where X is the bus number and Y is the CS number + +SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 +SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 +SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 +SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 + +Parameters: + +param_spidev_spi_bus (int) + SPI bus to activate mcp2515 support on + Required + Supported values: 0, 1, 2 + +param_spidev_spi_cs (int) + SPI chip select number for SPIdev on SPI bus 0 + Optional + Default: 0 + Supported values: 0, 1 + Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay + +param_spi2_bus_pins (char) + SPI bus 2 pinmux variant + Optional + Default: a + Supported values: a, b + Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay + +param_spidev_max_freq (int) + Maximum SPIdev frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### uart2 + +Activates serial port 2 (/dev/ttyS2) + +UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17 + +Parameters: + +param_uart2_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart3 + +Activates serial port 3 (/dev/ttyS3) + +UART 3 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 + +Parameters: + +param_uart3_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart4 + +Activates serial port 4 (/dev/ttyS4) + +UART 4 pins a (TX, RX): PG10, PG11 +UART 4 pins b (TX, RX): PH4, PH5 + +Parameters: + +param_uart4_pins (char) + Determines what pins UART 4 is exposed on + Optional + Default: a + Supported values: a, b + +### uart 5 + +Activates serial port 5 (/dev/ttyS5) + +UART 5 pins (TX, RX): PH6, PH7 + +### uart 6 + +Activates serial port 6 (/dev/ttyS6) + +UART 6 pins (TX, RX): PI12, PI13 + +### uart 7 + +Activates serial port 7 (/dev/ttyS7) + +UART 7 pins (TX, RX): PI20, PI21 + +### w1-gpio + +Activates 1-Wire GPIO master +Requires an external pull-up resistor on the data pin +or enabling the internal pull-up + +Parameters: + +param_w1_pin (pin) + Data pin for 1-Wire master + Optional + Default: PI15 + +param_w1_pin_int_pullup (bool) + Enable internal pull-up for the data pin + Optional + Default: 0 + Set to 1 to enable the pull-up + This option should not be used with multiple sensors or long wires - + please use external pull-up resistor instead diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts b/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts new file mode 100644 index 00000000..9254e22e --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target = <&codec>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-can.dts b/arch/arm/boot/dts/overlay/sun4i-a10-can.dts new file mode 100644 index 00000000..5d394c9f --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-can.dts @@ -0,0 +1,35 @@ +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target = <&pio>; + __overlay__ { + can_pins: can_pins { + pins = "PH20", "PH21"; + function = "can"; + }; + }; + }; + + fragment@1 { + target-path = "/soc@01c00000"; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + can@01c2bc00 { + compatible = "allwinner,sun4i-a10-can"; + reg = <0x01c2bc00 0x400>; + interrupts = ; + clocks = <&apb1_gates 4>; + pinctrl-names = "default"; + pinctrl-0 = <&can_pins>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd new file mode 100644 index 00000000..69af411f --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd @@ -0,0 +1,109 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command + +# setexpr test_var ${tmp_bank} - A +# works only for hex numbers (A-F) + +setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1"; +setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; +test "${tmp_bank}" = "B" && setenv tmp_bank 1; +test "${tmp_bank}" = "C" && setenv tmp_bank 2; +test "${tmp_bank}" = "D" && setenv tmp_bank 3; +test "${tmp_bank}" = "E" && setenv tmp_bank 4; +test "${tmp_bank}" = "G" && setenv tmp_bank 6; +test "${tmp_bank}" = "H" && setenv tmp_bank 7; +test "${tmp_bank}" = "I" && setenv tmp_bank 8' + +if test -n "${param_spinor_spi_bus}"; then + test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@01c05000" + test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@01c06000" + test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@01c17000" + fdt set /soc@01c00000/${tmp_spi_path} status "okay" + fdt set /soc@01c00000/${tmp_spi_path}/spiflash status "okay" + if test -n "${param_spinor_max_freq}"; then + fdt set /soc@01c00000/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_spidev_spi_bus}"; then + test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@01c05000" + test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@01c06000" + test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@01c17000" + fdt set /soc@01c00000/${tmp_spi_path} status "okay" + fdt set /soc@01c00000/${tmp_spi_path}/spidev status "okay" + if test -n "${param_spidev_max_freq}"; then + fdt set /soc@01c00000/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" + fi + env delete tmp_spi_path +fi + +if test "${param_spi2_bus_pins}" = "b"; then + fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/spi2@1 phandle + fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/spi2_cs0@1 phandle + fdt set /soc@01c00000/spi@01c17000 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc@01c00000/spi@01c17000 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test -n "${param_pps_pin}"; then + setenv tmp_bank "${param_pps_pin}" + setenv tmp_pin "${param_pps_pin}" + run decompose_pin + fdt set /soc@01c00000/pinctrl@01c20800/pps_pins pins "${param_pps_pin}" + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800 phandle + fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_pps_falling_edge}" = "1"; then + fdt set /pps@0 assert-falling-edge +fi + +if test "${param_pwm_pins}" = "0"; then + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/pwm0@0 + fdt set /soc@01c00000/pwm@01c20e00 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test "${param_pwm_pins}" = "1"; then + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/pwm1@0 + fdt set /soc@01c00000/pwm@01c20e00 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" + run decompose_pin + fdt set /soc@01c00000/pinctrl@01c20800/w1_pins pins "${param_w1_pin}" + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800 phandle + fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_w1_pin_int_pullup}" = "1"; then + fdt set /soc@01c00000/pinctrl@01c20800/w1_pins bias-pull-up +fi + +if test "${param_uart2_rtscts}" = "1"; then + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart2@0 phandle + fdt set /soc@01c00000/serial@01c28800 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test "${param_uart3_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/uart3 phandle + fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/uart3_rts_cts phandle + fdt set /soc@01c00000/serial@01c28c00 pinctrl-names "default" "default" + fdt set /soc@01c00000/serial@01c28c00 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc@01c00000/serial@01c28c00 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart4_pins}" = "b"; then + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart4@1 phandle + fdt set /soc@01c00000/serial@01c29000 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts b/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts new file mode 100644 index 00000000..44a7ce9b --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts @@ -0,0 +1,22 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + i2c1 = "/soc@01c00000/i2c@01c2b000"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts new file mode 100644 index 00000000..ab3c00fa --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts @@ -0,0 +1,22 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + i2c2 = "/soc@01c00000/i2c@01c2b400"; + }; + }; + + fragment@1 { + target = <&i2c2>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts b/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts new file mode 100644 index 00000000..f0d4c2f3 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts @@ -0,0 +1,103 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target = <&pio>; + __overlay__ { + nand_pins_a: nand_pins@0 { + pins = "PC0", "PC1", "PC2", + "PC5", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14", + "PC15", "PC16"; + function = "nand0"; + }; + + nand_cs0_pins_a: nand_cs@0 { + pins = "PC4"; + function = "nand0"; + }; + + nand_cs1_pins_a: nand_cs@1 { + pins = "PC3"; + function = "nand0"; + }; + + nand_cs2_pins_a: nand_cs@2 { + pins = "PC17"; + function = "nand0"; + }; + + nand_cs3_pins_a: nand_cs@3 { + pins = "PC18"; + function = "nand0"; + }; + + nand_rb0_pins_a: nand_rb@0 { + pins = "PC6"; + function = "nand0"; + }; + + nand_rb1_pins_a: nand_rb@1 { + pins = "PC7"; + function = "nand0"; + }; + }; + }; + + fragment@1 { + target = <&nfc>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>; + status = "okay"; + + nand@0 { + reg = <0>; + allwinner,rb = <0>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "SPL"; + reg = <0x0 0x0 0x0 0x400000>; + }; + + partition@400000 { + label = "SPL.backup"; + reg = <0x0 0x400000 0x0 0x400000>; + }; + + partition@800000 { + label = "U-Boot"; + reg = <0x0 0x800000 0x0 0x400000>; + }; + + partition@c00000 { + label = "U-Boot.backup"; + reg = <0x0 0xc00000 0x0 0x400000>; + }; + + partition@1000000 { + label = "env"; + reg = <0x0 0x1000000 0x0 0x400000>; + }; + + partition@1400000 { + label = "rootfs"; + reg = <0x0 0xa00000 0x01 0xff000000>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts new file mode 100644 index 00000000..6031fc53 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts @@ -0,0 +1,29 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target = <&pio>; + __overlay__ { + pps_pins: pps_pins { + pins = "PI15"; + function = "gpio_in"; + }; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + pps@0 { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pps_pins>; + gpios = <&pio 8 15 0>; /* PI15 */ + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts b/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts new file mode 100644 index 00000000..1927fc52 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target = <&pwm>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts new file mode 100644 index 00000000..5811e474 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts @@ -0,0 +1,38 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target = <&spdif>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pins_a>; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts new file mode 100644 index 00000000..a9feedf8 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts @@ -0,0 +1,65 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + spi0 = "/soc/spi@01c05000"; + spi1 = "/soc/spi@01c06000"; + spi2 = "/soc/spi@01c17000"; + }; + }; + + fragment@1 { + target = <&spi0>; + __overlay__ { + pinctrl-names = "default", "default"; + pinctrl-0 = <&spi0_pins_a>; + pinctrl-1 = <&spi0_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spiflash { + compatible = "jedec,spi-nor"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + fragment@2 { + target = <&spi1>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spiflash { + compatible = "jedec,spi-nor"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + fragment@3 { + target = <&spi2>; + __overlay__ { + pinctrl-names = "default", "default"; + pinctrl-0 = <&spi2_pins_a>; + pinctrl-1 = <&spi2_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spiflash { + compatible = "jedec,spi-nor"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts new file mode 100644 index 00000000..6072c66a --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts @@ -0,0 +1,65 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + spi0 = "/soc/spi@01c05000"; + spi1 = "/soc/spi@01c06000"; + spi2 = "/soc/spi@01c17000"; + }; + }; + + fragment@1 { + target = <&spi0>; + __overlay__ { + pinctrl-names = "default", "default"; + pinctrl-0 = <&spi0_pins_a>; + pinctrl-1 = <&spi0_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spidev { + compatible = "spidev"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + fragment@2 { + target = <&spi1>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spidev { + compatible = "spidev"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + fragment@3 { + target = <&spi2>; + __overlay__ { + pinctrl-names = "default", "default"; + pinctrl-0 = <&spi2_pins_a>; + pinctrl-1 = <&spi2_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spidev { + compatible = "spidev"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts new file mode 100644 index 00000000..3711af57 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts @@ -0,0 +1,37 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + uart2 = "/soc@01c00000/serial@01c28800"; + }; + }; + + fragment@1 { + target = <&pio>; + __overlay__ { + uart2_pins_a: uart2@0 { + pins = "PI16", "PI17", "PI18", "PI19"; + function = "uart2"; + }; + + uart2_pins_a_2: uart2@1 { + pins = "PI18", "PI19"; + function = "uart2"; + }; + }; + }; + + fragment@2 { + target = <&uart2>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a_2>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts new file mode 100644 index 00000000..191e7e79 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts @@ -0,0 +1,37 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + uart3 = "/soc@01c00000/serial@01c28c00"; + }; + }; + + fragment@1 { + target = <&pio>; + __overlay__ { + uart3_pins_a: uart3@0 { + pins = "PG6", "PG7", "PG8", "PG9"; + function = "uart3"; + }; + + uart3_pins_a_2: uart3@1 { + pins = "PG6", "PG7"; + function = "uart3"; + }; + }; + }; + + fragment@2 { + target = <&uart3>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a_2>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts new file mode 100644 index 00000000..0677c634 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts @@ -0,0 +1,37 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + serial4 = "/soc@01c00000/serial@01c29000"; + }; + }; + + fragment@1 { + target = <&pio>; + __overlay__ { + uart4_pins_a: uart4@0 { + pins = "PG10", "PG11"; + function = "uart4"; + }; + + uart4_pins_b: uart4@1 { + pins = "PH4", "PH5"; + function = "uart4"; + }; + }; + }; + + fragment@2 { + target = <&uart4>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts new file mode 100644 index 00000000..0a3ed9b5 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts @@ -0,0 +1,32 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + serial5 = "/soc@01c00000/serial@01c29400"; + }; + }; + + fragment@1 { + target = <&pio>; + __overlay__ { + uart5_pins_a: uart5@0 { + pins = "PH6", "PH7"; + function = "uart5"; + }; + }; + }; + + fragment@2 { + target = <&uart5>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts new file mode 100644 index 00000000..f58b4112 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts @@ -0,0 +1,32 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + serial6 = "/soc@01c00000/serial@01c29800"; + }; + }; + + fragment@1 { + target = <&pio>; + __overlay__ { + uart6_pins_a: uart6@0 { + pins = "PI12", "PI13"; + function = "uart6"; + }; + }; + }; + + fragment@2 { + target = <&uart6>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts new file mode 100644 index 00000000..65d8c688 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts @@ -0,0 +1,32 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + serial7 = "/soc@01c00000/serial@01c29c00"; + }; + }; + + fragment@1 { + target = <&pio>; + __overlay__ { + uart7_pins_a: uart7@0 { + pins = "PI20", "PI21"; + function = "uart7"; + }; + }; + }; + + fragment@2 { + target = <&uart7>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts new file mode 100644 index 00000000..41da08c6 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts @@ -0,0 +1,29 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun4i-a10"; + + fragment@0 { + target = <&pio>; + __overlay__ { + w1_pins: w1_pins { + pins = "PI15"; + function = "gpio_in"; + }; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + onewire@0 { + compatible = "w1-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&w1_pins>; + gpios = <&pio 8 15 0>; /* PI15 */ + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts new file mode 100644 index 00000000..e1a70c51 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target = <&codec>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-can.dts b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts new file mode 100644 index 00000000..8a5b98e2 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts @@ -0,0 +1,35 @@ +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target = <&pio>; + __overlay__ { + can_pins: can_pins { + pins = "PH20", "PH21"; + function = "can"; + }; + }; + }; + + fragment@1 { + target-path = "/soc@01c00000"; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + can@01c2bc00 { + compatible = "allwinner,sun4i-a10-can"; + reg = <0x01c2bc00 0x400>; + interrupts = ; + clocks = <&apb1_gates 4>; + pinctrl-names = "default"; + pinctrl-0 = <&can_pins>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd new file mode 100644 index 00000000..86028d79 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd @@ -0,0 +1,128 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command + +# setexpr test_var ${tmp_bank} - A +# works only for hex numbers (A-F) + +setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1"; +setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; +test "${tmp_bank}" = "B" && setenv tmp_bank 1; +test "${tmp_bank}" = "C" && setenv tmp_bank 2; +test "${tmp_bank}" = "D" && setenv tmp_bank 3; +test "${tmp_bank}" = "E" && setenv tmp_bank 4; +test "${tmp_bank}" = "G" && setenv tmp_bank 6; +test "${tmp_bank}" = "H" && setenv tmp_bank 7; +test "${tmp_bank}" = "I" && setenv tmp_bank 8' + +if test -n "${param_spinor_spi_bus}"; then + test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@01c05000" + test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@01c06000" + test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@01c17000" + fdt set /soc@01c00000/${tmp_spi_path} status "okay" + fdt set /soc@01c00000/${tmp_spi_path}/spiflash status "okay" + if test -n "${param_spinor_max_freq}"; then + fdt set /soc@01c00000/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" + fi + if test "${param_spinor_spi_bus}" = "0" && test "${param_spinor_spi_cs}" = "1"; then + fdt set /soc@01c00000/${tmp_spi_path}/spiflash reg "<1>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_spidev_spi_bus}"; then + test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@01c05000" + test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@01c06000" + test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@01c17000" + fdt set /soc@01c00000/${tmp_spi_path} status "okay" + fdt set /soc@01c00000/${tmp_spi_path}/spidev status "okay" + if test -n "${param_spidev_max_freq}"; then + fdt set /soc@01c00000/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" + fi + if test "${param_spidev_spi_bus}" = "0" && test "${param_spidev_spi_cs}" = "1"; then + fdt set /soc@01c00000/${tmp_spi_path}/spidev reg "<1>" + fi + env delete tmp_spi_path +fi + +if test "${param_spi2_bus_pins}" = "b"; then + fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/spi2@1 phandle + fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/spi2_cs0@1 phandle + fdt set /soc@01c00000/spi@01c17000 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc@01c00000/spi@01c17000 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test -n "${param_pps_pin}"; then + setenv tmp_bank "${param_pps_pin}" + setenv tmp_pin "${param_pps_pin}" + run decompose_pin + fdt set /soc@01c00000/pinctrl@01c20800/pps_pins pins "${param_pps_pin}" + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800 phandle + fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_pps_falling_edge}" = "1"; then + fdt set /pps@0 assert-falling-edge +fi + +if test "${param_pwm_pins}" = "0"; then + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/pwm0@0 + fdt set /soc@01c00000/pwm@01c20e00 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test "${param_pwm_pins}" = "1"; then + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/pwm1@0 + fdt set /soc@01c00000/pwm@01c20e00 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" + run decompose_pin + fdt set /soc@01c00000/pinctrl@01c20800/w1_pins pins "${param_w1_pin}" + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800 phandle + fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test -n "${param_mmc2_cd_pin}"; then + setenv tmp_bank "${param_mmc2_cd_pin}" + setenv tmp_pin "${param_mmc2_cd_pin}" + run decompose_pin + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800 phandle + fdt set /soc@01c00000/mmc@01c11000 cd-gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 1>" +fi + +if test "${param_mmc2_non_removable}" = "1"; then + fdt rm /soc@01c00000/mmc@01c11000 cd-gpios + fdt set /soc@01c00000/mmc@01c11000 non-removable +fi + +if test "${param_w1_pin_int_pullup}" = "1"; then + fdt set /soc@01c00000/pinctrl@01c20800/w1_pins bias-pull-up +fi + +if test "${param_uart2_rtscts}" = "1"; then + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart2@0 phandle + fdt set /soc@01c00000/serial@01c28800 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test "${param_uart3_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/uart3 phandle + fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/uart3_rts_cts phandle + fdt set /soc@01c00000/serial@01c28c00 pinctrl-names "default" "default" + fdt set /soc@01c00000/serial@01c28c00 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc@01c00000/serial@01c28c00 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart4_pins}" = "b"; then + fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart4@1 phandle + fdt set /soc@01c00000/serial@01c29000 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts new file mode 100644 index 00000000..d1146ee4 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts @@ -0,0 +1,22 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + i2c1 = "/soc@01c00000/i2c@01c2b000"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts new file mode 100644 index 00000000..e6b32de5 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts @@ -0,0 +1,22 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + i2c2 = "/soc@01c00000/i2c@01c2b400"; + }; + }; + + fragment@1 { + target = <&i2c2>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts new file mode 100644 index 00000000..5273d06c --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts @@ -0,0 +1,22 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + i2c3 = "/soc@01c00000/i2c@01c2b800"; + }; + }; + + fragment@1 { + target = <&i2c3>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts new file mode 100644 index 00000000..113a220b --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts @@ -0,0 +1,32 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + i2c4 = "/soc@01c00000/i2c@01c2c000"; + }; + }; + + fragment@1 { + target = <&pio>; + __overlay__ { + i2c4_pins_a: i2c4@0 { + pins = "PI2", "PI3"; + function = "i2c4"; + }; + }; + }; + + fragment@2 { + target = <&i2c4>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts new file mode 100644 index 00000000..f1ddbaa2 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts @@ -0,0 +1,18 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target = <&mmc2>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 0 1>; /* PH0, active low */ + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts new file mode 100644 index 00000000..ffa49cc6 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts @@ -0,0 +1,103 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target = <&pio>; + __overlay__ { + nand_pins_a: nand_pins@0 { + pins = "PC0", "PC1", "PC2", + "PC5", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14", + "PC15", "PC16"; + function = "nand0"; + }; + + nand_cs0_pins_a: nand_cs@0 { + pins = "PC4"; + function = "nand0"; + }; + + nand_cs1_pins_a: nand_cs@1 { + pins = "PC3"; + function = "nand0"; + }; + + nand_cs2_pins_a: nand_cs@2 { + pins = "PC17"; + function = "nand0"; + }; + + nand_cs3_pins_a: nand_cs@3 { + pins = "PC18"; + function = "nand0"; + }; + + nand_rb0_pins_a: nand_rb@0 { + pins = "PC6"; + function = "nand0"; + }; + + nand_rb1_pins_a: nand_rb@1 { + pins = "PC7"; + function = "nand0"; + }; + }; + }; + + fragment@1 { + target = <&nfc>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>; + status = "okay"; + + nand@0 { + reg = <0>; + allwinner,rb = <0>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "SPL"; + reg = <0x0 0x0 0x0 0x400000>; + }; + + partition@400000 { + label = "SPL.backup"; + reg = <0x0 0x400000 0x0 0x400000>; + }; + + partition@800000 { + label = "U-Boot"; + reg = <0x0 0x800000 0x0 0x400000>; + }; + + partition@c00000 { + label = "U-Boot.backup"; + reg = <0x0 0xc00000 0x0 0x400000>; + }; + + partition@1000000 { + label = "env"; + reg = <0x0 0x1000000 0x0 0x400000>; + }; + + partition@1400000 { + label = "rootfs"; + reg = <0x0 0xa00000 0x01 0xff000000>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts new file mode 100644 index 00000000..fe3e2bd9 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts @@ -0,0 +1,29 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target = <&pio>; + __overlay__ { + pps_pins: pps_pins { + pins = "PI15"; + function = "gpio_in"; + }; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + pps@0 { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pps_pins>; + gpios = <&pio 8 15 0>; /* PI15 */ + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts b/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts new file mode 100644 index 00000000..a0cc4695 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target = <&pwm>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts new file mode 100644 index 00000000..7983ad0e --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts @@ -0,0 +1,38 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target = <&spdif>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pins_a>; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts new file mode 100644 index 00000000..2de39a20 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts @@ -0,0 +1,16 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + pinctrl-names = "default", "default", "default"; + pinctrl-0 = <&spi0_pins_a>; + pinctrl-1 = <&spi0_cs0_pins_a>; + pinctrl-2 = <&spi0_cs1_pins_a>; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts new file mode 100644 index 00000000..08177a33 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts @@ -0,0 +1,65 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + spi0 = "/soc/spi@01c05000"; + spi1 = "/soc/spi@01c06000"; + spi2 = "/soc/spi@01c17000"; + }; + }; + + fragment@1 { + target = <&spi0>; + __overlay__ { + pinctrl-names = "default", "default"; + pinctrl-0 = <&spi0_pins_a>; + pinctrl-1 = <&spi0_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spiflash { + compatible = "jedec,spi-nor"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + fragment@2 { + target = <&spi1>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spiflash { + compatible = "jedec,spi-nor"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + fragment@3 { + target = <&spi2>; + __overlay__ { + pinctrl-names = "default", "default"; + pinctrl-0 = <&spi2_pins_a>; + pinctrl-1 = <&spi2_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spiflash { + compatible = "jedec,spi-nor"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts new file mode 100644 index 00000000..c52ba0e4 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts @@ -0,0 +1,65 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + spi0 = "/soc/spi@01c05000"; + spi1 = "/soc/spi@01c06000"; + spi2 = "/soc/spi@01c17000"; + }; + }; + + fragment@1 { + target = <&spi0>; + __overlay__ { + pinctrl-names = "default", "default"; + pinctrl-0 = <&spi0_pins_a>; + pinctrl-1 = <&spi0_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spidev { + compatible = "spidev"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + fragment@2 { + target = <&spi1>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spidev { + compatible = "spidev"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + fragment@3 { + target = <&spi2>; + __overlay__ { + pinctrl-names = "default", "default"; + pinctrl-0 = <&spi2_pins_a>; + pinctrl-1 = <&spi2_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + spidev { + compatible = "spidev"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts new file mode 100644 index 00000000..721a02de --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts @@ -0,0 +1,32 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + uart2 = "/soc@01c00000/serial@01c28800"; + }; + }; + + fragment@1 { + target = <&pio>; + __overlay__ { + uart2_pins_a_2: uart2@1 { + pins = "PI18", "PI19"; + function = "uart2"; + }; + }; + }; + + fragment@2 { + target = <&uart2>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a_2>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts new file mode 100644 index 00000000..5c430438 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts @@ -0,0 +1,32 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + uart3 = "/soc@01c00000/serial@01c28c00"; + }; + }; + + fragment@1 { + target = <&pio>; + __overlay__ { + uart3_pins_a_2: uart3@2 { + pins = "PG6", "PG7"; + function = "uart3"; + }; + }; + }; + + fragment@2 { + target = <&uart3>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a_2>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts new file mode 100644 index 00000000..008cf83a --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts @@ -0,0 +1,22 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + serial4 = "/soc@01c00000/serial@01c29000"; + }; + }; + + fragment@1 { + target = <&uart4>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts new file mode 100644 index 00000000..32367102 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts @@ -0,0 +1,22 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + serial5 = "/soc@01c00000/serial@01c29400"; + }; + }; + + fragment@1 { + target = <&uart5>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts new file mode 100644 index 00000000..12435386 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts @@ -0,0 +1,22 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + serial6 = "/soc@01c00000/serial@01c29800"; + }; + }; + + fragment@1 { + target = <&uart6>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts new file mode 100644 index 00000000..3087271b --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts @@ -0,0 +1,22 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + serial7 = "/soc@01c00000/serial@01c29c00"; + }; + }; + + fragment@1 { + target = <&uart7>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts new file mode 100644 index 00000000..7d77606a --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts @@ -0,0 +1,29 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { + target = <&pio>; + __overlay__ { + w1_pins: w1_pins { + pins = "PI15"; + function = "gpio_in"; + }; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + onewire@0 { + compatible = "w1-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&w1_pins>; + gpios = <&pio 8 15 0>; /* PI15 */ + status = "okay"; + }; + }; + }; +};