diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index dc785da9c..141fd186b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -113,6 +113,12 @@ clock-latency-ns = <244144>; /* 8 32k periods */ }; + opp@1640000000 { + opp-hz = /bits/ 64 <1640000000>; + opp-microvolt = <1160000 1160000 1160000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + opp@1800000000 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <1160000 1160000 1160000>; @@ -254,6 +260,26 @@ #reset-cells = <1>; }; + dma: dma-controller@3002000 { + compatible = "allwinner,sun8i-h3-dma"; + reg = <0x03002000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + + gic: interrupt-controller@3021000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + sid: sid@3006000 { compatible = "allwinner,sun50i-h6-sid"; reg = <0x03006000 0x400>; @@ -279,6 +305,7 @@ interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ ext_rgmii_pins: rgmii-pins { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD7", "PD8", "PD9", "PD10", @@ -292,6 +319,24 @@ function = "hdmi"; }; + i2c0_pins: i2c0 { + pins = "PD25", "PD26"; + function = "i2c0"; + pull = <1>; + }; + + i2c1_pins: i2c1 { + pins = "PH5", "PH6"; + function = "i2c1"; + pull = <1>; + }; + + i2c2_pins: i2c2 { + pins = "PD23", "PD24"; + function = "i2c2"; + pull = <1>; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -309,6 +354,7 @@ bias-pull-up; }; + /omit-if-no-ref/ mmc2_pins: mmc2-pins { pins = "PC1", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", @@ -318,6 +364,16 @@ bias-pull-up; }; + spi0_pins: spi0-pins { + pins = "PC2", "PC3", "PC0", "PC5"; + function = "spi0"; + }; + + spi1_pins: spi1-pins { + pins = "PH5", "PH6", "PH4", "PH3"; + function = "spi1"; + }; + uart0_ph_pins: uart0-ph-pins { pins = "PH0", "PH1"; function = "uart0"; @@ -332,17 +388,65 @@ pins = "PG8", "PG9"; function = "uart1"; }; + + uart2_pins: uart2-pins { + pins = "PD19", "PD20"; + function = "uart2"; + }; + + uart2_rts_cts_pins: uart2-rts-cts-pins { + pins = "PD21", "PD22"; + function = "uart2"; + }; + + uart3_pins: uart3-pins { + pins = "PD23", "PD24"; + function = "uart3"; + }; + + uart3_rts_cts_pins: uart3-rts-cts-pins { + pins = "PD25", "PD26"; + function = "uart3"; + }; }; - gic: interrupt-controller@3021000 { - compatible = "arm,gic-400"; - reg = <0x03021000 0x1000>, - <0x03022000 0x2000>, - <0x03024000 0x2000>, - <0x03026000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; + i2c0: i2c@5002000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x05002000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@5002400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x05002400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@5002800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x05002800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc0: mmc@4020000 { @@ -391,6 +495,38 @@ #size-cells = <0>; }; + spi0: spi@5010000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x05010000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@5011000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x05011000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + uart0: serial@5000000 { compatible = "snps,dw-apb-uart"; reg = <0x05000000 0x400>; @@ -768,6 +904,29 @@ pins = "PL0", "PL1"; function = "s_i2c"; }; + + r_ir_rx_pins: r-ir-rx-pins { + pins = "PL9"; + function = "s_cir_rx"; + }; + + r_uart_pins: r-uart-pins { + pins = "PL2", "PL3"; + function = "s_uart"; + }; + }; + + r_uart: serial@7080000 { + compatible = "snps,dw-apb-uart"; + reg = <0x07080000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&r_ccu CLK_R_APB2_UART>; + resets = <&r_ccu RST_R_APB2_UART>; + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins>; + status = "disabled"; }; r_i2c: i2c@7081400 { @@ -782,6 +941,16 @@ #address-cells = <1>; #size-cells = <0>; }; + + ir: ir@7040000 { + compatible = "allwinner,sun5i-a13-ir"; + clocks = <&r_ccu CLK_R_APB1_IR>, <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_R_APB1_IR>; + interrupts = ; + reg = <0x07040000 0x400>; + status = "disabled"; + }; }; thermal-zones {