From 7e7c821aec6eb45f26b40f3ec2f3d8408ec58300 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Mon, 21 May 2018 18:47:02 +0800 Subject: [PATCH 062/146] drm/lima: lima_reg.h use BIT() Signed-off-by: Qiang Yu --- drivers/gpu/drm/lima/lima_regs.h | 238 +++++++++++++++---------------- 1 file changed, 119 insertions(+), 119 deletions(-) diff --git a/drivers/gpu/drm/lima/lima_regs.h b/drivers/gpu/drm/lima/lima_regs.h index 0d8dced21633..91ae9d6c197b 100644 --- a/drivers/gpu/drm/lima/lima_regs.h +++ b/drivers/gpu/drm/lima/lima_regs.h @@ -9,9 +9,9 @@ /* PMU regs */ #define LIMA_PMU_POWER_UP 0x00 #define LIMA_PMU_POWER_DOWN 0x04 -#define LIMA_PMU_POWER_GP0_MASK (1 << 0) -#define LIMA_PMU_POWER_L2_MASK (1 << 1) -#define LIMA_PMU_POWER_PP_MASK(i) (1 << (2 + i)) +#define LIMA_PMU_POWER_GP0_MASK BIT(0) +#define LIMA_PMU_POWER_L2_MASK BIT(1) +#define LIMA_PMU_POWER_PP_MASK(i) BIT(2 + i) /* * On Mali450 each block automatically starts up its corresponding L2 @@ -26,25 +26,25 @@ #define LIMA_PMU_INT_MASK 0x0C #define LIMA_PMU_INT_RAWSTAT 0x10 #define LIMA_PMU_INT_CLEAR 0x18 -#define LIMA_PMU_INT_CMD_MASK (1 << 0) +#define LIMA_PMU_INT_CMD_MASK BIT(0) #define LIMA_PMU_SW_DELAY 0x1C /* L2 cache regs */ -#define LIMA_L2_CACHE_SIZE 0x0004 -#define LIMA_L2_CACHE_STATUS 0x0008 -#define LIMA_L2_CACHE_STATUS_COMMAND_BUSY (1 << 0) -#define LIMA_L2_CACHE_STATUS_DATA_BUSY (1 << 1) -#define LIMA_L2_CACHE_COMMAND 0x0010 -#define LIMA_L2_CACHE_COMMAND_CLEAR_ALL (1 << 0) -#define LIMA_L2_CACHE_CLEAR_PAGE 0x0014 -#define LIMA_L2_CACHE_MAX_READS 0x0018 -#define LIMA_L2_CACHE_ENABLE 0x001C -#define LIMA_L2_CACHE_ENABLE_ACCESS (1 << 0) -#define LIMA_L2_CACHE_ENABLE_READ_ALLOCATE (1 << 1) -#define LIMA_L2_CACHE_PERFCNT_SRC0 0x0020 -#define LIMA_L2_CACHE_PERFCNT_VAL0 0x0024 -#define LIMA_L2_CACHE_PERFCNT_SRC1 0x0028 -#define LIMA_L2_CACHE_ERFCNT_VAL1 0x002C +#define LIMA_L2_CACHE_SIZE 0x0004 +#define LIMA_L2_CACHE_STATUS 0x0008 +#define LIMA_L2_CACHE_STATUS_COMMAND_BUSY BIT(0) +#define LIMA_L2_CACHE_STATUS_DATA_BUSY BIT(1) +#define LIMA_L2_CACHE_COMMAND 0x0010 +#define LIMA_L2_CACHE_COMMAND_CLEAR_ALL BIT(0) +#define LIMA_L2_CACHE_CLEAR_PAGE 0x0014 +#define LIMA_L2_CACHE_MAX_READS 0x0018 +#define LIMA_L2_CACHE_ENABLE 0x001C +#define LIMA_L2_CACHE_ENABLE_ACCESS BIT(0) +#define LIMA_L2_CACHE_ENABLE_READ_ALLOCATE BIT(1) +#define LIMA_L2_CACHE_PERFCNT_SRC0 0x0020 +#define LIMA_L2_CACHE_PERFCNT_VAL0 0x0024 +#define LIMA_L2_CACHE_PERFCNT_SRC1 0x0028 +#define LIMA_L2_CACHE_ERFCNT_VAL1 0x002C /* GP regs */ #define LIMA_GP_VSCL_START_ADDR 0x00 @@ -54,36 +54,36 @@ #define LIMA_GP_PLBU_ALLOC_START_ADDR 0x10 #define LIMA_GP_PLBU_ALLOC_END_ADDR 0x14 #define LIMA_GP_CMD 0x20 -#define LIMA_GP_CMD_START_VS (1 << 0) -#define LIMA_GP_CMD_START_PLBU (1 << 1) -#define LIMA_GP_CMD_UPDATE_PLBU_ALLOC (1 << 4) -#define LIMA_GP_CMD_RESET (1 << 5) -#define LIMA_GP_CMD_FORCE_HANG (1 << 6) -#define LIMA_GP_CMD_STOP_BUS (1 << 9) -#define LIMA_GP_CMD_SOFT_RESET (1 << 10) +#define LIMA_GP_CMD_START_VS BIT(0) +#define LIMA_GP_CMD_START_PLBU BIT(1) +#define LIMA_GP_CMD_UPDATE_PLBU_ALLOC BIT(4) +#define LIMA_GP_CMD_RESET BIT(5) +#define LIMA_GP_CMD_FORCE_HANG BIT(6) +#define LIMA_GP_CMD_STOP_BUS BIT(9) +#define LIMA_GP_CMD_SOFT_RESET BIT(10) #define LIMA_GP_INT_RAWSTAT 0x24 #define LIMA_GP_INT_CLEAR 0x28 #define LIMA_GP_INT_MASK 0x2C #define LIMA_GP_INT_STAT 0x30 -#define LIMA_GP_IRQ_VS_END_CMD_LST (1 << 0) -#define LIMA_GP_IRQ_PLBU_END_CMD_LST (1 << 1) -#define LIMA_GP_IRQ_PLBU_OUT_OF_MEM (1 << 2) -#define LIMA_GP_IRQ_VS_SEM_IRQ (1 << 3) -#define LIMA_GP_IRQ_PLBU_SEM_IRQ (1 << 4) -#define LIMA_GP_IRQ_HANG (1 << 5) -#define LIMA_GP_IRQ_FORCE_HANG (1 << 6) -#define LIMA_GP_IRQ_PERF_CNT_0_LIMIT (1 << 7) -#define LIMA_GP_IRQ_PERF_CNT_1_LIMIT (1 << 8) -#define LIMA_GP_IRQ_WRITE_BOUND_ERR (1 << 9) -#define LIMA_GP_IRQ_SYNC_ERROR (1 << 10) -#define LIMA_GP_IRQ_AXI_BUS_ERROR (1 << 11) -#define LIMA_GP_IRQ_AXI_BUS_STOPPED (1 << 12) -#define LIMA_GP_IRQ_VS_INVALID_CMD (1 << 13) -#define LIMA_GP_IRQ_PLB_INVALID_CMD (1 << 14) -#define LIMA_GP_IRQ_RESET_COMPLETED (1 << 19) -#define LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW (1 << 20) -#define LIMA_GP_IRQ_SEMAPHORE_OVERFLOW (1 << 21) -#define LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS (1 << 22) +#define LIMA_GP_IRQ_VS_END_CMD_LST BIT(0) +#define LIMA_GP_IRQ_PLBU_END_CMD_LST BIT(1) +#define LIMA_GP_IRQ_PLBU_OUT_OF_MEM BIT(2) +#define LIMA_GP_IRQ_VS_SEM_IRQ BIT(3) +#define LIMA_GP_IRQ_PLBU_SEM_IRQ BIT(4) +#define LIMA_GP_IRQ_HANG BIT(5) +#define LIMA_GP_IRQ_FORCE_HANG BIT(6) +#define LIMA_GP_IRQ_PERF_CNT_0_LIMIT BIT(7) +#define LIMA_GP_IRQ_PERF_CNT_1_LIMIT BIT(8) +#define LIMA_GP_IRQ_WRITE_BOUND_ERR BIT(9) +#define LIMA_GP_IRQ_SYNC_ERROR BIT(10) +#define LIMA_GP_IRQ_AXI_BUS_ERROR BIT(11) +#define LIMA_GP_IRQ_AXI_BUS_STOPPED BIT(12) +#define LIMA_GP_IRQ_VS_INVALID_CMD BIT(13) +#define LIMA_GP_IRQ_PLB_INVALID_CMD BIT(14) +#define LIMA_GP_IRQ_RESET_COMPLETED BIT(19) +#define LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW BIT(20) +#define LIMA_GP_IRQ_SEMAPHORE_OVERFLOW BIT(21) +#define LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS BIT(22) #define LIMA_GP_WRITE_BOUND_LOW 0x34 #define LIMA_GP_PERF_CNT_0_ENABLE 0x3C #define LIMA_GP_PERF_CNT_1_ENABLE 0x40 @@ -93,11 +93,11 @@ #define LIMA_GP_PERF_CNT_1_VALUE 0x50 #define LIMA_GP_PERF_CNT_0_LIMIT 0x54 #define LIMA_GP_STATUS 0x68 -#define LIMA_GP_STATUS_VS_ACTIVE (1 << 1) -#define LIMA_GP_STATUS_BUS_STOPPED (1 << 2) -#define LIMA_GP_STATUS_PLBU_ACTIVE (1 << 3) -#define LIMA_GP_STATUS_BUS_ERROR (1 << 6) -#define LIMA_GP_STATUS_WRITE_BOUND_ERR (1 << 8) +#define LIMA_GP_STATUS_VS_ACTIVE BIT(1) +#define LIMA_GP_STATUS_BUS_STOPPED BIT(2) +#define LIMA_GP_STATUS_PLBU_ACTIVE BIT(3) +#define LIMA_GP_STATUS_BUS_ERROR BIT(6) +#define LIMA_GP_STATUS_WRITE_BOUND_ERR BIT(8) #define LIMA_GP_VERSION 0x6C #define LIMA_GP_VSCL_START_ADDR_READ 0x80 #define LIMA_GP_PLBCL_START_ADDR_READ 0x84 @@ -156,42 +156,42 @@ #define LIMA_PP_VERSION 0x1000 #define LIMA_PP_CURRENT_REND_LIST_ADDR 0x1004 -#define LIMA_PP_STATUS 0x1008 -#define LIMA_PP_STATUS_RENDERING_ACTIVE (1 << 0) -#define LIMA_PP_STATUS_BUS_STOPPED (1 << 4) -#define LIMA_PP_CTRL 0x100c -#define LIMA_PP_CTRL_STOP_BUS (1 << 0) -#define LIMA_PP_CTRL_FLUSH_CACHES (1 << 3) -#define LIMA_PP_CTRL_FORCE_RESET (1 << 5) -#define LIMA_PP_CTRL_START_RENDERING (1 << 6) -#define LIMA_PP_CTRL_SOFT_RESET (1 << 7) -#define LIMA_PP_INT_RAWSTAT 0x1020 -#define LIMA_PP_INT_CLEAR 0x1024 -#define LIMA_PP_INT_MASK 0x1028 -#define LIMA_PP_INT_STATUS 0x102c -#define LIMA_PP_IRQ_END_OF_FRAME (1 << 0) -#define LIMA_PP_IRQ_END_OF_TILE (1 << 1) -#define LIMA_PP_IRQ_HANG (1 << 2) -#define LIMA_PP_IRQ_FORCE_HANG (1 << 3) -#define LIMA_PP_IRQ_BUS_ERROR (1 << 4) -#define LIMA_PP_IRQ_BUS_STOP (1 << 5) -#define LIMA_PP_IRQ_CNT_0_LIMIT (1 << 6) -#define LIMA_PP_IRQ_CNT_1_LIMIT (1 << 7) -#define LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR (1 << 8) -#define LIMA_PP_IRQ_INVALID_PLIST_COMMAND (1 << 9) -#define LIMA_PP_IRQ_CALL_STACK_UNDERFLOW (1 << 10) -#define LIMA_PP_IRQ_CALL_STACK_OVERFLOW (1 << 11) -#define LIMA_PP_IRQ_RESET_COMPLETED (1 << 12) -#define LIMA_PP_WRITE_BOUNDARY_LOW 0x1044 -#define LIMA_PP_BUS_ERROR_STATUS 0x1050 -#define LIMA_PP_PERF_CNT_0_ENABLE 0x1080 -#define LIMA_PP_PERF_CNT_0_SRC 0x1084 -#define LIMA_PP_PERF_CNT_0_LIMIT 0x1088 -#define LIMA_PP_PERF_CNT_0_VALUE 0x108c -#define LIMA_PP_PERF_CNT_1_ENABLE 0x10a0 -#define LIMA_PP_PERF_CNT_1_SRC 0x10a4 -#define LIMA_PP_PERF_CNT_1_LIMIT 0x10a8 -#define LIMA_PP_PERF_CNT_1_VALUE 0x10ac +#define LIMA_PP_STATUS 0x1008 +#define LIMA_PP_STATUS_RENDERING_ACTIVE BIT(0) +#define LIMA_PP_STATUS_BUS_STOPPED BIT(4) +#define LIMA_PP_CTRL 0x100c +#define LIMA_PP_CTRL_STOP_BUS BIT(0) +#define LIMA_PP_CTRL_FLUSH_CACHES BIT(3) +#define LIMA_PP_CTRL_FORCE_RESET BIT(5) +#define LIMA_PP_CTRL_START_RENDERING BIT(6) +#define LIMA_PP_CTRL_SOFT_RESET BIT(7) +#define LIMA_PP_INT_RAWSTAT 0x1020 +#define LIMA_PP_INT_CLEAR 0x1024 +#define LIMA_PP_INT_MASK 0x1028 +#define LIMA_PP_INT_STATUS 0x102c +#define LIMA_PP_IRQ_END_OF_FRAME BIT(0) +#define LIMA_PP_IRQ_END_OF_TILE BIT(1) +#define LIMA_PP_IRQ_HANG BIT(2) +#define LIMA_PP_IRQ_FORCE_HANG BIT(3) +#define LIMA_PP_IRQ_BUS_ERROR BIT(4) +#define LIMA_PP_IRQ_BUS_STOP BIT(5) +#define LIMA_PP_IRQ_CNT_0_LIMIT BIT(6) +#define LIMA_PP_IRQ_CNT_1_LIMIT BIT(7) +#define LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR BIT(8) +#define LIMA_PP_IRQ_INVALID_PLIST_COMMAND BIT(9) +#define LIMA_PP_IRQ_CALL_STACK_UNDERFLOW BIT(10) +#define LIMA_PP_IRQ_CALL_STACK_OVERFLOW BIT(11) +#define LIMA_PP_IRQ_RESET_COMPLETED BIT(12) +#define LIMA_PP_WRITE_BOUNDARY_LOW 0x1044 +#define LIMA_PP_BUS_ERROR_STATUS 0x1050 +#define LIMA_PP_PERF_CNT_0_ENABLE 0x1080 +#define LIMA_PP_PERF_CNT_0_SRC 0x1084 +#define LIMA_PP_PERF_CNT_0_LIMIT 0x1088 +#define LIMA_PP_PERF_CNT_0_VALUE 0x108c +#define LIMA_PP_PERF_CNT_1_ENABLE 0x10a0 +#define LIMA_PP_PERF_CNT_1_SRC 0x10a4 +#define LIMA_PP_PERF_CNT_1_LIMIT 0x10a8 +#define LIMA_PP_PERF_CNT_1_VALUE 0x10ac #define LIMA_PP_PERFMON_CONTR 0x10b0 #define LIMA_PP_PERFMON_BASE 0x10b4 @@ -226,41 +226,41 @@ LIMA_PP_IRQ_MASK_ERROR) /* MMU regs */ -#define LIMA_MMU_DTE_ADDR 0x0000 -#define LIMA_MMU_STATUS 0x0004 -#define LIMA_MMU_STATUS_PAGING_ENABLED (1 << 0) -#define LIMA_MMU_STATUS_PAGE_FAULT_ACTIVE (1 << 1) -#define LIMA_MMU_STATUS_STALL_ACTIVE (1 << 2) -#define LIMA_MMU_STATUS_IDLE (1 << 3) -#define LIMA_MMU_STATUS_REPLAY_BUFFER_EMPTY (1 << 4) -#define LIMA_MMU_STATUS_PAGE_FAULT_IS_WRITE (1 << 5) +#define LIMA_MMU_DTE_ADDR 0x0000 +#define LIMA_MMU_STATUS 0x0004 +#define LIMA_MMU_STATUS_PAGING_ENABLED BIT(0) +#define LIMA_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1) +#define LIMA_MMU_STATUS_STALL_ACTIVE BIT(2) +#define LIMA_MMU_STATUS_IDLE BIT(3) +#define LIMA_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) +#define LIMA_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) #define LIMA_MMU_STATUS_BUS_ID(x) ((x >> 6) & 0x1F) -#define LIMA_MMU_COMMAND 0x0008 -#define LIMA_MMU_COMMAND_ENABLE_PAGING 0x00 -#define LIMA_MMU_COMMAND_DISABLE_PAGING 0x01 -#define LIMA_MMU_COMMAND_ENABLE_STALL 0x02 -#define LIMA_MMU_COMMAND_DISABLE_STALL 0x03 -#define LIMA_MMU_COMMAND_ZAP_CACHE 0x04 -#define LIMA_MMU_COMMAND_PAGE_FAULT_DONE 0x05 -#define LIMA_MMU_COMMAND_HARD_RESET 0x06 -#define LIMA_MMU_PAGE_FAULT_ADDR 0x000C -#define LIMA_MMU_ZAP_ONE_LINE 0x0010 -#define LIMA_MMU_INT_RAWSTAT 0x0014 -#define LIMA_MMU_INT_CLEAR 0x0018 -#define LIMA_MMU_INT_MASK 0x001C -#define LIMA_MMU_INT_PAGE_FAULT 0x01 -#define LIMA_MMU_INT_READ_BUS_ERROR 0x02 -#define LIMA_MMU_INT_STATUS 0x0020 +#define LIMA_MMU_COMMAND 0x0008 +#define LIMA_MMU_COMMAND_ENABLE_PAGING 0x00 +#define LIMA_MMU_COMMAND_DISABLE_PAGING 0x01 +#define LIMA_MMU_COMMAND_ENABLE_STALL 0x02 +#define LIMA_MMU_COMMAND_DISABLE_STALL 0x03 +#define LIMA_MMU_COMMAND_ZAP_CACHE 0x04 +#define LIMA_MMU_COMMAND_PAGE_FAULT_DONE 0x05 +#define LIMA_MMU_COMMAND_HARD_RESET 0x06 +#define LIMA_MMU_PAGE_FAULT_ADDR 0x000C +#define LIMA_MMU_ZAP_ONE_LINE 0x0010 +#define LIMA_MMU_INT_RAWSTAT 0x0014 +#define LIMA_MMU_INT_CLEAR 0x0018 +#define LIMA_MMU_INT_MASK 0x001C +#define LIMA_MMU_INT_PAGE_FAULT BIT(0) +#define LIMA_MMU_INT_READ_BUS_ERROR BIT(1) +#define LIMA_MMU_INT_STATUS 0x0020 -#define LIMA_VM_FLAG_PRESENT (1 << 0) -#define LIMA_VM_FLAG_READ_PERMISSION (1 << 1) -#define LIMA_VM_FLAG_WRITE_PERMISSION (1 << 2) -#define LIMA_VM_FLAG_OVERRIDE_CACHE (1 << 3) -#define LIMA_VM_FLAG_WRITE_CACHEABLE (1 << 4) -#define LIMA_VM_FLAG_WRITE_ALLOCATE (1 << 5) -#define LIMA_VM_FLAG_WRITE_BUFFERABLE (1 << 6) -#define LIMA_VM_FLAG_READ_CACHEABLE (1 << 7) -#define LIMA_VM_FLAG_READ_ALLOCATE (1 << 8) +#define LIMA_VM_FLAG_PRESENT BIT(0) +#define LIMA_VM_FLAG_READ_PERMISSION BIT(1) +#define LIMA_VM_FLAG_WRITE_PERMISSION BIT(2) +#define LIMA_VM_FLAG_OVERRIDE_CACHE BIT(3) +#define LIMA_VM_FLAG_WRITE_CACHEABLE BIT(4) +#define LIMA_VM_FLAG_WRITE_ALLOCATE BIT(5) +#define LIMA_VM_FLAG_WRITE_BUFFERABLE BIT(6) +#define LIMA_VM_FLAG_READ_CACHEABLE BIT(7) +#define LIMA_VM_FLAG_READ_ALLOCATE BIT(8) #define LIMA_VM_FLAG_MASK 0x1FF #define LIMA_VM_FLAGS_CACHE ( \ -- 2.17.1