diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 9a5464c62..91142959c 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -341,17 +341,18 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
  * with all ones or all zeros in the low bits. Bound the loop by the maximum
  * number of CPU cycles in 3 consecutive 24 MHz counter periods.
  */
-#define __sun50i_a64_read_reg(reg) ({					\
-	u64 _val;							\
-	int _retries = 150;						\
-									\
-	do {								\
-		_val = read_sysreg(reg);				\
-		_retries--;						\
-	} while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries);	\
-									\
-	WARN_ON_ONCE(!_retries);					\
-	_val;								\
+#define __sun50i_a64_read_reg(reg) ({							\
+	u64 _old, _new;												\
+	int _retries = 200;											\
+																\
+	do {														\
+		_old = read_sysreg(reg);								\
+		_new = read_sysreg(reg);								\
+		_retries--;												\
+	} while (unlikely(_old != _new) && _retries);				\
+																\
+	WARN_ON_ONCE(!_retries);									\
+	_new;														\
 })
 
 static u64 notrace sun50i_a64_read_cntpct_el0(void)