diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d6546d2676b9..26fbba6273ed 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -938,6 +938,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3188-px3-evb.dtb \ rk3188-radxarock.dtb \ rk3228-evb.dtb \ + rk3228a-box.dtb \ + rk3228a-box-h96mini.dtb \ + rk3228a-box-nand.dtb \ + rk3229-box.dtb \ + rk3229-box-a95xr1.dtb \ + rk3229-box-nand.dtb \ rk3229-evb.dtb \ rk3229-xms6.dtb \ rk3288-evb-act8846.dtb \ diff --git a/arch/arm/boot/dts/rk3228a-box-h96mini.dts b/arch/arm/boot/dts/rk3228a-box-h96mini.dts new file mode 100644 index 000000000000..c624500d1470 --- /dev/null +++ b/arch/arm/boot/dts/rk3228a-box-h96mini.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include "rk3228a-box.dtsi" + +/ { + compatible = "eledvb,h96mini", "rockchip,rk3228a-box", "rockchip,rk3229"; + model = "Rockchip RK3228A Box H96 mini"; + + leds { + compatible = "gpio-leds"; + + led_green { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red { + gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + +}; + +&emmc { + mmc-hs200-1_8v; + status = "okay"; +}; + +&gmac { + tx_delay = <0x26>; + rx_delay = <0x11>; +}; + +&ir_receiver { + status = "okay"; +}; + +&pinctrl { + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + bt { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&power_key { + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + brcm,drive-strength = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + disable-wp; + status = "okay"; +}; + +&uart1 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + host-wakeup-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + }; +}; + +&usb_otg { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/rk3228a-box-nand.dts b/arch/arm/boot/dts/rk3228a-box-nand.dts new file mode 100644 index 000000000000..f3e5ab89462b --- /dev/null +++ b/arch/arm/boot/dts/rk3228a-box-nand.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3228a-box.dtsi" + +/ { + model = "Rockchip RK3228A Box"; + + leds { + compatible = "gpio-leds"; + + led_blue { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red { + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + +}; + +&ir_receiver { + status = "okay"; +}; + +&nfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <60>; + nand-ecc-step-size = <1024>; + nand-bus-width = <8>; + }; +}; + +&sdio { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/rk3228a-box.dts b/arch/arm/boot/dts/rk3228a-box.dts new file mode 100644 index 000000000000..e68ef44b95c9 --- /dev/null +++ b/arch/arm/boot/dts/rk3228a-box.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3228a-box.dtsi" + +/ { + model = "Rockchip RK3228A Box"; + + leds { + compatible = "gpio-leds"; + + led_blue { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red { + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + +}; + +&emmc { + status = "okay"; +}; + +&ir_receiver { + status = "okay"; +}; + +&sdio { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/rk3228a-box.dtsi b/arch/arm/boot/dts/rk3228a-box.dtsi new file mode 100644 index 000000000000..dbd5c5dc4491 --- /dev/null +++ b/arch/arm/boot/dts/rk3228a-box.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk322x-box.dtsi" + +/ { + + model = "Rockchip RK3228A Box"; + compatible = "rockchip,rk3228a-box", "rockchip,rk3229"; + +}; diff --git a/arch/arm/boot/dts/rk3229-box-a95xr1.dts b/arch/arm/boot/dts/rk3229-box-a95xr1.dts new file mode 100644 index 000000000000..b3695fb0b255 --- /dev/null +++ b/arch/arm/boot/dts/rk3229-box-a95xr1.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include "rk3229-box.dtsi" + +/ { + model = "Rockchip RK3229 Box A95X-R1"; + + leds { + compatible = "gpio-leds"; + + led_blue { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red { + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "rc-feedback"; + }; + }; + +}; + +&emmc { + mmc-hs200-1_8v; + status = "okay"; +}; + +&gmac { + tx_delay = <0x26>; + rx_delay = <0x11>; +}; + +&ir_receiver { + status = "okay"; +}; + +&power_key { + status = "okay"; +}; + +&sdio { + status = "okay"; +}; + +&sdmmc { + disable-wp; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/rk3229-box-nand.dts b/arch/arm/boot/dts/rk3229-box-nand.dts new file mode 100644 index 000000000000..5eca0f335c55 --- /dev/null +++ b/arch/arm/boot/dts/rk3229-box-nand.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3229-box.dtsi" + +/ { + model = "Rockchip RK3229 Box"; + + leds { + compatible = "gpio-leds"; + + led_green { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red { + gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&ir_receiver { + status = "okay"; +}; + +&nfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <60>; + nand-ecc-step-size = <1024>; + nand-bus-width = <8>; + }; +}; + +&power_key { + status = "okay"; +}; + +&sdio { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/rk3229-box.dts b/arch/arm/boot/dts/rk3229-box.dts new file mode 100644 index 000000000000..b63e61cda257 --- /dev/null +++ b/arch/arm/boot/dts/rk3229-box.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3229-box.dtsi" + +/ { + model = "Rockchip RK3229 Box"; + + leds { + compatible = "gpio-leds"; + + led_green { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red { + gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&emmc { + status = "okay"; +}; + +&ir_receiver { + status = "okay"; +}; + +&power_key { + status = "okay"; +}; + +&sdio { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/rk3229-box.dtsi b/arch/arm/boot/dts/rk3229-box.dtsi new file mode 100644 index 000000000000..79e2524e07f2 --- /dev/null +++ b/arch/arm/boot/dts/rk3229-box.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk322x-box.dtsi" +#include "rk3229-cpu-opp.dtsi" + +/ { + + model = "Rockchip RK3229 Box"; + compatible = "rockchip,rk3229-box", "rockchip,rk3229"; + +}; + +&cpu0_opp_table { + + opp-1464000000 { + status = "disabled"; + }; + +}; diff --git a/arch/arm/boot/dts/rk3229-cpu-opp.dtsi b/arch/arm/boot/dts/rk3229-cpu-opp.dtsi new file mode 100644 index 000000000000..c1c7613bab11 --- /dev/null +++ b/arch/arm/boot/dts/rk3229-cpu-opp.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/ { + compatible = "rockchip,rk3229"; + + /delete-node/ opp-table0; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1400000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000 975000 1400000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000 1000000 1400000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000 1175000 1400000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000 1275000 1400000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1325000 1325000 1400000>; + }; + opp-1392000000 { + opp-hz = /bits/ 64 <1392000000>; + opp-microvolt = <1350000 1350000 1400000>; + }; + opp-1464000000 { + opp-hz = /bits/ 64 <1464000000>; + opp-microvolt = <1400000 1400000 1400000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk322x-box.dtsi b/arch/arm/boot/dts/rk322x-box.dtsi new file mode 100644 index 000000000000..29df40f4fa63 --- /dev/null +++ b/arch/arm/boot/dts/rk322x-box.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include "rk322x-dcdc.dtsi" + +/ { + model = "Rockchip RK322x Box"; + compatible = "rockchip,rk3229"; + + chosen { + bootargs = "earlyprintk=uart8250,mmio32,0x11030000"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power_key: power-key { + label = "GPIO Key Power"; + gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + wakeup-source; + status = "disabled"; + }; + }; + + ir_receiver: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + status = "disabled"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + trust_reserved: trust@68400000 { + reg = <0x68400000 0xe00000>; + no-map; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>; + }; + + timer { + arm,cpu-registers-not-fw-configured; + }; +}; + +&cpu_alert1 { + temperature = <105000>; +}; + +&cpu_crit { + temperature = <115000>; +}; + +&cpu_thermal { + cooling-maps { + /delete-node/ map0; + }; +}; + +&emmc { + cap-mmc-highspeed; + keep-power-in-suspend; + non-removable; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_SRC>; + assigned-clock-rates = <50000000>; + clock_in_out = "output"; + phy-handle = <&phy>; + phy-mode = "rmii"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: phy@0 { + compatible = "ethernet-phy-id1234.d400", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clocks = <&cru SCLK_MAC_PHY>; + phy-is-integrated; + resets = <&cru SRST_MACPHY>; + }; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&hdmi_phy { + status = "okay"; +}; + +&i2s0 { + status = "okay"; +}; + +&pinctrl { + + ir { + ir_int: ir-int { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +&rga { + status = "okay"; +}; + +&sdio { + mmc-pwrseq = <&sdio_pwrseq>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + no-sd; +}; + +&sdmmc { + cap-sd-highspeed; + keep-power-in-suspend; + no-sdio; +}; + +&spdif { + status = "okay"; +}; + +&spdif_out { + status = "okay"; +}; + +&spdif_sound { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart11_xfer &uart11_rts &uart11_cts>; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_ehci { + status = "okay"; +}; + +&usb_host2_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP>; + assigned-clock-parents = <&cru SCLK_HDMI_PHY>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk322x-dcdc.dtsi b/arch/arm/boot/dts/rk322x-dcdc.dtsi new file mode 100644 index 000000000000..6076cb1d0d0b --- /dev/null +++ b/arch/arm/boot/dts/rk322x-dcdc.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk322x.dtsi" + +/ { + + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vccio_1v8: vccio-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vccio_3v3: vccio-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + + vcc_otg: vcc-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vccio_1v8>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_arm: vdd-arm-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <12500>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12500>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + }; + +}; + + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&io_domains { + vccio1-supply = <&vccio_3v3>; + vccio2-supply = <&vccio_1v8>; + vccio4-supply = <&vccio_3v3>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; +}; + +&gpu { + mali-supply = <&vdd_log>; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_pin_pull_down>; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_pin_pull_up>; + status = "okay"; +}; + +&u2phy0 { + u2phy0_host: host-port { + phy-supply = <&vcc_host>; + }; + + u2phy0_otg: otg-port { + phy-supply = <&vcc_otg>; + }; +}; + +&u2phy1 { + u2phy1_host: host-port { + phy-supply = <&vcc_host>; + }; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_otg>; + }; +}; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index eef2c44bdf69..f7a50b903a7d 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -5,6 +5,8 @@ #include #include #include +#include +#include #include / { @@ -14,6 +16,7 @@ interrupt-parent = <&gic>; aliases { + ethernet0 = &gmac; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -73,25 +76,25 @@ opp-408000000 { opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; + opp-microvolt = <950000 950000 1275000>; clock-latency-ns = <40000>; opp-suspend; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; + opp-microvolt = <975000 975000 1275000>; }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; + opp-microvolt = <1000000 1000000 1275000>; }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; + opp-microvolt = <1175000 1175000 1275000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; + opp-microvolt = <1275000 1275000 1275000>; }; }; @@ -121,11 +124,52 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured; @@ -143,17 +187,13 @@ #clock-cells = <0>; }; - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - i2s1: i2s1@100b0000 { compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100b0000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; + #sound-dai-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; dmas = <&pdma 14>, <&pdma 15>; @@ -169,6 +209,7 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + #sound-dai-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; dmas = <&pdma 11>, <&pdma 12>; @@ -186,6 +227,7 @@ dma-names = "tx"; pinctrl-names = "default"; pinctrl-0 = <&spdif_tx>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -213,6 +255,43 @@ status = "disabled"; }; + power: power-controller { + compatible = "rockchip,rk3228-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_gpu@RK3228_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + }; + + pd_vpu@RK3228_PD_VPU { + reg = ; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + pm_qos = <&qos_vpu>; + }; + + pd_rkvdec@RK3228_PD_RKVDEC { + reg = ; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>; + }; + }; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x5c8>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; + u2phy0: usb2-phy@760 { compatible = "rockchip,rk3228-usb2phy"; reg = <0x0760 0x0c>; @@ -263,6 +342,7 @@ status = "disabled"; }; }; + }; uart0: serial@11010000 { @@ -301,7 +381,7 @@ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; + pinctrl-0 = <&uart21_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -460,13 +540,13 @@ <&cru PLL_CPLL>, <&cru ACLK_PERI>, <&cru HCLK_PERI>, <&cru PCLK_PERI>, <&cru ACLK_CPU>, <&cru HCLK_CPU>, - <&cru PCLK_CPU>; + <&cru PCLK_CPU>, <&cru ACLK_VOP>; assigned-clock-rates = - <594000000>, <816000000>, + <1200000000>, <816000000>, <500000000>, <150000000>, <150000000>, <75000000>, <150000000>, <150000000>, - <75000000>; + <75000000>, <400000000>; }; thermal-zones { @@ -511,6 +591,12 @@ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; + + map2 { + trip = <&cpu_alert1>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; }; }; }; @@ -529,8 +615,9 @@ pinctrl-0 = <&otp_gpio>; pinctrl-1 = <&otp_out>; pinctrl-2 = <&otp_gpio>; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <120000>; #thermal-sensor-cells = <0>; - rockchip,hw-tshut-temp = <95000>; status = "disabled"; }; @@ -560,10 +647,33 @@ "ppmmu0", "pp1", "ppmmu1"; + assigned-clocks = <&cru ACLK_GPU>; + assigned-clock-rates = <300000000>; clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; clock-names = "bus", "core"; + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + power-domains = <&power RK3228_PD_GPU>; resets = <&cru SRST_GPU_A>; - status = "disabled"; + }; + + gpu_opp_table: opp-table2 { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1050000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1050000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1150000>; + }; }; vpu_mmu: iommu@20020800 { @@ -573,8 +683,8 @@ interrupt-names = "vpu_mmu"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "iface"; - iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3228_PD_VPU>; + #iommu-cells = <0>; }; vdec_mmu: iommu@20030480 { @@ -584,8 +694,8 @@ interrupt-names = "vdec_mmu"; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; - iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3228_PD_RKVDEC>; + #iommu-cells = <0>; }; vop: vop@20050000 { @@ -639,7 +749,7 @@ interrupt-names = "iep_mmu"; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk", "iface"; - iommu-cells = <0>; + #iommu-cells = <0>; status = "disabled"; }; @@ -659,6 +769,7 @@ phys = <&hdmi_phy>; phy-names = "hdmi"; rockchip,grf = <&grf>; + #sound-dai-cells = <0>; status = "disabled"; ports { @@ -680,9 +791,13 @@ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + bus-width = <4>; fifo-depth = <0x100>; + max-frequency = <150000000>; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_pwr>; + resets = <&cru SRST_SDMMC>; + reset-names = "reset"; status = "disabled"; }; @@ -692,10 +807,14 @@ interrupts = ; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + bus-width = <4>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; + max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; + resets = <&cru SRST_SDIO>; + reset-names = "reset"; status = "disabled"; }; @@ -703,14 +822,13 @@ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30020000 0x4000>; interrupts = ; - clock-frequency = <37500000>; - max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; bus-width = <8>; default-sample-phase = <158>; fifo-depth = <0x100>; + max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; resets = <&cru SRST_EMMC>; @@ -718,6 +836,22 @@ status = "disabled"; }; + nfc: nand-controller@ff4b0000 { + compatible = "rockchip,rk3228_nfc"; + reg = <0x30030000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; + clock-names = "nfc", "ahb"; + assigned-clocks = <&cru SCLK_NANDC>; + assigned-clock-rates = <150000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&flash_cs0 &flash_rdy &flash_ale &flash_cle + &flash_wrn &flash_rdn &flash_bus8>; + status = "disabled"; + + }; + usb_otg: usb@30040000 { compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", "snps,dwc2"; @@ -820,6 +954,26 @@ status = "disabled"; }; + qos_vpu: qos@31040000 { + compatible = "syscon"; + reg = <0x31040000 0x20>; + }; + + qos_gpu: qos@31050000 { + compatible = "syscon"; + reg = <0x31050000 0x20>; + }; + + qos_rkvdec_r: qos@31070000 { + compatible = "syscon"; + reg = <0x31070000 0x20>; + }; + + qos_rkvdec_w: qos@31070080 { + compatible = "syscon"; + reg = <0x31070080 0x20>; + }; + gic: interrupt-controller@32010000 { compatible = "arm,gic-400"; interrupt-controller; @@ -908,6 +1062,11 @@ drive-strength = <12>; }; + pcfg_pull_up_12ma: pcfg-pull-up-12ma { + bias-pull-up; + drive-strength = <12>; + }; + sdmmc { sdmmc_clk: sdmmc-clk { rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; @@ -923,6 +1082,10 @@ <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; sdio { @@ -963,6 +1126,55 @@ }; }; + flash { + + flash_cs0: flash-cs0 { + rockchip,pins = + <2 RK_PA6 1 &pcfg_pull_none>; + }; + + flash_cs1: flash-cs1 { + rockchip,pins = + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + flash_rdy: flash-rdy { + rockchip,pins = + <2 RK_PA4 1 &pcfg_pull_none>; + }; + + flash_ale: flash-ale { + rockchip,pins = + <2 RK_PA0 1 &pcfg_pull_none>; + }; + + flash_cle: flash-cle { + rockchip,pins = + <2 RK_PA1 1 &pcfg_pull_none>; + }; + + flash_wrn: flash-wrn { + rockchip,pins = + <2 RK_PA2 1 &pcfg_pull_none>; + }; + + flash_rdn: flash-rdn { + rockchip,pins = + <2 RK_PA3 1 &pcfg_pull_none>; + }; + + flash_bus8: flash-bus8 { + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, + <1 RK_PD1 1 &pcfg_pull_none>, + <1 RK_PD2 1 &pcfg_pull_none>, + <1 RK_PD3 1 &pcfg_pull_none>, + <1 RK_PD4 1 &pcfg_pull_none>, + <1 RK_PD5 1 &pcfg_pull_none>, + <1 RK_PD6 1 &pcfg_pull_none>, + <1 RK_PD7 1 &pcfg_pull_none>; + }; + }; + gmac { rgmii_pins: rgmii-pins { rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, @@ -1104,12 +1316,20 @@ pwm1_pin: pwm1-pin { rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; }; + + pwm1_pin_pull_down: pwm1-pin-pull-down { + rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_down>; + }; }; pwm2 { pwm2_pin: pwm2-pin { rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; }; + + pwm2_pin_pull_up: pwm2-pin-pull-up { + rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_up>; + }; }; pwm3 { @@ -1164,16 +1384,31 @@ }; }; + uart1-1 { + uart11_xfer: uart11-xfer { + rockchip,pins = <3 RK_PB6 RK_FUNC_1 &pcfg_pull_up>, + <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart11_cts: uart11-cts { + rockchip,pins = <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart11_rts: uart11-rts { + rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart11_rts_gpio: uart11-rts-gpio { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + uart2 { uart2_xfer: uart2-xfer { rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, <1 RK_PC3 2 &pcfg_pull_none>; }; - uart21_xfer: uart21-xfer { - rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, - <1 RK_PB1 2 &pcfg_pull_none>; - }; uart2_cts: uart2-cts { rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; @@ -1183,5 +1418,23 @@ rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; }; }; + + uart2-1 { + uart21_xfer: uart21-xfer { + rockchip,pins = <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>, + <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; }; -- 2.17.1