mirror of
https://github.com/Fishwaldo/build.git
synced 2025-07-22 21:08:49 +00:00
967 lines
22 KiB
Diff
967 lines
22 KiB
Diff
diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
|
|
new file mode 100755
|
|
index 00000000..abd197ed
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/Makefile
|
|
@@ -0,0 +1,28 @@
|
|
+# SPDX-License-Identifier: GPL-2.0
|
|
+dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
|
|
+ rk322x-emmc.dtbo \
|
|
+ rk322x-nand.dtbo \
|
|
+ rk322x-emmc-nand.dtbo \
|
|
+ rk322x-led-conf1.dtbo \
|
|
+ rk322x-led-conf2.dtbo \
|
|
+ rk322x-led-conf3.dtbo \
|
|
+ rk322x-led-conf4.dtbo \
|
|
+ rk322x-cpu-hs.dtbo \
|
|
+ rk322x-cpu-stability.dtbo \
|
|
+ rk322x-bluetooth.dtbo \
|
|
+ rk322x-wlan-ssv6051.dtbo \
|
|
+ rk322x-cpu-hs-lv.dtbo \
|
|
+ rk322x-wlan-esp8089.dtbo \
|
|
+ rk322x-wlan-alt-wiring.dtbo
|
|
+
|
|
+scr-$(CONFIG_ARCH_ROCKCHIP) += \
|
|
+ rk322x-fixup.scr
|
|
+
|
|
+dtbotxt-$(CONFIG_ARCH_ROCKCHIP) += \
|
|
+ README.rk322x-overlays
|
|
+
|
|
+targets += $(dtbo-y) $(scr-y) $(dtbotxt-y)
|
|
+
|
|
+always := $(dtbo-y) $(scr-y) $(dtbotxt-y)
|
|
+clean-files := *.dtbo *.scr
|
|
+
|
|
diff --git a/arch/arm/boot/dts/overlay/README.rk322x-overlays b/arch/arm/boot/dts/overlay/README.rk322x-overlays
|
|
new file mode 100755
|
|
index 00000000..8823a01d
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/README.rk322x-overlays
|
|
@@ -0,0 +1,80 @@
|
|
+This document describes overlays provided in the kernel packages
|
|
+For generic Armbian overlays documentation please see
|
|
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
|
|
+
|
|
+### Platform:
|
|
+
|
|
+rk322x (Rockchip)
|
|
+
|
|
+### Provided overlays:
|
|
+
|
|
+- rk322x-cpu-hs
|
|
+- rk322x-emmc
|
|
+- rk322x-nand
|
|
+- rk322x-emmc-nand
|
|
+- rk322x-led-conf*
|
|
+- rk322x-bluetooth
|
|
+- rk322x-wlan-*
|
|
+- rk322x-cpu-hs-lv
|
|
+- rk322x-wlan-alt-wiring
|
|
+
|
|
+### Overlay details:
|
|
+
|
|
+### rk322x-cpu-hs
|
|
+
|
|
+Activates higher CPU speed (up to 1.4ghz) for rk3228b/rk3229 boxes
|
|
+
|
|
+### emmc
|
|
+
|
|
+Activates onboard emmc device node and deactivates the nand controller.
|
|
+Also sets up the pin controller default pull up/down configuration
|
|
+
|
|
+### nand
|
|
+
|
|
+Activates onboard nand device node and deactivates the emmc controller.
|
|
+Also sets up the pin controller default pull up/down configuration
|
|
+
|
|
+### emmc-nand
|
|
+
|
|
+Activates onboard nand and emmc devices. Usually they are alternative
|
|
+because manufacturers share the same pads so emmc and nand cannot be
|
|
+mixed together. Usually this works because the emmc and nand drivers
|
|
+can automatically guess what's in the pads, but may bring instabilities
|
|
+or misdetections. Also does not set up the pin controller default
|
|
+configuration, which in turn can be detrimental of stability and
|
|
+performance
|
|
+
|
|
+### rk322x-led-conf*
|
|
+
|
|
+Each device tree of this kind provides a different known wiring configuration
|
|
+(ie: gpio and active low/high) of the onboard leds. Each board manufacturer
|
|
+usually choose a different GPIO for the auxiliary led, but the main "working"
|
|
+led is always wired to the same gpio (although it may be active high or low)
|
|
+led-conf1 is commonly found in boards made by Chiptrip manufacturer
|
|
+led-conf2 is found in other boards with R329Q and MXQ_RK3229 marking
|
|
+led-conf3 is found in boards with R28-MXQ marking
|
|
+led-conf4 is found on boards with T066 marking
|
|
+
|
|
+### rk322x-bluetooth
|
|
+
|
|
+Enables the bluetooth power gpio for initialization, wakeup and rfkill
|
|
+functionalities. The overlay also enables uart named serial1 and changes the
|
|
+default pin controller gpio configuration to match those used with uart
|
|
+based bluetooth modules
|
|
+
|
|
+### rk322x-wlan*
|
|
+
|
|
+Enables various wlan rkfill platform data. Actually they are not really
|
|
+needed, but provided for completeness. Wifi should work farily well
|
|
+because power handling is done mmc-pwrseq
|
|
+
|
|
+### rk322x-cpu-hs-lv
|
|
+
|
|
+Enables high cpu speed for high leakage cpus, thus reducing cpu core
|
|
+and logic voltages. May work on non-high leakage cpus, providing significant
|
|
+power consumption saving and less heat production, but may reduce stability.
|
|
+
|
|
+### rk322x-alt-wiring
|
|
+
|
|
+Some boards have different SDIO wiring setup for wifi chips. This overlay
|
|
+enables the different pin controller wiring and power enable
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts b/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts
|
|
new file mode 100755
|
|
index 00000000..5698b14b
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts
|
|
@@ -0,0 +1,39 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/pinctrl/rockchip.h>
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ wireless_bluetooth: wireless-bluetooth {
|
|
+ compatible = "bluetooth-platdata";
|
|
+ uart_rts_gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
|
|
+ BT,power_gpio = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>;
|
|
+ BT,wake_gpio = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>;
|
|
+ BT,wake_host_irq = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
|
|
+ pinctrl-names = "default", "rts_gpio";
|
|
+ pinctrl-0 = <&uart11_rts>;
|
|
+ pinctrl-1 = <&uart11_rts_gpio>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart1>;
|
|
+ __overlay__ {
|
|
+ dma-names = "!tx", "!rx";
|
|
+ dmas = <&pdma 0x04 &pdma 0x05>;
|
|
+ #dma-cells = <0x02>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart11_xfer &uart11_cts>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-cpu-hs-lv.dts b/arch/arm/boot/dts/overlay/rk322x-cpu-hs-lv.dts
|
|
new file mode 100755
|
|
index 00000000..4cde1178
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-cpu-hs-lv.dts
|
|
@@ -0,0 +1,113 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&cpu0_opp_table>;
|
|
+ __overlay__ {
|
|
+
|
|
+ opp-408000000 {
|
|
+ opp-microvolt = <850000 850000 1275000>;
|
|
+ opp-microvolt-L0 = <850000 850000 1275000>;
|
|
+ opp-microvolt-L1 = <850000 850000 1275000>;
|
|
+ };
|
|
+ opp-600000000 {
|
|
+ opp-microvolt = <875000 875000 1275000>;
|
|
+ opp-microvolt-L0 = <875000 875000 1275000>;
|
|
+ opp-microvolt-L1 = <875000 875000 1275000>;
|
|
+ };
|
|
+ opp-816000000 {
|
|
+ opp-microvolt = <900000 900000 1275000>;
|
|
+ opp-microvolt-L0 = <900000 900000 1275000>;
|
|
+ opp-microvolt-L1 = <900000 900000 1275000>;
|
|
+ };
|
|
+ opp-1008000000 {
|
|
+ opp-microvolt = <1075000 1075000 1275000>;
|
|
+ opp-microvolt-L0 = <1075000 1075000 1275000>;
|
|
+ opp-microvolt-L1 = <1025000 1025000 1275000>;
|
|
+ };
|
|
+ opp-1200000000 {
|
|
+ opp-microvolt = <1175000 1175000 1275000>;
|
|
+ opp-microvolt-L0 = <1175000 1175000 1275000>;
|
|
+ opp-microvolt-L1 = <1125000 1125000 1275000>;
|
|
+ };
|
|
+ opp-1296000000 {
|
|
+ opp-hz = /bits/ 64 <1296000000>;
|
|
+ opp-microvolt = <1225000 1225000 1400000>;
|
|
+ opp-microvolt-L0 = <1225000 1225000 1400000>;
|
|
+ opp-microvolt-L1 = <1225000 1225000 1400000>;
|
|
+ };
|
|
+ opp-1392000000 {
|
|
+ opp-hz = /bits/ 64 <1392000000>;
|
|
+ opp-microvolt = <1250000 1250000 1400000>;
|
|
+ opp-microvolt-L0 = <1250000 1250000 1400000>;
|
|
+ opp-microvolt-L1 = <1250000 1250000 1400000>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&vdd_arm>;
|
|
+ __overlay__ {
|
|
+ regulator-min-microvolt = <850000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&gpu_opp_table>;
|
|
+ __overlay__ {
|
|
+ opp-200000000 {
|
|
+ opp-hz = /bits/ 64 <200000000>;
|
|
+ opp-microvolt = <950000>;
|
|
+ opp-microvolt-L0 = <950000>;
|
|
+ opp-microvolt-L1 = <900000>;
|
|
+ };
|
|
+ opp-300000000 {
|
|
+ opp-hz = /bits/ 64 <300000000>;
|
|
+ opp-microvolt = <950000>;
|
|
+ opp-microvolt-L0 = <950000>;
|
|
+ opp-microvolt-L1 = <900000>;
|
|
+ };
|
|
+ opp-500000000 {
|
|
+ opp-hz = /bits/ 64 <500000000>;
|
|
+ opp-microvolt = <1050000>;
|
|
+ opp-microvolt-L0 = <1050000>;
|
|
+ opp-microvolt-L1 = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&vdd_log>;
|
|
+ __overlay__ {
|
|
+ regulator-min-microvolt = <900000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@4 {
|
|
+ target = <&rkvdec_opp_table>;
|
|
+ __overlay__ {
|
|
+ opp-100000000 {
|
|
+ opp-hz = /bits/ 64 <100000000>;
|
|
+ opp-microvolt = <950000>;
|
|
+ opp-microvolt-L0 = <950000>;
|
|
+ opp-microvolt-L1 = <900000>;
|
|
+ };
|
|
+ opp-200000000 {
|
|
+ opp-hz = /bits/ 64 <200000000>;
|
|
+ opp-microvolt = <950000>;
|
|
+ opp-microvolt-L0 = <950000>;
|
|
+ opp-microvolt-L1 = <900000>;
|
|
+ };
|
|
+ opp-500000000 {
|
|
+ opp-hz = /bits/ 64 <500000000>;
|
|
+ opp-microvolt = <950000>;
|
|
+ opp-microvolt-L0 = <950000>;
|
|
+ opp-microvolt-L1 = <900000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts b/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts
|
|
new file mode 100755
|
|
index 00000000..1c2fc79e
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts
|
|
@@ -0,0 +1,28 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&cpu0_opp_table>;
|
|
+ __overlay__ {
|
|
+
|
|
+ opp-1296000000 {
|
|
+ opp-hz = /bits/ 64 <1296000000>;
|
|
+ opp-microvolt = <1325000 1325000 1400000>;
|
|
+ };
|
|
+ opp-1392000000 {
|
|
+ opp-hz = /bits/ 64 <1392000000>;
|
|
+ opp-microvolt = <1350000 1350000 1400000>;
|
|
+ };
|
|
+ /*
|
|
+ opp-1464000000 {
|
|
+ opp-hz = /bits/ 64 <1464000000>;
|
|
+ opp-microvolt = <1400000 1400000 1400000>;
|
|
+ };
|
|
+ */
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-cpu-stability.dts b/arch/arm/boot/dts/overlay/rk322x-cpu-stability.dts
|
|
new file mode 100644
|
|
index 00000000..f434af92
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-cpu-stability.dts
|
|
@@ -0,0 +1,52 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+
|
|
+ /*
|
|
+ Device tree overlay that tries to overcome issues on power regulators (expecially ARM
|
|
+ power regulator) increasing lowest voltage and adding settling time to allow voltage
|
|
+ stabilization
|
|
+ */
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&cpu0_opp_table>;
|
|
+ __overlay__ {
|
|
+
|
|
+ /*
|
|
+ Increase 600 and 800 Mhz operating points voltage to decrease the range
|
|
+ between minimum and maximum voltages
|
|
+ */
|
|
+ opp-600000000 {
|
|
+ opp-hz = /bits/ 64 <600000000>;
|
|
+ opp-microvolt = <1100000>;
|
|
+ };
|
|
+
|
|
+ opp-816000000 {
|
|
+ opp-hz = /bits/ 64 <816000000>;
|
|
+ opp-microvolt = <1100000>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&vdd_arm>;
|
|
+ __overlay__ {
|
|
+
|
|
+ regulator-ramp-delay = <300>; // 30 uV/us, so 0.3v transition settling time is 1ms
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&vdd_log>;
|
|
+ __overlay__ {
|
|
+
|
|
+ regulator-ramp-delay = <600>; // 600 uV/us, so 0,3v transition settling time is 0.5ms
|
|
+
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts
|
|
new file mode 100755
|
|
index 00000000..b451da65
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&emmc>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ mmc-ddr-1_8v;
|
|
+ rockchip,default-sample-phase = <180>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&nandc>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc.dts b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
|
|
new file mode 100755
|
|
index 00000000..f3b262ef
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
|
|
@@ -0,0 +1,24 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&emmc>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr &emmc_rst>;
|
|
+ mmc-ddr-1_8v;
|
|
+ rockchip,default-sample-phase = <180>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&nandc>;
|
|
+ __overlay__ {
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-fixup.scr-cmd b/arch/arm/boot/dts/overlay/rk322x-fixup.scr-cmd
|
|
new file mode 100755
|
|
index 00000000..d4c39e20
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-fixup.scr-cmd
|
|
@@ -0,0 +1,4 @@
|
|
+# overlays fixup script
|
|
+# implements (or rather substitutes) overlay arguments functionality
|
|
+# using u-boot scripting, environment variables and "fdt" command
|
|
+
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts
|
|
new file mode 100755
|
|
index 00000000..f30f21a8
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts
|
|
@@ -0,0 +1,57 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/input/rk-input.h>
|
|
+#include <dt-bindings/pinctrl/rockchip.h>
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/gpio-leds";
|
|
+ __overlay__ {
|
|
+
|
|
+ working {
|
|
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
|
+ linux,default-trigger = "none";
|
|
+ };
|
|
+
|
|
+ auxiliary {
|
|
+ gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
|
|
+ label = "auxiliary";
|
|
+ linux,default-trigger = "mmc2";
|
|
+ default-state = "off";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&gpio_led_aux>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/pinctrl/gpio";
|
|
+ __overlay__ {
|
|
+
|
|
+ gpio_led_aux: gpio-led-aux {
|
|
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&gpio_keys>;
|
|
+ __overlay__ {
|
|
+
|
|
+ reset {
|
|
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
|
|
+ label = "reset";
|
|
+ linux,code = <KEY_RESTART>;
|
|
+ debounce-interval = <200>;
|
|
+ wakeup-source;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf2.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf2.dts
|
|
new file mode 100755
|
|
index 00000000..153f7156
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-led-conf2.dts
|
|
@@ -0,0 +1,57 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/input/input.h>
|
|
+#include <dt-bindings/pinctrl/rockchip.h>
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/gpio-leds";
|
|
+ __overlay__ {
|
|
+
|
|
+ working {
|
|
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
|
|
+ linux,default-trigger = "none";
|
|
+ };
|
|
+
|
|
+ auxiliary {
|
|
+ gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
|
|
+ label = "auxiliary";
|
|
+ linux,default-trigger = "mmc2";
|
|
+ default-state = "off";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&gpio_led_aux>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/pinctrl/gpio";
|
|
+ __overlay__ {
|
|
+
|
|
+ gpio_led_aux: gpio-led-aux {
|
|
+ rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&gpio_keys>;
|
|
+ __overlay__ {
|
|
+
|
|
+ reset {
|
|
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
|
|
+ label = "reset";
|
|
+ linux,code = <KEY_RESTART>;
|
|
+ debounce-interval = <200>;
|
|
+ wakeup-source;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf3.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf3.dts
|
|
new file mode 100755
|
|
index 00000000..39f4547e
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-led-conf3.dts
|
|
@@ -0,0 +1,57 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/input/rk-input.h>
|
|
+#include <dt-bindings/pinctrl/rockchip.h>
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/gpio-leds";
|
|
+ __overlay__ {
|
|
+
|
|
+ working {
|
|
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
|
+ linux,default-trigger = "none";
|
|
+ };
|
|
+
|
|
+ auxiliary {
|
|
+ gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
|
|
+ label = "auxiliary";
|
|
+ linux,default-trigger = "mmc2";
|
|
+ default-state = "off";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&gpio_led_aux>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/pinctrl/gpio";
|
|
+ __overlay__ {
|
|
+
|
|
+ gpio_led_aux: gpio-led-aux {
|
|
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&gpio_keys>;
|
|
+ __overlay__ {
|
|
+
|
|
+ reset {
|
|
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
|
|
+ label = "reset";
|
|
+ linux,code = <KEY_RESTART>;
|
|
+ debounce-interval = <200>;
|
|
+ wakeup-source;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf4.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf4.dts
|
|
new file mode 100644
|
|
index 00000000..e9cda296
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-led-conf4.dts
|
|
@@ -0,0 +1,81 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/input/rk-input.h>
|
|
+#include <dt-bindings/pinctrl/rockchip.h>
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/gpio-leds";
|
|
+ __overlay__ {
|
|
+
|
|
+ working {
|
|
+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
|
|
+ linux,default-trigger = "none";
|
|
+ };
|
|
+
|
|
+ auxiliary {
|
|
+ gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
|
|
+ label = "auxiliary";
|
|
+ linux,default-trigger = "mmc2";
|
|
+ default-state = "off";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&gpio_led_aux>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/pinctrl/gpio";
|
|
+ __overlay__ {
|
|
+
|
|
+ gpio_led_working: gpio-led-working {
|
|
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ gpio_led_aux: gpio-led-aux {
|
|
+ rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&gpio_keys>;
|
|
+ __overlay__ {
|
|
+
|
|
+ reset {
|
|
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
|
|
+ label = "reset";
|
|
+ linux,code = <KEY_RESTART>;
|
|
+ debounce-interval = <200>;
|
|
+ wakeup-source;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&sdio_pwrseq>;
|
|
+ __overlay__ {
|
|
+
|
|
+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; /* GPIO2_D3 */
|
|
+
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
+ fragment@4 {
|
|
+ target = <&wifi_enable_h>;
|
|
+ __overlay__ {
|
|
+
|
|
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts
|
|
new file mode 100644
|
|
index 00000000..e9cda296
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts
|
|
@@ -0,0 +1,81 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/input/rk-input.h>
|
|
+#include <dt-bindings/pinctrl/rockchip.h>
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/gpio-leds";
|
|
+ __overlay__ {
|
|
+
|
|
+ working {
|
|
+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
|
|
+ linux,default-trigger = "none";
|
|
+ };
|
|
+
|
|
+ auxiliary {
|
|
+ gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
|
|
+ label = "auxiliary";
|
|
+ linux,default-trigger = "mmc2";
|
|
+ default-state = "off";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&gpio_led_aux>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/pinctrl/gpio";
|
|
+ __overlay__ {
|
|
+
|
|
+ gpio_led_working: gpio-led-working {
|
|
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ gpio_led_aux: gpio-led-aux {
|
|
+ rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&gpio_keys>;
|
|
+ __overlay__ {
|
|
+
|
|
+ reset {
|
|
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
|
|
+ label = "reset";
|
|
+ linux,code = <KEY_RESTART>;
|
|
+ debounce-interval = <200>;
|
|
+ wakeup-source;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&sdio_pwrseq>;
|
|
+ __overlay__ {
|
|
+
|
|
+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; /* GPIO2_D3 */
|
|
+
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
+ fragment@4 {
|
|
+ target = <&wifi_enable_h>;
|
|
+ __overlay__ {
|
|
+
|
|
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-nand.dts b/arch/arm/boot/dts/overlay/rk322x-nand.dts
|
|
new file mode 100755
|
|
index 00000000..5675f5b3
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-nand.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&nandc>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-0 = <&flash_cs0 &flash_cs1 &flash_cs2 &flash_cs3 &flash_rdy &flash_ale &flash_cle &flash_wrn &flash_bus8 &flash_dqs &flash_wp>;
|
|
+ pinctrl-names = "default";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&emmc>;
|
|
+ __overlay__ {
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-wlan-alt-wiring.dts b/arch/arm/boot/dts/overlay/rk322x-wlan-alt-wiring.dts
|
|
new file mode 100644
|
|
index 00000000..f6a1a720
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-wlan-alt-wiring.dts
|
|
@@ -0,0 +1,66 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/pinctrl/rockchip.h>
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pinctrl>;
|
|
+ __overlay__ {
|
|
+
|
|
+ pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
|
|
+ bias-disable;
|
|
+ drive-strength = <0x04>;
|
|
+ };
|
|
+
|
|
+ pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
|
|
+ bias-pull-up;
|
|
+ drive-strength = <0x04>;
|
|
+ };
|
|
+
|
|
+ sdio {
|
|
+ sdio_clk: sdio-clk {
|
|
+ rockchip,pins = <1 0 1 &pcfg_pull_none_drv_4ma>;
|
|
+ };
|
|
+
|
|
+ sdio_cmd: sdio-cmd {
|
|
+ rockchip,pins = <0 3 2 &pcfg_pull_up_drv_4ma>;
|
|
+ };
|
|
+
|
|
+ sdio_bus4: sdio-bus4 {
|
|
+ rockchip,pins = <1 1 1 &pcfg_pull_up_drv_4ma>,
|
|
+ <1 2 1 &pcfg_pull_up_drv_4ma>,
|
|
+ <1 4 1 &pcfg_pull_up_drv_4ma>,
|
|
+ <1 5 1 &pcfg_pull_up_drv_4ma>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&sdio_pwrseq>;
|
|
+ __overlay__ {
|
|
+ reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&wifi_enable_h>;
|
|
+ __overlay__ {
|
|
+ rockchip,pins = <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&sdio>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdio_clk>, <&sdio_cmd>, <&sdio_bus4>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-wlan-esp8089.dts b/arch/arm/boot/dts/overlay/rk322x-wlan-esp8089.dts
|
|
new file mode 100755
|
|
index 00000000..75a2ac8b
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-wlan-esp8089.dts
|
|
@@ -0,0 +1,24 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/pinctrl/rockchip.h>
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ wireless_wlan: wireless-wlan {
|
|
+ compatible = "wlan-platdata";
|
|
+ rockchip,grf = <&grf>;
|
|
+ wifi_chip_type = "esp8089";
|
|
+ sdio_vref = <1800>;
|
|
+ //WIFI,poweren_gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
|
+ WIFI,host_wake_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/rk322x-wlan-ssv6051.dts b/arch/arm/boot/dts/overlay/rk322x-wlan-ssv6051.dts
|
|
new file mode 100755
|
|
index 00000000..47644f6e
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/rk322x-wlan-ssv6051.dts
|
|
@@ -0,0 +1,24 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/pinctrl/rockchip.h>
|
|
+
|
|
+/ {
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ wireless_wlan: wireless-wlan {
|
|
+ compatible = "wlan-platdata";
|
|
+ rockchip,grf = <&grf>;
|
|
+ wifi_chip_type = "ssv6051";
|
|
+ sdio_vref = <1800>;
|
|
+ //WIFI,poweren_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
|
|
+ WIFI,host_wake_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|