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cc7ab6a6b1
* Attach Meson64 to mainline with a bunch of patches. Tested, but need further work. * Enable DVFS on N2 which sometimes works, sometime doesn't, cleanup * Enable beta targets for Meson64 kernel family * Bump with version
487 lines
14 KiB
Diff
487 lines
14 KiB
Diff
From d033c693819d133a6d04b9916b26475795f61a5a Mon Sep 17 00:00:00 2001
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From: Jerome Brunet <jbrunet@baylibre.com>
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Date: Tue, 22 Oct 2019 17:54:41 +0200
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Subject: [PATCH 52/94] WIP: ASoC: meson: aiu: add i2s encoder support
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Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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---
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sound/soc/meson/Kconfig | 8 +
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sound/soc/meson/Makefile | 2 +
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sound/soc/meson/aiu-i2s-encode.c | 426 +++++++++++++++++++++++++++++++++++++++
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3 files changed, 436 insertions(+)
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create mode 100644 sound/soc/meson/aiu-i2s-encode.c
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diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kconfig
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index 47a7cae..562d960 100644
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--- a/sound/soc/meson/Kconfig
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+++ b/sound/soc/meson/Kconfig
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@@ -26,6 +26,14 @@ config SND_MESON_AIU_SPDIF_FIFO
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help
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Select Y or M to add support for spdif FIFO of the GXL family
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+config SND_MESON_AIU_I2S_ENCODER
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+ tristate "Amlogic AIU I2S Encoder"
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+ imply SND_MESON_AIU_I2S_FIFO
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+ imply SND_MESON_AIU_BUS
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+ select MFD_SYSCON
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+ help
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+ Select Y or M to add support for i2s Encoder of the GXL family
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+
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config SND_MESON_AXG_FIFO
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tristate
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select REGMAP_MMIO
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diff --git a/sound/soc/meson/Makefile b/sound/soc/meson/Makefile
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index 45637ce..cfbe404 100644
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--- a/sound/soc/meson/Makefile
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+++ b/sound/soc/meson/Makefile
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@@ -4,6 +4,7 @@ snd-soc-meson-aiu-bus-objs := aiu-bus.o
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snd-soc-meson-aiu-fifo-objs := aiu-fifo.o
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snd-soc-meson-aiu-i2s-fifo-objs := aiu-i2s-fifo.o
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snd-soc-meson-aiu-spdif-fifo-objs := aiu-spdif-fifo.o
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+snd-soc-meson-aiu-i2s-encode-objs := aiu-i2s-encode.o
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snd-soc-meson-axg-fifo-objs := axg-fifo.o
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snd-soc-meson-axg-frddr-objs := axg-frddr.o
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snd-soc-meson-axg-toddr-objs := axg-toddr.o
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@@ -24,6 +25,7 @@ obj-$(CONFIG_SND_MESON_AIU_BUS) += snd-soc-meson-aiu-bus.o
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obj-$(CONFIG_SND_MESON_AIU_FIFO) += snd-soc-meson-aiu-fifo.o
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obj-$(CONFIG_SND_MESON_AIU_I2S_FIFO) += snd-soc-meson-aiu-i2s-fifo.o
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obj-$(CONFIG_SND_MESON_AIU_SPDIF_FIFO) += snd-soc-meson-aiu-spdif-fifo.o
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+obj-$(CONFIG_SND_MESON_AIU_I2S_ENCODER) += snd-soc-meson-aiu-i2s-encode.o
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obj-$(CONFIG_SND_MESON_AXG_FIFO) += snd-soc-meson-axg-fifo.o
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obj-$(CONFIG_SND_MESON_AXG_FRDDR) += snd-soc-meson-axg-frddr.o
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obj-$(CONFIG_SND_MESON_AXG_TODDR) += snd-soc-meson-axg-toddr.o
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diff --git a/sound/soc/meson/aiu-i2s-encode.c b/sound/soc/meson/aiu-i2s-encode.c
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new file mode 100644
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index 0000000..4a77fba
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--- /dev/null
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+++ b/sound/soc/meson/aiu-i2s-encode.c
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@@ -0,0 +1,426 @@
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+// SPDX-License-Identifier: GPL-2.0
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+//
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+// Copyright (c) 2018 BayLibre, SAS.
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+// Author: Jerome Brunet <jbrunet@baylibre.com>
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+
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+#include <linux/bitfield.h>
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+#include <linux/clk.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/module.h>
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+#include <linux/of_platform.h>
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+#include <sound/pcm_params.h>
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+#include <sound/soc.h>
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+#include <sound/soc-dai.h>
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+
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+#define AIU_CLK_CTRL 0x058
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+#define AIU_CLK_CTRL_I2S_DIV_EN BIT(0)
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+#define AIU_CLK_CTRL_I2S_DIV GENMASK(3, 2)
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+#define AIU_CLK_CTRL_AOCLK_INVERT BIT(6)
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+#define AIU_CLK_CTRL_LRCLK_INVERT BIT(7)
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+#define AIU_CLK_CTRL_LRCLK_SKEW GENMASK(9, 8)
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+#define AIU_CLK_CTRL_MORE 0x064
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+#define AIU_CLK_CTRL_MORE_HDMI_AMCLK BIT(6)
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+#define AIU_CLK_CTRL_MORE_I2S_DIV GENMASK(5, 0)
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+#define AIU_I2S_SOURCE_DESC 0x034
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+#define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
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+#define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
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+#define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
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+#define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11)
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+#define AIU_I2S_DAC_CFG 0x040
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+#define AIU_I2S_DAC_CFG_PAYLOAD_SIZE GENMASK(1, 0)
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+#define CFG_AOCLK_64 3
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+#define AIU_CODEC_DAC_LRCLK_CTRL 0x0a0
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+#define AIU_CODEC_DAC_LRCLK_CTRL_DIV GENMASK(11, 0)
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+#define AIU_I2S_MISC 0x048
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+#define AIU_I2S_MISC_HOLD_EN BIT(2)
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+
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+struct aiu_i2s_encode {
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+ struct clk *aoclk;
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+ struct clk *mclk;
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+ struct clk *pclk;
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+};
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+
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+static void aiu_i2s_encode_divider_enable(struct snd_soc_component *component,
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+ bool enable)
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+{
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+ snd_soc_component_update_bits(component, AIU_CLK_CTRL,
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+ AIU_CLK_CTRL_I2S_DIV_EN,
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+ enable ? AIU_CLK_CTRL_I2S_DIV_EN : 0);
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+}
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+
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+static void aiu_i2s_encode_hold(struct snd_soc_component *component,
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+ bool enable)
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+{
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+ snd_soc_component_update_bits(component, AIU_I2S_MISC,
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+ AIU_I2S_MISC_HOLD_EN,
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+ enable ? AIU_I2S_MISC_HOLD_EN : 0);
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+}
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+
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+static int aiu_i2s_encode_trigger(struct snd_pcm_substream *substream, int cmd,
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+ struct snd_soc_dai *dai)
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+{
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+ struct snd_soc_component *component = dai->component;
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+
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+ switch (cmd) {
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+ case SNDRV_PCM_TRIGGER_START:
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+ case SNDRV_PCM_TRIGGER_RESUME:
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+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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+ aiu_i2s_encode_hold(component, false);
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+ return 0;
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+
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+ case SNDRV_PCM_TRIGGER_STOP:
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+ case SNDRV_PCM_TRIGGER_SUSPEND:
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+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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+ aiu_i2s_encode_hold(component, true);
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+ return 0;
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+
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+ default:
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+ return -EINVAL;
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+ }
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+}
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+
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+/* Does this register/setting belong in the FIFO driver */
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+static int aiu_i2s_encode_setup_desc(struct snd_soc_component *component,
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+ struct snd_pcm_hw_params *params)
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+{
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+ /* Always operate in split (classic interleaved) mode */
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+ unsigned int desc = AIU_I2S_SOURCE_DESC_MODE_SPLIT;
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+
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+ /*
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+ * TODO: The encoder probably supports S24_3LE (24 bits
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+ * physical width) formats but it is not clear how to support
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+ * this in the FIFO driver so we can't test it yet
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+ */
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+ switch (params_physical_width(params)) {
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+ case 16: /* Nothing to do */
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+ break;
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+
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+ case 32:
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+ desc |= (AIU_I2S_SOURCE_DESC_MODE_24BIT |
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+ AIU_I2S_SOURCE_DESC_MODE_32BIT);
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+ break;
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+
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ switch (params_channels(params)) {
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+ case 2: /* Nothing to do */
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+ break;
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+ case 8:
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+ desc |= AIU_I2S_SOURCE_DESC_MODE_8CH;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ snd_soc_component_update_bits(component, AIU_I2S_SOURCE_DESC,
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+ AIU_I2S_SOURCE_DESC_MODE_8CH |
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+ AIU_I2S_SOURCE_DESC_MODE_24BIT |
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+ AIU_I2S_SOURCE_DESC_MODE_32BIT |
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+ AIU_I2S_SOURCE_DESC_MODE_SPLIT,
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+ desc);
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+
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+ return 0;
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+}
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+
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+static int aiu_i2s_encode_set_clocks(struct snd_soc_component *component,
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+ struct snd_pcm_hw_params *params)
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+{
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+ struct aiu_i2s_encode *encoder = snd_soc_component_get_drvdata(component);
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+ unsigned int srate = params_rate(params);
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+ unsigned int fs;
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+
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+ /* Get the oversampling factor */
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+ fs = DIV_ROUND_CLOSEST(clk_get_rate(encoder->mclk), srate);
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+
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+ /* TODO: add support for 24 and 16 bits slot width */
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+ if (fs % 64)
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+ return -EINVAL;
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+
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+ /* Set the divider between bclk and lrclk to 64 */
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+ snd_soc_component_update_bits(component, AIU_I2S_DAC_CFG,
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+ AIU_I2S_DAC_CFG_PAYLOAD_SIZE,
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+ FIELD_PREP(AIU_I2S_DAC_CFG_PAYLOAD_SIZE,
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+ CFG_AOCLK_64));
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+
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+ snd_soc_component_update_bits(component, AIU_CODEC_DAC_LRCLK_CTRL,
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+ AIU_CODEC_DAC_LRCLK_CTRL_DIV,
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+ FIELD_PREP(AIU_CODEC_DAC_LRCLK_CTRL_DIV,
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+ 64 - 1));
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+
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+ /* Use CLK_MORE for mclk to bclk divider */
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+ snd_soc_component_update_bits(component, AIU_CLK_CTRL,
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+ AIU_CLK_CTRL_I2S_DIV, 0);
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+
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+ snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
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+ AIU_CLK_CTRL_MORE_I2S_DIV,
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+ FIELD_PREP(AIU_CLK_CTRL_MORE_I2S_DIV,
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+ (fs / 64) - 1));
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+
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+ /* Make sure amclk is used for HDMI i2s as well */
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+ snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
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+ AIU_CLK_CTRL_MORE_HDMI_AMCLK,
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+ AIU_CLK_CTRL_MORE_HDMI_AMCLK);
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+
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+ /* REMOVE ME: HARD CODED TEST */
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+ /* Set HDMI path */
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+ snd_soc_component_write(component, 0xa8, 0x22);
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+
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+ /* Internal DAC Path */
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+ snd_soc_component_write(component, 0xb0, 0x8058);
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+
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+ return 0;
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+}
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+
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+static int aiu_i2s_encode_hw_params(struct snd_pcm_substream *substream,
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+ struct snd_pcm_hw_params *params,
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+ struct snd_soc_dai *dai)
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+{
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+ struct snd_soc_component *component = dai->component;
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+ int ret;
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+
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+ /* Disable the clock while changing the settings */
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+ aiu_i2s_encode_divider_enable(component, false);
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+
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+ ret = aiu_i2s_encode_setup_desc(component, params);
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+ if (ret) {
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+ dev_err(dai->dev, "setting i2s desc failed\n");
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+ return ret;
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+ }
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+
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+ ret = aiu_i2s_encode_set_clocks(component, params);
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+ if (ret) {
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+ dev_err(dai->dev, "setting i2s clocks failed\n");
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+ return ret;
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+ }
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+
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+ aiu_i2s_encode_divider_enable(component, true);
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+
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+ return 0;
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+}
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+
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+static int aiu_i2s_encode_hw_free(struct snd_pcm_substream *substream,
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+ struct snd_soc_dai *dai)
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+{
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+ struct snd_soc_component *component = dai->component;
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+
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+ aiu_i2s_encode_divider_enable(component, false);
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+
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+ return 0;
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+}
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+
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+static int aiu_i2s_encode_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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+{
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+ struct snd_soc_component *component = dai->component;
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+ unsigned int inv = fmt & SND_SOC_DAIFMT_INV_MASK;
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+ unsigned int val = 0;
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+ unsigned int skew;
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+
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+ /* Only CPU Master / Codec Slave supported ATM */
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+ if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
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+ return -EINVAL;
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+
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+ if ((inv == SND_SOC_DAIFMT_NB_IF) || (inv == SND_SOC_DAIFMT_IB_IF))
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+ val |= AIU_CLK_CTRL_LRCLK_INVERT;
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+
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+ if ((inv == SND_SOC_DAIFMT_IB_NF) || (inv == SND_SOC_DAIFMT_IB_IF))
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+ val |= AIU_CLK_CTRL_AOCLK_INVERT;
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+
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+ /* Signal skew */
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+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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+ case SND_SOC_DAIFMT_I2S:
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+ /* Invert sample clock for i2s */
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+ val ^= AIU_CLK_CTRL_LRCLK_INVERT;
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+ skew = 1;
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+ break;
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+ case SND_SOC_DAIFMT_LEFT_J:
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+ skew = 0;
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+ break;
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+ case SND_SOC_DAIFMT_RIGHT_J:
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+ skew = 2;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ val |= FIELD_PREP(AIU_CLK_CTRL_LRCLK_SKEW, skew);
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+ snd_soc_component_update_bits(component, AIU_CLK_CTRL,
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+ AIU_CLK_CTRL_LRCLK_INVERT |
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+ AIU_CLK_CTRL_AOCLK_INVERT |
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+ AIU_CLK_CTRL_LRCLK_SKEW,
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+ val);
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+
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+ return 0;
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+}
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+
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+static int aiu_i2s_encode_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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+ unsigned int freq, int dir)
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+{
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+ struct aiu_i2s_encode *encoder = snd_soc_dai_get_drvdata(dai);
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+ int ret;
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+
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+ if (WARN_ON(clk_id != 0))
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+ return -EINVAL;
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+
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+ if (dir == SND_SOC_CLOCK_IN)
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+ return 0;
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+
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+ ret = clk_set_rate(encoder->mclk, freq);
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+ if (ret)
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+ dev_err(dai->dev, "Failed to set sysclk to %uHz", freq);
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+
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+ return ret;
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+}
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+
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+static const unsigned int hw_channels[] = {2, 8};
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+static const struct snd_pcm_hw_constraint_list hw_channel_constraints = {
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+ .list = hw_channels,
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+ .count = ARRAY_SIZE(hw_channels),
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+ .mask = 0,
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+};
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+
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+static int aiu_i2s_encode_startup(struct snd_pcm_substream *substream,
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+ struct snd_soc_dai *dai)
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+{
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+ struct aiu_i2s_encode *encoder = snd_soc_dai_get_drvdata(dai);
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+ int ret;
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+
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+ /* Make sure the encoder gets either 2 or 8 channels */
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+ ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
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+ SNDRV_PCM_HW_PARAM_CHANNELS,
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+ &hw_channel_constraints);
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+ if (ret) {
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+ dev_err(dai->dev, "adding channels constraints failed\n");
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+ return ret;
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+ }
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+
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+ ret = clk_prepare_enable(encoder->pclk);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_prepare_enable(encoder->mclk);
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+ if (ret)
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+ goto err_mclk;
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+
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+ ret = clk_prepare_enable(encoder->aoclk);
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+ if (ret)
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+ goto err_aoclk;
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+
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+ return 0;
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+
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+err_aoclk:
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+ clk_disable_unprepare(encoder->mclk);
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+err_mclk:
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+ clk_disable_unprepare(encoder->pclk);
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+ return ret;
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+}
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+
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+static void aiu_i2s_encode_shutdown(struct snd_pcm_substream *substream,
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+ struct snd_soc_dai *dai)
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+{
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+ struct aiu_i2s_encode *encoder = snd_soc_dai_get_drvdata(dai);
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+
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+ clk_disable_unprepare(encoder->aoclk);
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+ clk_disable_unprepare(encoder->mclk);
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+ clk_disable_unprepare(encoder->pclk);
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+}
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+
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+static const struct snd_soc_dai_ops aiu_i2s_encode_dai_ops = {
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+ .trigger = aiu_i2s_encode_trigger,
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+ .hw_params = aiu_i2s_encode_hw_params,
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+ .hw_free = aiu_i2s_encode_hw_free,
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+ .set_fmt = aiu_i2s_encode_set_fmt,
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+ .set_sysclk = aiu_i2s_encode_set_sysclk,
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+ .startup = aiu_i2s_encode_startup,
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+ .shutdown = aiu_i2s_encode_shutdown,
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+};
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+
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+static struct snd_soc_dai_driver aiu_i2s_encode_dai_drv = {
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+ .playback = {
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+ .stream_name = "Playback",
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+ .channels_min = 2,
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+ .channels_max = 8,
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+ .rates = SNDRV_PCM_RATE_8000_192000,
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+ .formats = (SNDRV_PCM_FMTBIT_S16_LE |
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+ SNDRV_PCM_FMTBIT_S20_LE |
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+ SNDRV_PCM_FMTBIT_S24_LE |
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+ SNDRV_PCM_FMTBIT_S32_LE)
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+ },
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+ .ops = &aiu_i2s_encode_dai_ops,
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+};
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+
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+int aiu_i2s_encode_component_probe(struct snd_soc_component *component)
|
|
+{
|
|
+ struct device *dev = component->dev;
|
|
+ struct regmap *map;
|
|
+
|
|
+ map = syscon_node_to_regmap(dev->parent->of_node);
|
|
+ if (IS_ERR(map)) {
|
|
+ dev_err(dev, "Could not get regmap\n");
|
|
+ return PTR_ERR(map);
|
|
+ }
|
|
+
|
|
+ snd_soc_component_init_regmap(component, map);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct snd_soc_component_driver aiu_i2s_encode_component = {
|
|
+ .probe = aiu_i2s_encode_component_probe,
|
|
+};
|
|
+
|
|
+static int aiu_i2s_encode_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct device *dev = &pdev->dev;
|
|
+ struct aiu_i2s_encode *encoder;
|
|
+
|
|
+ encoder = devm_kzalloc(dev, sizeof(*encoder), GFP_KERNEL);
|
|
+ if (!encoder)
|
|
+ return -ENOMEM;
|
|
+ platform_set_drvdata(pdev, encoder);
|
|
+
|
|
+ encoder->pclk = devm_clk_get(dev, "pclk");
|
|
+ if (IS_ERR(encoder->pclk)) {
|
|
+ if (PTR_ERR(encoder->pclk) != -EPROBE_DEFER)
|
|
+ dev_err(dev,
|
|
+ "Can't get the peripheral clock\n");
|
|
+ return PTR_ERR(encoder->pclk);
|
|
+ }
|
|
+
|
|
+ encoder->aoclk = devm_clk_get(dev, "aoclk");
|
|
+ if (IS_ERR(encoder->aoclk)) {
|
|
+ if (PTR_ERR(encoder->aoclk) != -EPROBE_DEFER)
|
|
+ dev_err(dev, "Can't get the ao clock\n");
|
|
+ return PTR_ERR(encoder->aoclk);
|
|
+ }
|
|
+
|
|
+ encoder->mclk = devm_clk_get(dev, "mclk");
|
|
+ if (IS_ERR(encoder->mclk)) {
|
|
+ if (PTR_ERR(encoder->mclk) != -EPROBE_DEFER)
|
|
+ dev_err(dev, "Can't get the i2s m\n");
|
|
+ return PTR_ERR(encoder->mclk);
|
|
+ }
|
|
+
|
|
+ return devm_snd_soc_register_component(dev, &aiu_i2s_encode_component,
|
|
+ &aiu_i2s_encode_dai_drv, 1);
|
|
+}
|
|
+
|
|
+static const struct of_device_id aiu_i2s_encode_of_match[] = {
|
|
+ { .compatible = "amlogic,aiu-i2s-encode", },
|
|
+ {}
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, aiu_i2s_encode_of_match);
|
|
+
|
|
+static struct platform_driver aiu_i2s_encode_pdrv = {
|
|
+ .probe = aiu_i2s_encode_probe,
|
|
+ .driver = {
|
|
+ .name = "meson-aiu-i2s-encode",
|
|
+ .of_match_table = aiu_i2s_encode_of_match,
|
|
+ },
|
|
+};
|
|
+module_platform_driver(aiu_i2s_encode_pdrv);
|
|
+
|
|
+MODULE_DESCRIPTION("Meson AIU I2S Encode Driver");
|
|
+MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
|
|
+MODULE_LICENSE("GPL v2");
|
|
--
|
|
2.7.1
|
|
|