mirror of
https://github.com/Fishwaldo/build.git
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cc7ab6a6b1
* Attach Meson64 to mainline with a bunch of patches. Tested, but need further work. * Enable DVFS on N2 which sometimes works, sometime doesn't, cleanup * Enable beta targets for Meson64 kernel family * Bump with version
308 lines
9.6 KiB
Diff
308 lines
9.6 KiB
Diff
The clock controller driver has provided the XTAL clock so far. This
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does not match how the hardware actually works because the XTAL clock is
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an actual crystal which is mounted on the PCB.
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Add the "xtal" clock to meson.dtsi and replace all references to the
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clock controller's CLKID_XTAL with the new xtal clock node.
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Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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---
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arch/arm/boot/dts/meson.dtsi | 7 +++++++
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arch/arm/boot/dts/meson6.dtsi | 7 -------
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arch/arm/boot/dts/meson8.dtsi | 15 ++++++++-------
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arch/arm/boot/dts/meson8b-ec100.dts | 2 +-
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arch/arm/boot/dts/meson8b-mxq.dts | 2 +-
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arch/arm/boot/dts/meson8b-odroidc1.dts | 2 +-
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arch/arm/boot/dts/meson8b.dtsi | 15 ++++++++-------
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7 files changed, 26 insertions(+), 24 deletions(-)
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diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
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index c4447f6c8b2c..5d198309058a 100644
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--- a/arch/arm/boot/dts/meson.dtsi
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+++ b/arch/arm/boot/dts/meson.dtsi
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@@ -282,4 +282,11 @@ efuse: nvmem@0 {
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};
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};
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};
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+
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+ xtal: xtal-clk {
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+ compatible = "fixed-clock";
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+ clock-frequency = <24000000>;
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+ clock-output-names = "xtal";
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+ #clock-cells = <0>;
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+ };
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}; /* end of / */
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diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
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index 2d31b7ce3f8c..4716030a48d0 100644
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--- a/arch/arm/boot/dts/meson6.dtsi
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+++ b/arch/arm/boot/dts/meson6.dtsi
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@@ -36,13 +36,6 @@ apb2: bus@d0000000 {
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ranges = <0x0 0xd0000000 0x40000>;
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};
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- xtal: xtal-clk {
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- compatible = "fixed-clock";
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- clock-frequency = <24000000>;
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- clock-output-names = "xtal";
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- #clock-cells = <0>;
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- };
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-
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clk81: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
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index 3c534cd50ee3..add6d7991fdf 100644
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--- a/arch/arm/boot/dts/meson8.dtsi
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+++ b/arch/arm/boot/dts/meson8.dtsi
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@@ -455,6 +455,8 @@ &gpio_intc {
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&hhi {
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clkc: clock-controller {
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compatible = "amlogic,meson8-clkc";
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+ clocks = <&xtal>;
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+ clock-names = "xtal";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@@ -529,8 +531,7 @@ &rtc {
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&saradc {
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compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
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- clocks = <&clkc CLKID_XTAL>,
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- <&clkc CLKID_SAR_ADC>;
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+ clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
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clock-names = "clkin", "core";
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amlogic,hhi-sysctrl = <&hhi>;
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nvmem-cells = <&temperature_calib>;
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@@ -548,31 +549,31 @@ &spifc {
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};
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&timer_abcde {
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- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
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+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
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clock-names = "xtal", "pclk";
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};
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&uart_AO {
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compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
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- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
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+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_A {
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compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
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- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
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+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_B {
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compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
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- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
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+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_C {
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compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
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- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
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+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
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clock-names = "baud", "xtal", "pclk";
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};
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diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
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index bed1dfef1985..163a200d5a7b 100644
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--- a/arch/arm/boot/dts/meson8b-ec100.dts
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+++ b/arch/arm/boot/dts/meson8b-ec100.dts
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@@ -377,7 +377,7 @@ &pwm_cd {
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status = "okay";
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pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
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pinctrl-names = "default";
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- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
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+ clocks = <&xtal>, <&xtal>;
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clock-names = "clkin0", "clkin1";
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};
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diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts
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index 6e39ad52e42d..33037ef62d0a 100644
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--- a/arch/arm/boot/dts/meson8b-mxq.dts
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+++ b/arch/arm/boot/dts/meson8b-mxq.dts
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@@ -165,7 +165,7 @@ &pwm_cd {
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status = "okay";
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pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
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pinctrl-names = "default";
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- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
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+ clocks = <&xtal>, <&xtal>;
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clock-names = "clkin0", "clkin1";
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};
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diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
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index a24eccc354b9..a2a47804fc4a 100644
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--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
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+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
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@@ -340,7 +340,7 @@ &pwm_cd {
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status = "okay";
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pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
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pinctrl-names = "default";
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- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
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+ clocks = <&xtal>, <&xtal>;
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clock-names = "clkin0", "clkin1";
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};
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diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
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index 099bf8e711c9..1934666ff60f 100644
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--- a/arch/arm/boot/dts/meson8b.dtsi
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+++ b/arch/arm/boot/dts/meson8b.dtsi
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@@ -434,6 +434,8 @@ &gpio_intc {
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&hhi {
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clkc: clock-controller {
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compatible = "amlogic,meson8-clkc";
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+ clocks = <&xtal>;
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+ clock-names = "xtal";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@@ -508,8 +510,7 @@ &rtc {
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&saradc {
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compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
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- clocks = <&clkc CLKID_XTAL>,
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- <&clkc CLKID_SAR_ADC>;
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+ clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
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clock-names = "clkin", "core";
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amlogic,hhi-sysctrl = <&hhi>;
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nvmem-cells = <&temperature_calib>;
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@@ -523,31 +524,31 @@ &sdio {
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};
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&timer_abcde {
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- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
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+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
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clock-names = "xtal", "pclk";
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};
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&uart_AO {
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compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
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- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
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+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_A {
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compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
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- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
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+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_B {
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compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
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- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
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+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_C {
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compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
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- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
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+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
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clock-names = "baud", "xtal", "pclk";
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};
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Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
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(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
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inputs for the audio clock muxes.
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Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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Reported-by: kbuild test robot <lkp@intel.com>
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---
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arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++--
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1 file changed, 11 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
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index add6d7991fdf..b35d7444c1f4 100644
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--- a/arch/arm/boot/dts/meson8.dtsi
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+++ b/arch/arm/boot/dts/meson8.dtsi
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@@ -3,6 +3,7 @@
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* Copyright 2014 Carlo Caione <carlo@caione.org>
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*/
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+#include <dt-bindings/clock/meson8-ddr-clkc.h>
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <dt-bindings/gpio/meson8-gpio.h>
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#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
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@@ -195,6 +196,14 @@ mmcbus: bus@c8000000 {
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#size-cells = <1>;
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ranges = <0x0 0xc8000000 0x8000>;
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+ ddr_clkc: clock-controller@400 {
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+ compatible = "amlogic,meson8-ddr-clkc";
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+ reg = <0x400 0x20>;
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+ clocks = <&xtal>;
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+ clock-names = "xtal";
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+ #clock-cells = <1>;
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+ };
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+
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dmcbus: bus@6000 {
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compatible = "simple-bus";
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reg = <0x6000 0x400>;
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@@ -455,8 +464,8 @@ &gpio_intc {
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&hhi {
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clkc: clock-controller {
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compatible = "amlogic,meson8-clkc";
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- clocks = <&xtal>;
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- clock-names = "xtal";
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+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
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+ clock-names = "xtal", "ddr_pll";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
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(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
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inputs for the audio clock muxes.
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Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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---
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arch/arm/boot/dts/meson8b.dtsi | 13 +++++++++++--
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1 file changed, 11 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
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index 1934666ff60f..8ac8bdfaf58f 100644
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--- a/arch/arm/boot/dts/meson8b.dtsi
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+++ b/arch/arm/boot/dts/meson8b.dtsi
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@@ -4,6 +4,7 @@
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* Author: Carlo Caione <carlo@endlessm.com>
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*/
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+#include <dt-bindings/clock/meson8-ddr-clkc.h>
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <dt-bindings/gpio/meson8b-gpio.h>
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#include <dt-bindings/reset/amlogic,meson8b-reset.h>
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@@ -172,6 +173,14 @@ mmcbus: bus@c8000000 {
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#size-cells = <1>;
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ranges = <0x0 0xc8000000 0x8000>;
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+ ddr_clkc: clock-controller@400 {
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+ compatible = "amlogic,meson8b-ddr-clkc";
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+ reg = <0x400 0x20>;
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+ clocks = <&xtal>;
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+ clock-names = "xtal";
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+ #clock-cells = <1>;
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+ };
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+
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dmcbus: bus@6000 {
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compatible = "simple-bus";
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reg = <0x6000 0x400>;
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@@ -434,8 +443,8 @@ &gpio_intc {
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&hhi {
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clkc: clock-controller {
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compatible = "amlogic,meson8-clkc";
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- clocks = <&xtal>;
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- clock-names = "xtal";
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+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
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+ clock-names = "xtal", "ddr_pll";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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