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AR-1 - Adding support category for distributions AR-4 - Remove Allwinner legacy AR-5 - Drop Udoo family and move Udoo board into newly created imx6 family AR-9 - Rename sunxi-next to sunxi-legacy AR-10 - Rename sunxi-dev to sunxi-current AR-11 - Adding Radxa Rockpi S support AR-13 - Rename rockchip64-default to rockchip64-legacy AR-14 - Add rockchip64-current as mainline source AR-15 - Drop Rockchip 4.19.y NEXT, current become 5.3.y AR-16 - Rename RK3399 default to legacy AR-17 - Rename Odroid XU4 next and default to legacy 4.14.y, add DEV 5.4.y AR-18 - Add Odroid N2 current mainline AR-19 - Move Odroid C1 to meson family AR-20 - Rename mvebu64-default to mvebu64-legacy AR-21 - Rename mvebu-default to mvebu-legacy AR-22 - Rename mvebu-next to mvebu-current AR-23 - Drop meson64 default and next, current becomes former DEV 5.3.y AR-24 - Drop cubox family and move Cubox/Hummingboard boards under imx6 AR-26 - Adjust motd AR-27 - Enabling distribution release status AR-28 - Added new GCC compilers AR-29 - Implementing Ubuntu Eoan AR-30 - Add desktop packages per board or family AR-31 - Remove (Ubuntu/Debian) distribution name from image filename AR-32 - Move arch configs from configuration.sh to separate arm64 and armhf config files AR-33 - Revision numbers for beta builds changed to day_in_the_year AR-34 - Patches support linked patches AR-35 - Break meson64 family into gxbb and gxl AR-36 - Add Nanopineo2 Black AR-38 - Upgrade option from old branches to new one via armbian-config AR-41 - Show full timezone info AR-43 - Merge Odroid N2 to meson64 AR-44 - Enable FORCE_BOOTSCRIPT_UPDATE for all builds
80 lines
2.5 KiB
Text
80 lines
2.5 KiB
Text
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
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index 75491fc84..c2adf380b 100644
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--- a/drivers/cpufreq/armada-37xx-cpufreq.c
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+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
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@@ -162,11 +162,25 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
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}
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/*
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- * Set cpu clock source, for all the level we keep the same
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- * clock source that the one already configured. For this one
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- * we need to use the clock framework
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- */
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+ * Set CPU clock source, for all the level we keep the same
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+ * clock source that the one already configured with DVS
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+ * disabled. For this one we need to use the clock framewor
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+ */
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parent = clk_get_parent(clk);
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+
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+ /*
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+ * Unset parent clock to force the clock framework setting again
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+ * the clock parent
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+ */
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+ clk_set_parent(clk, NULL);
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+
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+ /*
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+ * For the Armada 37xx CPU clocks, setting the parent will
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+ * actually configure the parent when DVFS is enabled. At
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+ * hardware level it will be a different register from the one
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+ * read when doing clk_get_parent that will be set with
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+ * clk_set_parent.
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+ */
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clk_set_parent(clk, parent);
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}
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@@ -359,11 +373,11 @@ static int __init armada37xx_cpufreq_driver_init(void)
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struct armada_37xx_dvfs *dvfs;
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struct platform_device *pdev;
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unsigned long freq;
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- unsigned int cur_frequency;
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+ unsigned int cur_frequency, base_frequency;
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struct regmap *nb_pm_base, *avs_base;
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struct device *cpu_dev;
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int load_lvl, ret;
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- struct clk *clk;
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+ struct clk *clk, *parent;
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nb_pm_base =
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syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
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@@ -399,6 +413,22 @@ static int __init armada37xx_cpufreq_driver_init(void)
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return PTR_ERR(clk);
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}
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+ parent = clk_get_parent(clk);
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+ if (IS_ERR(parent)) {
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+ dev_err(cpu_dev, "Cannot get parent clock for CPU0\n");
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+ clk_put(clk);
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+ return PTR_ERR(parent);
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+ }
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+
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+ /* Get parent CPU frequency */
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+ base_frequency = clk_get_rate(parent);
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+
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+ if (!base_frequency) {
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+ dev_err(cpu_dev, "Failed to get parent clock rate for CPU\n");
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+ clk_put(clk);
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+ return -EINVAL;
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+ }
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+
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/* Get nominal (current) CPU frequency */
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cur_frequency = clk_get_rate(clk);
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if (!cur_frequency) {
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@@ -431,7 +461,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
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for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
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load_lvl++) {
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unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
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- freq = cur_frequency / dvfs->divider[load_lvl];
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+ freq = base_frequency / dvfs->divider[load_lvl];
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ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
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if (ret)
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goto remove_opp;
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