mirror of
https://github.com/Fishwaldo/build.git
synced 2025-07-23 13:29:33 +00:00
Adapted rk322x-dev to kernel 5.8.y Added ssv6x5x driver to legacy kernel, rk322x-config now allows the user to select which driver load at boot Added esp8089 kernel module, device tree overlay and detection in rk322x-config script Fixed some indentation Added reset button binding Added sdcard debounce Fixes indentation, added device tree overlay for high-leakage cpus Added support for bluetooth device tree overlay and realtek systemd service for rk322x targets
1651 lines
36 KiB
Text
1651 lines
36 KiB
Text
diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
|
|
index c8c4b00ecb94..4ca357835a48 100644
|
|
--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
|
|
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
|
|
@@ -1,7 +1,9 @@
|
|
Rockchip SuperSpeed DWC3 USB SoC controller
|
|
|
|
Required properties:
|
|
-- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
|
|
+- compatible: should be one of the following:
|
|
+ - "rockchip,rk3399-dwc3": for rk3399 SoC
|
|
+ - "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3": for rk3328 SoC
|
|
- clocks: A list of phandle + clock-specifier pairs for the
|
|
clocks listed in clock-names
|
|
- clock-names: Should contain the following:
|
|
--
|
|
2.17.1
|
|
|
|
|
|
From 041ddb731b5e025e1bea4d3d68c30f09521ca8dd Mon Sep 17 00:00:00 2001
|
|
From: William Wu <william.wu@rock-chips.com>
|
|
Date: Mon, 4 Dec 2017 10:40:39 +0100
|
|
Subject: [PATCH] arm64: dts: rockchip: add usb3 controller node for RK3328
|
|
SoCs
|
|
|
|
RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
|
|
core's general architecture. It can act as static xHCI host
|
|
controller, static device controller, USB 3.0/2.0 OTG basing
|
|
on ID of USB3.0 PHY.
|
|
|
|
Signed-off-by: William Wu <william.wu@rock-chips.com>
|
|
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|
---
|
|
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 32 ++++++++++++++++++++++++
|
|
1 file changed, 32 insertions(+)
|
|
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
|
index a4b0947f82a7..bc9186f66d9c 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
|
@@ -1037,6 +1037,38 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ usbdrd3: usb@ff600000 {
|
|
+ compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
|
|
+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
|
|
+ <&cru ACLK_USB3OTG>;
|
|
+ clock-names = "ref_clk", "suspend_clk",
|
|
+ "bus_clk";
|
|
+ resets = <&cru SRST_USB3OTG>;
|
|
+ reset-names = "usb3-otg";
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ usbdrd_dwc3: dwc3@ff600000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0xff600000 0x0 0x100000>;
|
|
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>,
|
|
+ <&cru SCLK_USB3OTG_SUSPEND>;
|
|
+ clock-names = "ref", "bus_early", "suspend";
|
|
+ dr_mode = "otg";
|
|
+ phy_type = "utmi_wide";
|
|
+ snps,dis_enblslpm_quirk;
|
|
+ snps,dis-u2-freeclk-exists-quirk;
|
|
+ snps,dis_u2_susphy_quirk;
|
|
+ snps,dis_u3_susphy_quirk;
|
|
+ snps,dis-del-phy-power-chg-quirk;
|
|
+ snps,dis-tx-ipgap-linecheck-quirk;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
gic: interrupt-controller@ff811000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
--
|
|
2.17.1
|
|
|
|
|
|
From 6b2ec0b7974089cd179241595d76f204151a0329 Mon Sep 17 00:00:00 2001
|
|
From: Heiko Stuebner <heiko@sntech.de>
|
|
Date: Mon, 4 Dec 2017 10:40:41 +0100
|
|
Subject: [PATCH] arm64: dts: rockchip: enable usb3 nodes on rk3328-rock64
|
|
|
|
Enable the nodes to make the usb3 port usable on that board.
|
|
|
|
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|
---
|
|
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 9 +++++++++
|
|
1 file changed, 9 insertions(+)
|
|
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
|
|
index 345c045c58e6..1cc3a8f5c3d7 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
|
|
@@ -364,6 +364,15 @@
|
|
status = "okay";
|
|
};
|
|
|
|
+&usbdrd3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd_dwc3 {
|
|
+ dr_mode = "host";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
&vop {
|
|
status = "okay";
|
|
};
|
|
--
|
|
2.17.1
|
|
|
|
|
|
From 39e4f61930b2b6108ae6423698f233d6d2b57958 Mon Sep 17 00:00:00 2001
|
|
From: Jonas Karlman <jonas@kwiboo.se>
|
|
Date: Tue, 12 Mar 2019 19:42:03 +0000
|
|
Subject: [PATCH] arm64: dts: rockchip: enable usb3 nodes on rk3328-roc-cc
|
|
|
|
Enable the nodes to make the usb3 port usable on that board.
|
|
|
|
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
|
---
|
|
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 9 +++++++++
|
|
1 file changed, 9 insertions(+)
|
|
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
|
index b58948f478a1..78e0e23d1efb 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
|
@@ -373,6 +373,15 @@
|
|
status = "okay";
|
|
};
|
|
|
|
+&usbdrd3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd_dwc3 {
|
|
+ dr_mode = "host";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
&vop {
|
|
status = "okay";
|
|
};
|
|
--
|
|
2.17.1
|
|
|
|
|
|
From aec6055775b63eaeb6b4a509b37aa6718fa2f84f Mon Sep 17 00:00:00 2001
|
|
From: Jonas Karlman <jonas@kwiboo.se>
|
|
Date: Sun, 12 May 2019 12:40:00 +0000
|
|
Subject: [PATCH] arm64: dts: rockchip: enable usb3 nodes on rk3328-rockbox
|
|
|
|
---
|
|
arch/arm64/boot/dts/rockchip/rk3328-rockbox.dts | 9 +++++++++
|
|
1 file changed, 9 insertions(+)
|
|
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rockbox.dts b/arch/arm64/boot/dts/rockchip/rk3328-rockbox.dts
|
|
index b82708cfe742..6f5eab7c0050 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3328-rockbox.dts
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rockbox.dts
|
|
@@ -340,6 +340,15 @@
|
|
status = "okay";
|
|
};
|
|
|
|
+&usbdrd3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd_dwc3 {
|
|
+ dr_mode = "host";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
&vop {
|
|
status = "okay";
|
|
};
|
|
--
|
|
2.17.1
|
|
|
|
|
|
From b1c19ab3e134c7ba1c0352b484fa5b3591f5af4d Mon Sep 17 00:00:00 2001
|
|
From: Jonas Karlman <jonas@kwiboo.se>
|
|
Date: Thu, 7 Feb 2019 22:03:15 +0000
|
|
Subject: [PATCH] HACK: ARM: dts: rockchip: disable vopl node on rk3288
|
|
|
|
---
|
|
arch/arm/boot/dts/rk3288-miqi.dts | 8 --------
|
|
arch/arm/boot/dts/rk3288-tinker.dtsi | 8 --------
|
|
2 files changed, 16 deletions(-)
|
|
|
|
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
|
|
index 8428095934f5..8d8a4f49e4af 100644
|
|
--- a/arch/arm/boot/dts/rk3288-miqi.dts
|
|
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
|
|
@@ -438,14 +438,6 @@
|
|
status = "okay";
|
|
};
|
|
|
|
-&vopl {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vopl_mmu {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
&wdt {
|
|
status = "okay";
|
|
};
|
|
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
|
|
index 49b64f4908cd..5976c9a8eb0c 100644
|
|
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
|
|
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
|
|
@@ -534,14 +534,6 @@
|
|
status = "okay";
|
|
};
|
|
|
|
-&vopl {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vopl_mmu {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
&wdt {
|
|
status = "okay";
|
|
};
|
|
--
|
|
2.17.1
|
|
|
|
|
|
From b255ef1b90ebee3cfb44b545f75aa00e653411e8 Mon Sep 17 00:00:00 2001
|
|
From: Jonas Karlman <jonas@kwiboo.se>
|
|
Date: Mon, 15 Apr 2019 05:06:50 +0000
|
|
Subject: [PATCH] HACK: arm64: dts: rockchip: disable vopl node on rk3399
|
|
|
|
---
|
|
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 8 --------
|
|
arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi | 8 --------
|
|
arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 8 --------
|
|
arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts | 8 --------
|
|
arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 8 --------
|
|
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 8 --------
|
|
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 8 --------
|
|
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 8 --------
|
|
8 files changed, 64 deletions(-)
|
|
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
|
|
index e9e2a6fb623b..ee38f6da9368 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
|
|
@@ -801,11 +801,3 @@
|
|
&vopb_mmu {
|
|
status = "okay";
|
|
};
|
|
-
|
|
-&vopl {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vopl_mmu {
|
|
- status = "okay";
|
|
-};
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
|
|
index e87a04477440..f22f54dd0b73 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
|
|
@@ -797,11 +797,3 @@
|
|
&vopb_mmu {
|
|
status = "okay";
|
|
};
|
|
-
|
|
-&vopl {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vopl_mmu {
|
|
- status = "okay";
|
|
-};
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
|
|
index c88018a0ef35..002ed18477e6 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
|
|
@@ -747,11 +747,3 @@
|
|
&vopb_mmu {
|
|
status = "okay";
|
|
};
|
|
-
|
|
-&vopl {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vopl_mmu {
|
|
- status = "okay";
|
|
-};
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
|
|
index bfb9fa11adcc..aa7f5e89ad72 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
|
|
@@ -787,11 +787,3 @@
|
|
&vopb_mmu {
|
|
status = "okay";
|
|
};
|
|
-
|
|
-&vopl {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vopl_mmu {
|
|
- status = "okay";
|
|
-};
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
|
|
index 9f225e9c3d54..e917060f34c7 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
|
|
@@ -804,11 +804,3 @@
|
|
&vopb_mmu {
|
|
status = "okay";
|
|
};
|
|
-
|
|
-&vopl {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vopl_mmu {
|
|
- status = "okay";
|
|
-};
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
|
|
index e4c71c77c3ef..4fdbc692b138 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
|
|
@@ -728,11 +728,3 @@
|
|
&vopb_mmu {
|
|
status = "okay";
|
|
};
|
|
-
|
|
-&vopl {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vopl_mmu {
|
|
- status = "okay";
|
|
-};
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
|
|
index b69f0f2cbd67..aab612855670 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
|
|
@@ -654,11 +654,3 @@
|
|
&vopb_mmu {
|
|
status = "okay";
|
|
};
|
|
-
|
|
-&vopl {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vopl_mmu {
|
|
- status = "okay";
|
|
-};
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
|
|
index 0885d48011ab..471161b1accf 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
|
|
@@ -639,11 +639,3 @@
|
|
&vopb_mmu {
|
|
status = "okay";
|
|
};
|
|
-
|
|
-&vopl {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vopl_mmu {
|
|
- status = "okay";
|
|
-};
|
|
--
|
|
2.17.1
|
|
|
|
|
|
From 915a6f4cd5cb34c183e26f1c0889f93e55fa9de9 Mon Sep 17 00:00:00 2001
|
|
From: Jonas Karlman <jonas@kwiboo.se>
|
|
Date: Sun, 14 Apr 2019 21:16:31 +0000
|
|
Subject: [PATCH] HACK: arm64: dts: rockchip: rename hdmi sound card on rk3399
|
|
|
|
---
|
|
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
|
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
|
index 33cc21fcf4c1..adc8c1058196 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
|
@@ -1735,7 +1735,7 @@
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,format = "i2s";
|
|
simple-audio-card,mclk-fs = <256>;
|
|
- simple-audio-card,name = "hdmi-sound";
|
|
+ simple-audio-card,name = "HDMI";
|
|
status = "disabled";
|
|
|
|
simple-audio-card,cpu {
|
|
--
|
|
2.17.1
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From 259475f3ec472d65fe037e5c6c4d217062e4a55c Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sun, 12 May 2019 12:40:00 +0000
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Subject: [PATCH] WIP: arm64: dts: rockchip: add rk3328-box devices
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---
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arch/arm64/boot/dts/rockchip/Makefile | 3 +
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.../boot/dts/rockchip/rk3328-box-trn9.dts | 420 ++++++++++++++++++
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.../boot/dts/rockchip/rk3328-box-z28.dts | 367 +++++++++++++++
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arch/arm64/boot/dts/rockchip/rk3328-box.dts | 400 +++++++++++++++++
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4 files changed, 1190 insertions(+)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-box-trn9.dts
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-box-z28.dts
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-box.dts
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diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
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index 1df8933cb084..9ff568832af7 100644
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--- a/arch/arm64/boot/dts/rockchip/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
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@@ -3,6 +3,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-box.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-box-trn9.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-box-z28.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rockbox.dtb
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-box-trn9.dts b/arch/arm64/boot/dts/rockchip/rk3328-box-trn9.dts
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new file mode 100644
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index 000000000000..e611d12ea375
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-box-trn9.dts
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@@ -0,0 +1,420 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2017 PINE64
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+ */
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+
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+/dts-v1/;
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+#include "rk3328.dtsi"
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+
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+/ {
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+ model = "Rockchip RK3328 TRN9";
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+ compatible = "rockchip,rk3328-box-trn9", "rockchip,rk3328";
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+
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+ gmac_clkin: external-gmac-clock {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "gmac_clkin";
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+ #clock-cells = <0>;
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+ };
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+
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+ vcc_sd: sdmmc-regulator {
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+ compatible = "regulator-fixed";
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+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdmmc0m1_gpio>;
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+ regulator-name = "vcc_sd";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <&vcc_io>;
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+ };
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+
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+ vcc_host_5v: vcc-host-5v-regulator {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&usb30_host_drv>;
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+ regulator-name = "vcc_host_5v";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ vin-supply = <&vcc_sys>;
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+ };
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+
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+ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&usb20_host_drv>;
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+ regulator-name = "vcc_host1_5v";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ vin-supply = <&vcc_sys>;
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+ };
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+
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+ vcc_sys: vcc-sys {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_sys";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+
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+ ir-receiver {
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+ compatible = "gpio-ir-receiver";
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+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
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+ pinctrl-0 = <&ir_int>;
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+ pinctrl-names = "default";
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ power {
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+ gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
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+ linux,default-trigger = "default-on";
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+ default-state = "on";
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+ };
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+ };
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+
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+ sdio_pwrseq: sdio-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&wifi_enable_h>;
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+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
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+ };
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+};
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+
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+&analog_sound {
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+ status = "okay";
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+};
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+
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+&codec {
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+ status = "okay";
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+};
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+
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+&cpu0 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu1 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu2 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu3 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&emmc {
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+ bus-width = <8>;
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+ cap-mmc-highspeed;
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+ mmc-ddr-1_8v;
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+ mmc-hs200-1_8v;
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+ non-removable;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
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+ vmmc-supply = <&vcc_io>;
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+ vqmmc-supply = <&vcc18_emmc>;
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+ status = "okay";
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+};
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+
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+&gmac2io {
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+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
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+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
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+ clock_in_out = "input";
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+ phy-mode = "rgmii";
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+ phy-supply = <&vcc_io>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&rgmiim1_pins>;
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+ snps,aal;
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+ snps,pbl = <0x4>;
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+ snps,reset-gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>;
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+ snps,reset-active-low;
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+ snps,reset-delays-us = <0 10000 50000>;
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+ tx_delay = <0x26>;
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+ rx_delay = <0x11>;
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+ status = "okay";
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+};
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+
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+&gpu {
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+ mali-supply = <&vdd_logic>;
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+};
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+
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+&hdmi {
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+ status = "okay";
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+};
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+
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+&hdmiphy {
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+ status = "okay";
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+};
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+
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+&hdmi_sound {
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+ status = "okay";
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+};
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+
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+&i2c1 {
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+ status = "okay";
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+
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+ rk805: rk805@18 {
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+ compatible = "rockchip,rk805";
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+ reg = <0x18>;
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+ interrupt-parent = <&gpio2>;
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+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
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+ #clock-cells = <1>;
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+ clock-output-names = "xin32k", "rk805-clkout2";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pmic_int_l>;
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+ rockchip,system-power-controller;
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+ wakeup-source;
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+
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+ vcc1-supply = <&vcc_sys>;
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+ vcc2-supply = <&vcc_sys>;
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+ vcc3-supply = <&vcc_sys>;
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+ vcc4-supply = <&vcc_sys>;
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+ vcc5-supply = <&vcc_io>;
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+ vcc6-supply = <&vcc_io>;
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+
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+ regulators {
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+ vdd_logic: DCDC_REG1 {
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+ regulator-name = "vdd_logic";
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+ regulator-min-microvolt = <900000>;
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+ regulator-max-microvolt = <1150000>;
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+ regulator-ramp-delay = <12500>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
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+ };
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+
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+ vdd_arm: DCDC_REG2 {
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+ regulator-name = "vdd_arm";
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+ regulator-min-microvolt = <950000>;
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+ regulator-max-microvolt = <1350000>;
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+ regulator-ramp-delay = <12500>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <950000>;
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+ };
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+ };
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+
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+ vcc_ddr: DCDC_REG3 {
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+ regulator-name = "vcc_ddr";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcc_io: DCDC_REG4 {
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+ regulator-name = "vcc_io";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <3300000>;
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+ };
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+ };
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+
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+ vcc_18: LDO_REG1 {
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+ regulator-name = "vcc_18";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vcc18_emmc: LDO_REG2 {
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+ regulator-name = "vcc18_emmc";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vdd_10: LDO_REG3 {
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+ regulator-name = "vdd_10";
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+ regulator-min-microvolt = <1000000>;
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+ regulator-max-microvolt = <1000000>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
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+ };
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+ };
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+ };
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+};
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+
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+&i2s0 {
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+ status = "okay";
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+};
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+
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+&i2s1 {
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+ status = "okay";
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+};
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+
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+&io_domains {
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+ vccio1-supply = <&vcc_io>;
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+ vccio2-supply = <&vcc18_emmc>;
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+ vccio3-supply = <&vcc_io>;
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+ vccio4-supply = <&vcc_18>;
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+ vccio5-supply = <&vcc_io>;
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+ vccio6-supply = <&vcc_18>;
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+ pmuio-supply = <&vcc_io>;
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+ status = "okay";
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+};
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+
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+&pinctrl {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&clk_32k_out>;
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+
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+ clk_32k {
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+ clk_32k_out: clk-32k-out {
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+ rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
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+ };
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+ };
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+
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+ ir {
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+ ir_int: ir-int {
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+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ pmic {
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+ pmic_int_l: pmic-int-l {
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+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
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+ };
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+ };
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+
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+ sdio-pwrseq {
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+ wifi_enable_h: wifi-enable-h {
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+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
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+ <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>,
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+ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
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+ <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ usb2 {
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+ usb20_host_drv: usb20-host-drv {
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+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ usb3 {
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+ usb30_host_drv: usb30-host-drv {
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+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+};
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+
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+&sdmmc_ext {
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+ bus-width = <4>;
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+ cap-sd-highspeed;
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+ cap-sdio-irq;
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+ keep-power-in-suspend;
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+ mmc-pwrseq = <&sdio_pwrseq>;
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+ non-removable;
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+ num-slots = <1>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdmmc0ext_bus4 &sdmmc0ext_cmd &sdmmc0ext_clk>;
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+ sd-uhs-sdr104;
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+ status = "okay";
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+};
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+
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+&sdmmc {
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+ bus-width = <4>;
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+ cap-mmc-highspeed;
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+ cap-sd-highspeed;
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+ disable-wp;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
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+ vmmc-supply = <&vcc_sd>;
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+ status = "okay";
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+};
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+
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+&spdif {
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+ pinctrl-0 = <&spdifm0_tx>;
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+ status = "okay";
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+};
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+
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+&spdif_out {
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+ status = "okay";
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+};
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+
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+&spdif_sound {
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+ status = "okay";
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+};
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+
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+&tsadc {
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+ rockchip,hw-tshut-mode = <0>;
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+ rockchip,hw-tshut-polarity = <0>;
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+ status = "okay";
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+};
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+
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+&uart2 {
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+ status = "okay";
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+};
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+
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+&u2phy {
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+ status = "okay";
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+};
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+
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+&u2phy_host {
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+ status = "okay";
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+};
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+
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+&u2phy_otg {
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+ status = "okay";
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+};
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+
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+&usb20_otg {
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+ dr_mode = "host";
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+ status = "okay";
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+};
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+
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+&usb_host0_ehci {
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+ status = "okay";
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+};
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+
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+&usb_host0_ohci {
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+ status = "okay";
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+};
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+
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+&usbdrd3 {
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+ status = "okay";
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+};
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+
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+&usbdrd_dwc3 {
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+ dr_mode = "host";
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+ status = "okay";
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+};
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+
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+&vop {
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+ status = "okay";
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+};
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+
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+&vop_mmu {
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+ status = "okay";
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+};
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-box-z28.dts b/arch/arm64/boot/dts/rockchip/rk3328-box-z28.dts
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|
new file mode 100644
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|
index 000000000000..797b92924f21
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--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328-box-z28.dts
|
|
@@ -0,0 +1,367 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
+/*
|
|
+ * Copyright (c) 2017 PINE64
|
|
+ */
|
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+
|
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+/dts-v1/;
|
|
+#include "rk3328.dtsi"
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+
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+/ {
|
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+ model = "Rockchip RK3328 Z28";
|
|
+ compatible = "rockchip,rk3328-box-z28", "rockchip,rk3328";
|
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+
|
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+ chosen {
|
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+ stdout-path = "serial2:1500000n8";
|
|
+ };
|
|
+
|
|
+ vcc_sd: sdmmc-regulator {
|
|
+ compatible = "regulator-fixed";
|
|
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc0m1_gpio>;
|
|
+ regulator-name = "vcc_sd";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ vin-supply = <&vcc_io>;
|
|
+ };
|
|
+
|
|
+ vcc_host_5v: vcc-host-5v-regulator {
|
|
+ compatible = "regulator-fixed";
|
|
+ enable-active-high;
|
|
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&usb30_host_drv>;
|
|
+ regulator-name = "vcc_host_5v";
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ vin-supply = <&vcc_sys>;
|
|
+ };
|
|
+
|
|
+ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
|
|
+ compatible = "regulator-fixed";
|
|
+ enable-active-high;
|
|
+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&usb20_host_drv>;
|
|
+ regulator-name = "vcc_host1_5v";
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ vin-supply = <&vcc_sys>;
|
|
+ };
|
|
+
|
|
+ vcc_sys: vcc-sys {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vcc_sys";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ };
|
|
+
|
|
+ ir-receiver {
|
|
+ compatible = "gpio-ir-receiver";
|
|
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
|
|
+ pinctrl-0 = <&ir_int>;
|
|
+ pinctrl-names = "default";
|
|
+ };
|
|
+
|
|
+ leds {
|
|
+ compatible = "gpio-leds";
|
|
+
|
|
+ power {
|
|
+ gpios = <&rk805 0 GPIO_ACTIVE_HIGH>;
|
|
+ linux,default-trigger = "default-on";
|
|
+ default-state = "on";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu0 {
|
|
+ cpu-supply = <&vdd_arm>;
|
|
+};
|
|
+
|
|
+&cpu1 {
|
|
+ cpu-supply = <&vdd_arm>;
|
|
+};
|
|
+
|
|
+&cpu2 {
|
|
+ cpu-supply = <&vdd_arm>;
|
|
+};
|
|
+
|
|
+&cpu3 {
|
|
+ cpu-supply = <&vdd_arm>;
|
|
+};
|
|
+
|
|
+&emmc {
|
|
+ bus-width = <8>;
|
|
+ cap-mmc-highspeed;
|
|
+ mmc-ddr-1_8v;
|
|
+ mmc-hs200-1_8v;
|
|
+ non-removable;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
|
+ vmmc-supply = <&vcc_io>;
|
|
+ vqmmc-supply = <&vcc18_emmc>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&gmac2phy {
|
|
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
|
|
+ assigned-clock-rate = <50000000>;
|
|
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
|
|
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
|
|
+ clock_in_out = "output";
|
|
+ phy-supply = <&vcc_io>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ mali-supply = <&vdd_logic>;
|
|
+};
|
|
+
|
|
+&hdmi {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hdmiphy {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hdmi_sound {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ status = "okay";
|
|
+
|
|
+ rk805: rk805@18 {
|
|
+ compatible = "rockchip,rk805";
|
|
+ reg = <0x18>;
|
|
+ interrupt-parent = <&gpio2>;
|
|
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
|
|
+ #clock-cells = <1>;
|
|
+ clock-output-names = "xin32k", "rk805-clkout2";
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pmic_int_l>;
|
|
+ rockchip,system-power-controller;
|
|
+ wakeup-source;
|
|
+
|
|
+ vcc1-supply = <&vcc_sys>;
|
|
+ vcc2-supply = <&vcc_sys>;
|
|
+ vcc3-supply = <&vcc_sys>;
|
|
+ vcc4-supply = <&vcc_sys>;
|
|
+ vcc5-supply = <&vcc_io>;
|
|
+ vcc6-supply = <&vcc_io>;
|
|
+
|
|
+ regulators {
|
|
+ vdd_logic: DCDC_REG1 {
|
|
+ regulator-name = "vdd_logic";
|
|
+ regulator-min-microvolt = <900000>;
|
|
+ regulator-max-microvolt = <1150000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_arm: DCDC_REG2 {
|
|
+ regulator-name = "vdd_arm";
|
|
+ regulator-min-microvolt = <950000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <950000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_ddr: DCDC_REG3 {
|
|
+ regulator-name = "vcc_ddr";
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_io: DCDC_REG4 {
|
|
+ regulator-name = "vcc_io";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <3300000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_18: LDO_REG1 {
|
|
+ regulator-name = "vcc_18";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1800000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc18_emmc: LDO_REG2 {
|
|
+ regulator-name = "vcc18_emmc";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1800000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_10: LDO_REG3 {
|
|
+ regulator-name = "vdd_10";
|
|
+ regulator-min-microvolt = <1000000>;
|
|
+ regulator-max-microvolt = <1000000>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2s0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&io_domains {
|
|
+ vccio1-supply = <&vcc_io>;
|
|
+ vccio2-supply = <&vcc18_emmc>;
|
|
+ vccio3-supply = <&vcc_io>;
|
|
+ vccio4-supply = <&vcc_18>;
|
|
+ vccio5-supply = <&vcc_io>;
|
|
+ vccio6-supply = <&vcc_io>;
|
|
+ pmuio-supply = <&vcc_io>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&clk_32k_out>;
|
|
+
|
|
+ clk_32k {
|
|
+ clk_32k_out: clk-32k-out {
|
|
+ rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ir {
|
|
+ ir_int: ir-int {
|
|
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmic {
|
|
+ pmic_int_l: pmic-int-l {
|
|
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb2 {
|
|
+ usb20_host_drv: usb20-host-drv {
|
|
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb3 {
|
|
+ usb30_host_drv: usb30-host-drv {
|
|
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc {
|
|
+ bus-width = <4>;
|
|
+ cap-mmc-highspeed;
|
|
+ cap-sd-highspeed;
|
|
+ disable-wp;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
|
|
+ vmmc-supply = <&vcc_sd>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spdif {
|
|
+ pinctrl-0 = <&spdifm0_tx>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spdif_out {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spdif_sound {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&tsadc {
|
|
+ rockchip,hw-tshut-mode = <0>;
|
|
+ rockchip,hw-tshut-polarity = <0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy_host {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy_otg {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb20_otg {
|
|
+ dr_mode = "host";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host0_ehci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host0_ohci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd_dwc3 {
|
|
+ dr_mode = "host";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vop {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vop_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-box.dts b/arch/arm64/boot/dts/rockchip/rk3328-box.dts
|
|
new file mode 100644
|
|
index 000000000000..2526147fd48b
|
|
--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328-box.dts
|
|
@@ -0,0 +1,400 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
+/*
|
|
+ * Copyright (c) 2017 PINE64
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+#include "rk3328.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Rockchip RK3328 BOX";
|
|
+ compatible = "rockchip,rk3328-box", "rockchip,rk3328";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial2:1500000n8";
|
|
+ };
|
|
+
|
|
+ vcc_sd: sdmmc-regulator {
|
|
+ compatible = "regulator-fixed";
|
|
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc0m1_gpio>;
|
|
+ regulator-name = "vcc_sd";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ vin-supply = <&vcc_io>;
|
|
+ };
|
|
+
|
|
+ vcc_host_5v: vcc-host-5v-regulator {
|
|
+ compatible = "regulator-fixed";
|
|
+ enable-active-high;
|
|
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&usb30_host_drv>;
|
|
+ regulator-name = "vcc_host_5v";
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ vin-supply = <&vcc_sys>;
|
|
+ };
|
|
+
|
|
+ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
|
|
+ compatible = "regulator-fixed";
|
|
+ enable-active-high;
|
|
+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&usb20_host_drv>;
|
|
+ regulator-name = "vcc_host1_5v";
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ vin-supply = <&vcc_sys>;
|
|
+ };
|
|
+
|
|
+ vcc_sys: vcc-sys {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vcc_sys";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ };
|
|
+
|
|
+ ir-receiver {
|
|
+ compatible = "gpio-ir-receiver";
|
|
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
|
|
+ pinctrl-0 = <&ir_int>;
|
|
+ pinctrl-names = "default";
|
|
+ };
|
|
+
|
|
+ leds {
|
|
+ compatible = "gpio-leds";
|
|
+
|
|
+ led1 {
|
|
+ gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
|
|
+ linux,default-trigger = "default-on";
|
|
+ default-state = "on";
|
|
+ };
|
|
+
|
|
+ led2 {
|
|
+ gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
|
|
+ linux,default-trigger = "mmc0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdio_pwrseq: sdio-pwrseq {
|
|
+ compatible = "mmc-pwrseq-simple";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&wifi_enable_h>;
|
|
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu0 {
|
|
+ cpu-supply = <&vdd_arm>;
|
|
+};
|
|
+
|
|
+&cpu1 {
|
|
+ cpu-supply = <&vdd_arm>;
|
|
+};
|
|
+
|
|
+&cpu2 {
|
|
+ cpu-supply = <&vdd_arm>;
|
|
+};
|
|
+
|
|
+&cpu3 {
|
|
+ cpu-supply = <&vdd_arm>;
|
|
+};
|
|
+
|
|
+&emmc {
|
|
+ bus-width = <8>;
|
|
+ cap-mmc-highspeed;
|
|
+ mmc-ddr-1_8v;
|
|
+ mmc-hs200-1_8v;
|
|
+ non-removable;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
|
+ vmmc-supply = <&vcc_io>;
|
|
+ vqmmc-supply = <&vcc18_emmc>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&gmac2phy {
|
|
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
|
|
+ assigned-clock-rate = <50000000>;
|
|
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
|
|
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
|
|
+ clock_in_out = "output";
|
|
+ phy-supply = <&vcc_io>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ mali-supply = <&vdd_logic>;
|
|
+};
|
|
+
|
|
+&hdmi {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hdmiphy {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hdmi_sound {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ status = "okay";
|
|
+
|
|
+ rk805: rk805@18 {
|
|
+ compatible = "rockchip,rk805";
|
|
+ reg = <0x18>;
|
|
+ interrupt-parent = <&gpio2>;
|
|
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
|
|
+ #clock-cells = <1>;
|
|
+ clock-output-names = "xin32k", "rk805-clkout2";
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pmic_int_l>;
|
|
+ rockchip,system-power-controller;
|
|
+ wakeup-source;
|
|
+
|
|
+ vcc1-supply = <&vcc_sys>;
|
|
+ vcc2-supply = <&vcc_sys>;
|
|
+ vcc3-supply = <&vcc_sys>;
|
|
+ vcc4-supply = <&vcc_sys>;
|
|
+ vcc5-supply = <&vcc_io>;
|
|
+ vcc6-supply = <&vcc_io>;
|
|
+
|
|
+ regulators {
|
|
+ vdd_logic: DCDC_REG1 {
|
|
+ regulator-name = "vdd_logic";
|
|
+ regulator-min-microvolt = <900000>;
|
|
+ regulator-max-microvolt = <1150000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_arm: DCDC_REG2 {
|
|
+ regulator-name = "vdd_arm";
|
|
+ regulator-min-microvolt = <950000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <950000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_ddr: DCDC_REG3 {
|
|
+ regulator-name = "vcc_ddr";
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_io: DCDC_REG4 {
|
|
+ regulator-name = "vcc_io";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <3300000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_18: LDO_REG1 {
|
|
+ regulator-name = "vcc_18";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1800000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc18_emmc: LDO_REG2 {
|
|
+ regulator-name = "vcc18_emmc";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1800000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_10: LDO_REG3 {
|
|
+ regulator-name = "vdd_10";
|
|
+ regulator-min-microvolt = <1000000>;
|
|
+ regulator-max-microvolt = <1000000>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2s0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&io_domains {
|
|
+ vccio1-supply = <&vcc_io>;
|
|
+ vccio2-supply = <&vcc18_emmc>;
|
|
+ vccio3-supply = <&vcc_io>;
|
|
+ vccio4-supply = <&vcc_18>;
|
|
+ vccio5-supply = <&vcc_io>;
|
|
+ vccio6-supply = <&vcc_io>;
|
|
+ pmuio-supply = <&vcc_io>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&clk_32k_out>;
|
|
+
|
|
+ clk_32k {
|
|
+ clk_32k_out: clk-32k-out {
|
|
+ rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ir {
|
|
+ ir_int: ir-int {
|
|
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmic {
|
|
+ pmic_int_l: pmic-int-l {
|
|
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdio-pwrseq {
|
|
+ wifi_enable_h: wifi-enable-h {
|
|
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_4ma>,
|
|
+ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none_4ma>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb2 {
|
|
+ usb20_host_drv: usb20-host-drv {
|
|
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb3 {
|
|
+ usb30_host_drv: usb30-host-drv {
|
|
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdio {
|
|
+ bus-width = <4>;
|
|
+ cap-sd-highspeed;
|
|
+ cap-sdio-irq;
|
|
+ keep-power-in-suspend;
|
|
+ mmc-pwrseq = <&sdio_pwrseq>;
|
|
+ non-removable;
|
|
+ num-slots = <1>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
|
|
+ sd-uhs-sdr104;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&sdmmc {
|
|
+ bus-width = <4>;
|
|
+ cap-mmc-highspeed;
|
|
+ cap-sd-highspeed;
|
|
+ disable-wp;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
|
|
+ vmmc-supply = <&vcc_sd>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spdif {
|
|
+ pinctrl-0 = <&spdifm0_tx>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spdif_out {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spdif_sound {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&tsadc {
|
|
+ rockchip,hw-tshut-mode = <0>;
|
|
+ rockchip,hw-tshut-polarity = <0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy_host {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy_otg {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb20_otg {
|
|
+ dr_mode = "host";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host0_ehci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host0_ohci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd_dwc3 {
|
|
+ dr_mode = "host";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vop {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vop_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
--
|
|
2.17.1
|
|
|