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a57ce78b37
* Bump to 4.18, removing the obvious, fixing build problems, put some on waiting. * Pin 4.18 to DEV, rollback 4.14 to NEXT, adjust configs, remove one deprecated patch from NEXT and add board-h3-address-some-stability-issues.patch * Adjust few boards in development to new reality, removing it from NEXT for now * Adjust few board configs * Board config adjustement * Adjust few boards configs * Port NeoCore2 and Neo21.1 to 4.14.y * Adjust board config * Adjust board config
41 lines
1.2 KiB
Groff
41 lines
1.2 KiB
Groff
From 958d54aad158b794f29f52567b96cd3ed8e0cae2 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Sat, 23 Dec 2017 00:20:21 +0800
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Subject: [PATCH 13/35] arm64: allwinner: h6: add node for R_PIO pin controller
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Allwinner H6 SoC has a R_PIO pin controller which controls PL and PM
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GPIO banks.
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Add support for it.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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index db0263e..41fa2c6 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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@@ -240,5 +240,18 @@
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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+
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+ r_pio: pinctrl@7022000 {
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+ compatible = "allwinner,sun50i-h6-r-pinctrl";
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+ reg = <0x07022000 0x400>;
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+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
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+ clock-names = "apb", "hosc", "losc";
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+ gpio-controller;
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+ #gpio-cells = <3>;
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ };
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};
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};
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--
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2.7.4
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