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78d28f8083
1, format all patches from https://github.com/megous/linux `git format-patch 79bf89b88a87f2ebf147f76d8c40183283b49b51...2a7cb228d29c3882c1414c10a44c5f3f59bfa44d` and copy them to sunxi-next with prefix `0000-` 2, remove unnecessary patches, due to they are revert of upstream patches:4d867e2bd64e674a3000b8e05fe47e8bb8175edda2888276ee3, remove fail to apply and no use:960ddd63a84, remove WireGuard patch:1cd13b836c5, remove meaningless patch:f26e36379a6, remove merged or included by megous/linux patches: 0112-mfd-axp20x-Add-supported-cells-for-AXP803.patch board-bpi-m3-make-ethernet-working.patch board-pine-h6-pine-h6-0025-phy-sun4i-usb-add-support-for-missing-USB-PHY-index.patch 7, remove stable release update patches. ignored. 8, rebase sunxi-next/sunxi64-next to upstream linux-4.19.y test result: all patches applied, no error. orangepipc/orangpioneplus build OK. Signed-off-by: Zhang Ning <832666+zhangn1985@users.noreply.github.com>
55 lines
1.6 KiB
Diff
55 lines
1.6 KiB
Diff
From 5b367397da1947fcbf6ed1091c351808218e59bc Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Thu, 12 Jan 2017 16:34:57 +0100
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Subject: [PATCH 01/82] clk: sunxi-ng: Set maximum M = 1 for H3 pll-cpux clock
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When using M factor greater than 1 system is experiencing
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occasional lockups.
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This change was verified to fix lockups with PLL stress
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tester available at https://github.com/megous/h3-firmware.
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Note that M factor must not be used outside the kernel
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either, so for example u-boot needs a similar patch.
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 24 +++++++++++++++---------
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1 file changed, 15 insertions(+), 9 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 77ed0b0ba681..8d47742def49 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -30,15 +30,21 @@
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#include "ccu-sun8i-h3.h"
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-static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
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- "osc24M", 0x000,
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- 8, 5, /* N */
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- 4, 2, /* K */
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- 0, 2, /* M */
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- 16, 2, /* P */
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- BIT(31), /* gate */
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- BIT(28), /* lock */
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- CLK_SET_RATE_UNGATE);
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+static struct ccu_nkmp pll_cpux_clk = {
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+ .enable = BIT(31),
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+ .lock = BIT(28),
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+ .n = _SUNXI_CCU_MULT(8, 5),
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+ .k = _SUNXI_CCU_MULT(4, 2),
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+ .m = _SUNXI_CCU_DIV_MAX(0, 2, 1),
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+ .p = _SUNXI_CCU_DIV(16, 2),
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+ .common = {
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+ .reg = 0x000,
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+ .hw.init = CLK_HW_INIT("pll-cpux",
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+ "osc24M",
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+ &ccu_nkmp_ops,
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+ CLK_SET_RATE_UNGATE),
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+ },
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+};
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/*
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* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
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--
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2.20.1
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