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a57ce78b37
* Bump to 4.18, removing the obvious, fixing build problems, put some on waiting. * Pin 4.18 to DEV, rollback 4.14 to NEXT, adjust configs, remove one deprecated patch from NEXT and add board-h3-address-some-stability-issues.patch * Adjust few boards in development to new reality, removing it from NEXT for now * Adjust few board configs * Board config adjustement * Adjust few boards configs * Port NeoCore2 and Neo21.1 to 4.14.y * Adjust board config * Adjust board config
32 lines
1.3 KiB
Diff
32 lines
1.3 KiB
Diff
From e591feb3b4929daf4eec146735d019291af5034e Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Tue, 1 Aug 2017 21:12:56 +0800
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Subject: [PATCH] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3
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Allwinner H3 features a PLL named CLK_PLL_DE, and a mod clock for the
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"Display Engine 2.0" named CLK_DE. As the name indicated, the CLK_PLL_DE
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is a PLL for CLK_DE.
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Only CLK_DE and CLK_TVE have a parent of CLK_PLL_DE, and CLK_TVE is also
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one part of the display clocks.
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So allow CLK_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it).
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 1729ff6a5aaed..7a222ff1ad0a9 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -439,7 +439,7 @@ static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
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static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
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static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
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- 0x104, 0, 4, 24, 3, BIT(31), 0);
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+ 0x104, 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
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static const char * const tcon_parents[] = { "pll-video" };
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static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
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