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3c793e66ed
* Add initial config for R4S * Enabled r8169 module for rockchip64-current * NanoPi R4S board configuration file tweaks * Add u-boot configuration * Update PCI speed * Add DT to DEV kernel * Enable build targets Co-authored-by: Piotr Szczepanik <piter75@gmail.com>
164 lines
3.6 KiB
Diff
164 lines
3.6 KiB
Diff
From 7117f55d19dc3b902b8ce7e28b944d30105069a5 Mon Sep 17 00:00:00 2001
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From: jensen <jensenhuang@friendlyarm.com>
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Date: Fri, 6 Nov 2020 10:40:23 +0800
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Subject: [PATCH] arm64: dts: rk3399: Add dts file for nanopi-r4s
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Change-Id: I95cc83e6c4f7234d6ef7bb9ba98e1c65eebd8e73
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Signed-off-by: jensen <jensenhuang@friendlyarm.com>
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---
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arch/arm64/boot/dts/rockchip/Makefile | 2 +
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.../dts/rockchip/rk3399-nanopi-r4s1.dts | 170 +++++++++++++++
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.../dts/rockchip/rk3399-nanopi-r4s2.dts | 203 ++++++++++++++++++
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3 files changed, 375 insertions(+)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s1.dts
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s2.dts
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diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
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index 71e33037e..eabf39e71 100644
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--- a/arch/arm64/boot/dts/rockchip/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
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@@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4v2.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
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diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
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new file mode 100644
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index 000000000000..b932e3bb6396
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
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@@ -0,0 +1,131 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
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+ * (http://www.friendlyarm.com)
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+ */
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+
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+/dts-v1/;
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+#include "rk3399-nanopi4.dtsi"
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+
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+/ {
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+ model = "FriendlyElec NanoPi R4S";
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+ compatible = "friendlyelec,nanopi-r4s", "rockchip,rk3399";
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+
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+ aliases {
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+ ethernet1 = &r8169;
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+ };
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+ vdd_5v: vdd-5v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vdd_5v";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ vcc5v0_core: vcc5v0-core {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_core";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ vin-supply = <&vdd_5v>;
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+ };
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+
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+ vcc5v0_usb1: vcc5v0-usb1 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_usb1";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+
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+ vcc5v0_usb2: vcc5v0-usb2 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_usb2";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+};
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+
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+&emmc_phy {
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+ status = "disabled";
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+};
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+
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+&sdhci {
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+ status = "disabled";
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+};
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+
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+&sdio0 {
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+ status = "disabled";
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+};
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+
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+&sdmmc {
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+ host-index-min = <1>;
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+};
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+
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+&i2s0 {
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+ status = "disabled";
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+};
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+
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+&pcie0 {
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+ max-link-speed = <1>;
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+ num-lanes = <1>;
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+ vpcie3v3-supply = <&vcc3v3_sys>;
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+
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+ pcie@0 {
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+ reg = <0x00000000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ r8169: pcie@0,0 {
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+ reg = <0x000000 0 0 0 0>;
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+ local-mac-address = [ 00 00 00 00 00 00 ];
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+ };
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+ };
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+};
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+
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+&fusb0 {
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+ status = "disabled";
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+};
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+
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+&cdn_dp {
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+ /delete-property/ extcon;
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+ status = "disabled";
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+};
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+
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+&tcphy0 {
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+ /delete-property/ extcon;
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+};
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+
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+&u2phy0 {
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+ /delete-property/ extcon;
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+};
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+
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+&usbdrd_dwc3_0 {
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+ /delete-property/ extcon;
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+ extcon = <&u2phy0>;
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+};
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+
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+&isp0_mmu {
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+ status = "disabled";
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+};
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+
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+&isp1_mmu {
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+ status = "disabled";
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+};
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+
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+&vcc3v3_sys {
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+ vin-supply = <&vcc5v0_core>;
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+};
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+
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+&u2phy0_host {
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+ phy-supply = <&vcc5v0_usb1>;
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+};
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+
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+&u2phy1_host {
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+ phy-supply = <&vcc5v0_usb2>;
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+};
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+
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+&vbus_typec {
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+ regulator-always-on;
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+ vin-supply = <&vdd_5v>;
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+};
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