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60 lines
No EOL
1.9 KiB
Diff
60 lines
No EOL
1.9 KiB
Diff
From d9ad129ac7a3114568a323f44316d9d5bfd9a3f9 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
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Date: Mon, 5 Mar 2018 11:04:31 +0100
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Subject: [PATCH 39/60] ARM: dts: sun8i: Add the H3/H5 CSI controller
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The H3 and H5 features the same CSI controller that was initially found on
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the A31.
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Add a DT node for it.
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Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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---
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arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 +++++++++++++++++++
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.../platform/sunxi/sun6i-csi/sun6i_csi.c | 1 +
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2 files changed, 23 insertions(+)
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diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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index ff05c532792d..be75e7cfdc3a 100644
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--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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@@ -550,6 +550,13 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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+ csi_pins: csi {
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+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
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+ "PE5", "PE6", "PE7", "PE8", "PE9",
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+ "PE10", "PE11";
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+ function = "csi";
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+ };
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+
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emac_rgmii_pins: emac0 {
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pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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"PD5", "PD7", "PD8", "PD9", "PD10",
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@@ -936,6 +943,21 @@
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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+ csi: camera@1cb0000 {
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+ compatible = "allwinner,sun8i-h3-csi",
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+ "allwinner,sun6i-a31-csi";
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+ reg = <0x01cb0000 0x1000>;
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+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_CSI>,
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+ <&ccu CLK_CSI_SCLK>,
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+ <&ccu CLK_DRAM_CSI>;
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+ clock-names = "bus", "mod", "ram";
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+ resets = <&ccu RST_BUS_CSI>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&csi_pins>;
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+ status = "disabled";
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+ };
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+
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rtc: rtc@1f00000 {
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compatible = "allwinner,sun6i-a31-rtc";
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reg = <0x01f00000 0x54>;
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