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61 lines
2 KiB
Diff
61 lines
2 KiB
Diff
From 1f82a2baa3b5935ed41738f38cf486872aa8a9f7 Mon Sep 17 00:00:00 2001
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From: Neil Armstrong <narmstrong@baylibre.com>
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Date: Fri, 13 Jan 2017 15:57:10 +0100
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Subject: [PATCH 48/93] drm/meson: Use crtc_state for hdisplay and fix atomic
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flush/enable sync for vsync commit
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Clean the crtc_enable by using the proper crtc_state instead of the state
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of the primary plane state data.
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Also fix the dependency to commit the plane changes even if enable is called
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after the flush.
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---
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drivers/gpu/drm/meson/meson_crtc.c | 15 +++++++++++----
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1 file changed, 11 insertions(+), 4 deletions(-)
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diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c
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index 749770e..d4b114d 100644
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--- a/drivers/gpu/drm/meson/meson_crtc.c
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+++ b/drivers/gpu/drm/meson/meson_crtc.c
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@@ -60,11 +60,18 @@ struct meson_crtc {
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static void meson_crtc_enable(struct drm_crtc *crtc)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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- struct drm_plane *plane = meson_crtc->priv->primary_plane;
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+ struct drm_crtc_state *crtc_state = crtc->state;
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struct meson_drm *priv = meson_crtc->priv;
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+ DRM_DEBUG_DRIVER("\n");
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+
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+ if (!crtc_state) {
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+ DRM_ERROR("Invalid crtc_state\n");
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+ return;
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+ }
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+
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/* Enable VPP Postblend */
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- writel(plane->state->crtc_w,
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+ writel(crtc_state->mode.hdisplay,
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priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
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writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
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@@ -79,6 +86,7 @@ static void meson_crtc_disable(struct drm_crtc *crtc)
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struct meson_drm *priv = meson_crtc->priv;
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priv->viu.osd1_enabled = false;
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+ priv->viu.osd1_commit = false;
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/* Disable VPP Postblend */
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writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
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@@ -115,8 +123,7 @@ static void meson_crtc_atomic_flush(struct drm_crtc *crtc,
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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struct meson_drm *priv = meson_crtc->priv;
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- if (priv->viu.osd1_enabled)
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- priv->viu.osd1_commit = true;
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+ priv->viu.osd1_commit = true;
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}
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static const struct drm_crtc_helper_funcs meson_crtc_helper_funcs = {
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--
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1.9.1
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