mirror of
https://github.com/Fishwaldo/build.git
synced 2025-04-11 16:41:51 +00:00
06451d37a6
the new cpu opp table in 4.19 now supports frequencies up to 1.368GHz, so this change updates the 1.3GHz overclock overlay as appropriate. overlay name has been changed to "cpu-clock-1.3GHz-1.3v" as this overlay is only needed for boards that provide a fixed-voltage GPIO regulator/switcher that operate at 1.1v/1.3v.
124 lines
3.4 KiB
Diff
124 lines
3.4 KiB
Diff
diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
|
|
index 3ef0a3737..fb6bee993 100644
|
|
--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
|
|
+++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
|
|
@@ -13,6 +13,8 @@ dtbo-$(CONFIG_ARCH_SUNXI) += \
|
|
sun50i-a64-w1-gpio.dtbo \
|
|
sun50i-h5-analog-codec.dtbo \
|
|
sun50i-h5-cir.dtbo \
|
|
+ sun50i-h5-cpu-clock-1.3GHz-1.3v.dtbo \
|
|
+ sun50i-h5-gpio-regulator-1.3v.dtbo \
|
|
sun50i-h5-i2c0.dtbo \
|
|
sun50i-h5-i2c1.dtbo \
|
|
sun50i-h5-i2c2.dtbo \
|
|
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dts
|
|
new file mode 100644
|
|
index 000000000..03cae05bd
|
|
--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dts
|
|
@@ -0,0 +1,61 @@
|
|
+// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v
|
|
+
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ fragment@0 {
|
|
+ target = <&cpu0_opp_table>;
|
|
+
|
|
+ __overlay__ {
|
|
+ compatible = "operating-points-v2";
|
|
+ opp-shared;
|
|
+
|
|
+ // in order to match the H5 DT cooling-maps, update the existing OP table in-place
|
|
+ // with the new voltages
|
|
+
|
|
+ opp@1056000000 {
|
|
+ opp-hz = /bits/ 64 <1056000000>;
|
|
+ opp-microvolt = <1300000 1300000 1300000>;
|
|
+ clock-latency-ns = <244144>; /* 8 32k periods */
|
|
+ };
|
|
+
|
|
+ opp@1104000000 {
|
|
+ opp-hz = /bits/ 64 <1104000000>;
|
|
+ opp-microvolt = <1300000 1300000 1300000>;
|
|
+ clock-latency-ns = <244144>; /* 8 32k periods */
|
|
+ };
|
|
+
|
|
+ opp@1152000000 {
|
|
+ opp-hz = /bits/ 64 <1152000000>;
|
|
+ opp-microvolt = <1300000 1300000 1300000>;
|
|
+ clock-latency-ns = <244144>; /* 8 32k periods */
|
|
+ };
|
|
+
|
|
+ opp@1200000000 {
|
|
+ opp-hz = /bits/ 64 <1200000000>;
|
|
+ opp-microvolt = <1300000 1300000 1300000>;
|
|
+ clock-latency-ns = <244144>; /* 8 32k periods */
|
|
+ };
|
|
+
|
|
+ opp@1224000000 {
|
|
+ opp-hz = /bits/ 64 <1224000000>;
|
|
+ opp-microvolt = <1300000 1300000 1300000>;
|
|
+ clock-latency-ns = <244144>; /* 8 32k periods */
|
|
+ };
|
|
+
|
|
+ opp@1248000000 {
|
|
+ opp-hz = /bits/ 64 <1248000000>;
|
|
+ opp-microvolt = <1300000 1300000 1300000>;
|
|
+ clock-latency-ns = <244144>; /* 8 32k periods */
|
|
+ };
|
|
+
|
|
+ opp@1296000000 {
|
|
+ opp-hz = /bits/ 64 <1296000000>;
|
|
+ opp-microvolt = <1300000 1300000 1300000>;
|
|
+ clock-latency-ns = <244144>; /* 8 32k periods */
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dts
|
|
new file mode 100644
|
|
index 000000000..4bf787c66
|
|
--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dts
|
|
@@ -0,0 +1,38 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun50i-h5";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/";
|
|
+
|
|
+ __overlay__ {
|
|
+ reg_vdd_cpux: gpio-regulator {
|
|
+ compatible = "regulator-gpio";
|
|
+ regulator-name = "vdd-cpux";
|
|
+ regulator-type = "voltage";
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <1100000>;
|
|
+ regulator-max-microvolt = <1300000>;
|
|
+ regulator-ramp-delay = <50>; /* 4ms */
|
|
+
|
|
+ gpios = <&r_pio 0 6 0>; /* PL6 */
|
|
+ enable-active-high;
|
|
+ gpios-states = <0x1>;
|
|
+ states = <1100000 0x0
|
|
+ 1300000 0x1>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&cpu0>;
|
|
+
|
|
+ __overlay__ {
|
|
+ cpu-supply = <®_vdd_cpux>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|