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build/patch/kernel/rk322x-current/01-linux-0013-v4l2-from-list.patch
Paolo 23604e8a0d
Introducing Rockchip RK322X SoC support (#2032) 
* Introducing Rockchip rk322x SoC support

Main features:

- Legacy kernel flavour based upon stable v2.x rk3288 Rockchip branch (https://github.com/rockchip-linux/kernel/tree/stable-4.4-rk3288-linux-v2.x)
- Current kernel flavour based on mainline 5.6.y kernel
- Mainline u-boot (v2020.04)
- Single generic tv box target (rk322x-box) which boots on all the known tv boxes
- Hardware devices (eMMC/NAND, led wiring configuration, SoC variant selection) modulation done by user at runtime via device tree overlays - a script (rk322x-config) is provided for autodetection and simple configuration by inexperienced users;
- Bits added to armbian-hardware-optimization to set affinity for irq handlers
- rk322x-box targets already added to targets.conf for automatic image creation

* Removed disabled patches
* Restored mysteriously removed comment character
2020-06-19 17:27:27 +02:00

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diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
index 28313c0f4e7c..d472a54d1c4d 100644
--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
+++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
@@ -2028,6 +2028,18 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type -
* - ``V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM``
- 0x00000004
- The DPB entry is a long term reference frame
+ * - ``V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE``
+ - 0x00000008
+ - The DPB entry is a field picture
+ * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_TOP``
+ - 0x00000010
+ - The DPB entry is a top field reference
+ * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM``
+ - 0x00000020
+ - The DPB entry is a bottom field reference
+ * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME``
+ - 0x00000030
+ - The DPB entry is a reference frame
``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (enum)``
Specifies the decoding mode to use. Currently exposes slice-based and
diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h
index e877bf1d537c..76020ebd1e6c 100644
--- a/include/media/h264-ctrls.h
+++ b/include/media/h264-ctrls.h
@@ -185,6 +185,10 @@ struct v4l2_ctrl_h264_slice_params {
#define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01
#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02
#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04
+#define V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE 0x08
+#define V4L2_H264_DPB_ENTRY_FLAG_REF_TOP 0x10
+#define V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM 0x20
+#define V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME 0x30
struct v4l2_h264_dpb_entry {
__u64 reference_ts;
--
2.17.1
From ef240de60cedea0264ca954a8e8e2fa25db097ae Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Tue, 29 Oct 2019 01:26:02 +0000
Subject: [PATCH] RFC: media: hantro: Fix H264 decoding of field encoded
content
This still need code cleanup and formatting
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../staging/media/hantro/hantro_g1_h264_dec.c | 17 +--
drivers/staging/media/hantro/hantro_h264.c | 122 ++++++++++++------
drivers/staging/media/hantro/hantro_hw.h | 2 +
3 files changed, 85 insertions(+), 56 deletions(-)
diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
index 424c648ce9fc..89cf5741280e 100644
--- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c
+++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
@@ -132,25 +132,12 @@ static void set_ref(struct hantro_ctx *ctx)
struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
const u8 *b0_reflist, *b1_reflist, *p_reflist;
struct hantro_dev *vpu = ctx->dev;
- u32 dpb_longterm = 0;
- u32 dpb_valid = 0;
int reg_num;
u32 reg;
int i;
- /*
- * Set up bit maps of valid and long term DPBs.
- * NOTE: The bits are reversed, i.e. MSb is DPB 0.
- */
- for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
- dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
-
- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
- dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
- }
- vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF);
- vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF);
+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF);
+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF);
/*
* Set up reference frame picture numbers.
diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c
index f2d3e81fb6ce..4db779354e89 100644
--- a/drivers/staging/media/hantro/hantro_h264.c
+++ b/drivers/staging/media/hantro/hantro_h264.c
@@ -225,17 +225,65 @@ static void prepare_table(struct hantro_ctx *ctx)
{
const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;
+ const struct v4l2_ctrl_h264_slice_params *slices = ctrls->slices;
struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu;
const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
+ u32 dpb_longterm = 0;
+ u32 dpb_valid = 0;
int i;
+ /*
+ * Set up bit maps of valid and long term DPBs.
+ * NOTE: The bits are reversed, i.e. MSb is DPB 0.
+ */
+ if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || (slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
+ for (i = 0; i < HANTRO_H264_DPB_SIZE * 2; ++i) {
+ // check for correct reference use
+ u32 flag = (i & 0x1) ? V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM : V4L2_H264_DPB_ENTRY_FLAG_REF_TOP;
+ if (dpb[i / 2].flags & flag)
+ dpb_valid |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
+
+ if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
+ dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
+ }
+
+ ctx->h264_dec.dpb_valid = dpb_valid;
+ ctx->h264_dec.dpb_longterm = dpb_longterm;
+ } else {
+ for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
+ dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
+
+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
+ dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
+ }
+
+ ctx->h264_dec.dpb_valid = dpb_valid << 16;
+ ctx->h264_dec.dpb_longterm = dpb_longterm << 16;
+ }
+
for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
- tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
- tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) {
+ tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
+ tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
+ } else {
+ tbl->poc[i * 2] = 0;
+ tbl->poc[i * 2 + 1] = 0;
+ }
}
- tbl->poc[32] = dec_param->top_field_order_cnt;
- tbl->poc[33] = dec_param->bottom_field_order_cnt;
+ if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || !(slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
+ if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC))
+ tbl->poc[32] = (slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ?
+ dec_param->bottom_field_order_cnt :
+ dec_param->top_field_order_cnt;
+ else
+ tbl->poc[32] = min(dec_param->top_field_order_cnt, dec_param->bottom_field_order_cnt);
+ tbl->poc[33] = 0;
+ } else {
+ tbl->poc[32] = dec_param->top_field_order_cnt;
+ tbl->poc[33] = dec_param->bottom_field_order_cnt;
+ }
reorder_scaling_list(ctx);
}
@@ -249,21 +297,6 @@ struct hantro_h264_reflist_builder {
u8 num_valid;
};
-static s32 get_poc(enum v4l2_field field, s32 top_field_order_cnt,
- s32 bottom_field_order_cnt)
-{
- switch (field) {
- case V4L2_FIELD_TOP:
- return top_field_order_cnt;
- case V4L2_FIELD_BOTTOM:
- return bottom_field_order_cnt;
- default:
- break;
- }
-
- return min(top_field_order_cnt, bottom_field_order_cnt);
-}
-
static void
init_reflist_builder(struct hantro_ctx *ctx,
struct hantro_h264_reflist_builder *b)
@@ -271,9 +304,7 @@ init_reflist_builder(struct hantro_ctx *ctx,
const struct v4l2_ctrl_h264_slice_params *slice_params;
const struct v4l2_ctrl_h264_decode_params *dec_param;
const struct v4l2_ctrl_h264_sps *sps;
- struct vb2_v4l2_buffer *buf = hantro_get_dst_buf(ctx);
const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
- struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q;
int cur_frame_num, max_frame_num;
unsigned int i;
@@ -285,21 +316,15 @@ init_reflist_builder(struct hantro_ctx *ctx,
memset(b, 0, sizeof(*b));
b->dpb = dpb;
- b->curpoc = get_poc(buf->field, dec_param->top_field_order_cnt,
- dec_param->bottom_field_order_cnt);
+ b->curpoc = (slice_params->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ?
+ dec_param->bottom_field_order_cnt :
+ dec_param->top_field_order_cnt;
for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) {
- int buf_idx;
-
- if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
+ u32 ref_flag = dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME;
+ if (!ref_flag)
continue;
- buf_idx = vb2_find_timestamp(cap_q, dpb[i].reference_ts, 0);
- if (buf_idx < 0)
- continue;
-
- buf = to_vb2_v4l2_buffer(vb2_get_buffer(cap_q, buf_idx));
-
/*
* Handle frame_num wraparound as described in section
* '8.2.4.1 Decoding process for picture numbers' of the spec.
@@ -311,8 +336,13 @@ init_reflist_builder(struct hantro_ctx *ctx,
else
b->frame_nums[i] = dpb[i].frame_num;
- b->pocs[i] = get_poc(buf->field, dpb[i].top_field_order_cnt,
- dpb[i].bottom_field_order_cnt);
+ if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME)
+ b->pocs[i] = min(dpb[i].bottom_field_order_cnt, dpb[i].top_field_order_cnt);
+ else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM)
+ b->pocs[i] = dpb[i].bottom_field_order_cnt;
+ else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_TOP)
+ b->pocs[i] = dpb[i].top_field_order_cnt;
+
b->unordered_reflist[b->num_valid] = i;
b->num_valid++;
}
@@ -466,8 +496,7 @@ build_b_ref_lists(const struct hantro_h264_reflist_builder *builder,
static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a,
const struct v4l2_h264_dpb_entry *b)
{
- return a->top_field_order_cnt == b->top_field_order_cnt &&
- a->bottom_field_order_cnt == b->bottom_field_order_cnt;
+ return a->reference_ts == b->reference_ts;
}
static void update_dpb(struct hantro_ctx *ctx)
@@ -481,13 +510,13 @@ static void update_dpb(struct hantro_ctx *ctx)
/* Disable all entries by default. */
for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++)
- ctx->h264_dec.dpb[i].flags &= ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE;
+ ctx->h264_dec.dpb[i].flags = 0;
/* Try to match new DPB entries with existing ones by their POCs. */
for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) {
const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i];
- if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
+ if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID))
continue;
/*
@@ -498,8 +527,7 @@ static void update_dpb(struct hantro_ctx *ctx)
struct v4l2_h264_dpb_entry *cdpb;
cdpb = &ctx->h264_dec.dpb[j];
- if (cdpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE ||
- !dpb_entry_match(cdpb, ndpb))
+ if (!dpb_entry_match(cdpb, ndpb))
continue;
*cdpb = *ndpb;
@@ -535,7 +563,11 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
unsigned int dpb_idx)
{
struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
+ const struct v4l2_ctrl_h264_decode_params *dec_param = ctx->h264_dec.ctrls.decode;
+ const struct v4l2_ctrl_h264_slice_params *slices = ctx->h264_dec.ctrls.slices;
dma_addr_t dma_addr = 0;
+ s32 cur_poc;
+ u32 flags;
if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
dma_addr = hantro_get_ref(ctx, dpb[dpb_idx].reference_ts);
@@ -553,7 +585,15 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
dma_addr = vb2_dma_contig_plane_dma_addr(buf, 0);
}
- return dma_addr;
+ cur_poc = slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD ?
+ dec_param->bottom_field_order_cnt :
+ dec_param->top_field_order_cnt;
+ flags = dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE ? 0x2 : 0;
+ flags |= abs(dpb[dpb_idx].top_field_order_cnt - cur_poc) <
+ abs(dpb[dpb_idx].bottom_field_order_cnt - cur_poc) ?
+ 0x1 : 0;
+
+ return dma_addr | flags;
}
int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx)
diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
index 2398d4c1f207..3dc7b8f27c32 100644
--- a/drivers/staging/media/hantro/hantro_hw.h
+++ b/drivers/staging/media/hantro/hantro_hw.h
@@ -88,6 +88,8 @@ struct hantro_h264_dec_hw_ctx {
struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE];
struct hantro_h264_dec_reflists reflists;
struct hantro_h264_dec_ctrls ctrls;
+ u32 dpb_longterm;
+ u32 dpb_valid;
};
/**
--
2.17.1
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