mirror of
https://github.com/Fishwaldo/build.git
synced 2025-03-22 14:51:41 +00:00
999 lines
22 KiB
Diff
999 lines
22 KiB
Diff
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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index 01180849..81523d5a 100644
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -1016,4 +1017,7 @@ dtstree := $(srctree)/$(src)
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dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
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always := $(dtb-y)
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+subdir-y := overlay
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clean-files := *.dtb
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+
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+dts-dirs += overlay
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diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
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new file mode 100644
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index 00000000..f9ca2574
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/Makefile
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@@ -0,0 +1,28 @@
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+dtbo-$(CONFIG_MACH_SUN8I) += \
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+ sun8i-h3-analog-codec.dtbo \
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+ sun8i-h3-cir.dtbo \
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+ sun8i-h3-i2c0.dtbo \
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+ sun8i-h3-i2c1.dtbo \
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+ sun8i-h3-i2c2.dtbo \
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+ sun8i-h3-pps-gpio.dtbo \
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+ sun8i-h3-pwm.dtbo \
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+ sun8i-h3-spdif-out.dtbo \
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+ sun8i-h3-spi-add-cs1.dtbo \
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+ sun8i-h3-spi-jedec-nor.dtbo \
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+ sun8i-h3-spi-spidev.dtbo \
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+ sun8i-h3-uart1.dtbo \
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+ sun8i-h3-uart2.dtbo \
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+ sun8i-h3-uart3.dtbo \
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+ sun8i-h3-usbhost0.dtbo \
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+ sun8i-h3-usbhost2.dtbo \
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+ sun8i-h3-usbhost3.dtbo \
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+ sun8i-h3-w1-gpio.dtbo
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+
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+scr-$(CONFIG_MACH_SUN8I) += sun8i-h3-fixup.scr
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+
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+dtbotxt-$(CONFIG_MACH_SUN8I) += README.sun8i-h3-overlays
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+
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+targets += $(dtbo-y) $(scr-y) $(dtbotxt-y)
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+
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+always := $(dtbo-y) $(scr-y) $(dtbotxt-y)
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+clean-files := *.dtbo *.scr
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diff --git a/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays
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new file mode 100644
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index 00000000..0ae207a1
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays
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@@ -0,0 +1,245 @@
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+This document describes overlays provided in the kernel packages
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+For generic Armbian overlays documentation please see
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+https://docs.armbian.com/User-Guide_Allwinner_overlays/
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+
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+### Platform:
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+
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+sun8i-h3 (Allwinner H3)
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+
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+### Platform details:
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+
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+Supported pin banks: PA, PC, PD, PG
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+
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+Both SPI controllers have only one hardware CS pin exposed,
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+adding fixed software (GPIO) chip selects is possible with a separate overlay
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+
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+### Provided overlays:
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+
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+- analog-codec
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+- cir
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+- i2c0
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+- i2c1
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+- i2c2
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+- pps-gpio
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+- pwm
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+- spdif-out
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+- spi-add-cs1
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+- spi-jedec-nor
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+- spi-spidev
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+- uart1
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+- uart2
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+- uart3
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+- usbhost0
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+- usbhost2
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+- usbhost3
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+- w1-gpio
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+
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+### Overlay details:
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+
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+### analog-codec
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+
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+Activates SoC analog codec driver that provides Line Out and Mic In
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+functionality
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+
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+### cir
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+
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+Activates CIR (Infrared remote) receiver
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+
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+CIR pin: PL11
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+
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+### i2c0
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+
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+Activates TWI/I2C bus 0
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+
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+I2C0 pins (SCL, SDA): PA11, PA12
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+
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+### i2c1
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+
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+Activates TWI/I2C bus 1
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+
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+I2C1 pins (SCL, SDA): PA18, PA19
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+
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+### i2c2
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+
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+Activates TWI/I2C bus 2
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+
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+I2C2 pins (SCL, SDA): PE12, PE13
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+
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+On most board this bus is wired to Camera (CSI) socket
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+
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+### pps-gpio
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+
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+Activates pulse-per-second GPIO client
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+
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+Parameters:
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+
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+param_pps_pin (pin)
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+ Pin PPS source is connected to
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+ Optional
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+ Default: PD14
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+
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+param_pps_falling_edge (bool)
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+ Assert by falling edge
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+ Optional
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+ Default: 0
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+ When set (to 1), assert is indicated by a falling edge
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+ (instead of by a rising edge)
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+
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+### pwm
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+
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+Activates hardware PWM controller
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+
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+PWM pin: PA5
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+
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+Pin PA5 is used as UART0 RX by default, so if this overlay is activated,
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+UART0 and kernel console on ttyS0 will be disabled
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+
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+### spdif-out
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+
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+Activates SPDIF/Toslink audio output
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+
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+SPDIF pin: PA17
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+
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+### spi-add-cs1
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+
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+Adds support for using SPI chip select 1 with GPIO for both SPI controllers
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+Respective GPIO will be claimed only if controller is enabled by another
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+overlay
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+This overlay is required for using chip select 1 with other SPI overlays
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+Due to the u-boot limitations CS1 pin can't be customized by a parameter, but
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+it can be changed by using an edited copy of this overlay
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+A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO)
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+
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+SPI 0 pins (CS1): PA21
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+SPI 1 pins (CS1): PA10
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+
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+### spi-jedec-nor
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+
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+Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
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+supported by the kernel SPI NOR driver
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+
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+SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
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+SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
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+
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+Parameters:
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+
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+param_spinor_spi_bus (int)
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+ SPI bus to activate SPI NOR flash support on
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+ Required
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+ Supported values: 0, 1
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+
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+param_spinor_spi_cs (int)
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+ SPI chip select number
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+ Optional
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+ Default: 0
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+ Supported values: 0, 1
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+ Using chip select 1 requires using "spi-add-cs1" overlay
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+
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+param_spinor_max_freq (int)
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+ Maximum SPI frequency
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+ Optional
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+ Default: 1000000
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+ Range: 3000 - 100000000
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+
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+### spi-spidev
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+
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+Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
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+where X is the bus number and Y is the CS number
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+
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+SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
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+SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
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+
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+Parameters:
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+
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+param_spidev_spi_bus (int)
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+ SPI bus to activate SPIdev support on
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+ Required
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+ Supported values: 0, 1
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+
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+param_spidev_spi_cs (int)
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+ SPI chip select number
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+ Optional
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+ Default: 0
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+ Supported values: 0, 1
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+ Using chip select 1 requires using "spi-add-cs1" overlay
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+
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+param_spidev_max_freq (int)
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+ Maximum SPIdev frequency
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+ Optional
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+ Default: 1000000
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+ Range: 3000 - 100000000
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+
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+### uart1
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+
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+Activates serial port 1 (/dev/ttyS1)
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+
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+UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
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+
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+Parameters:
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+
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+param_uart1_rtscts (bool)
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+ Enable RTS and CTS pins
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+ Optional
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+ Default: 0
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+ Set to 1 to enable
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+
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+### uart2
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+
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+Activates serial port 2 (/dev/ttyS2)
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+
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+UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3
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+
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+Parameters:
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+
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+param_uart2_rtscts (bool)
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+ Enable RTS and CTS pins
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+ Optional
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+ Default: 0
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+ Set to 1 to enable CTS and RTS pins
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+
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+### uart3
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+
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+Activates serial port 3 (/dev/ttyS3)
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+
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+UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16
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+
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+Parameters:
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+
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+param_uart3_rtscts (bool)
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+ Enable RTS and CTS pins
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+ Optional
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+ Default: 0
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+ Set to 1 to enable CTS and RTS pins
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+
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+### usbhost0
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+
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+Activates USB host controller 0
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+
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+### usbhost2
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+
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+Activates USB host controller 2
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+
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+### usbhost3
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+
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+Activates USB host controller 3
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+
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+### w1-gpio
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+
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+Activates 1-Wire GPIO master
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+Requires an external pull-up resistor on the data pin
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+or enabling the internal pull-up
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+
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+Parameters:
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+
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+param_w1_pin (pin)
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+ Data pin for 1-Wire master
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+ Optional
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+ Default: PD14
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+
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+param_w1_pin_int_pullup (bool)
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+ Enable internal pull-up for the data pin
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+ Optional
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+ Default: 0
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+ Set to 1 to enable the pull-up
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+ This option should not be used with multiple devices, parasite power setup
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+ or long wires - please use external pull-up resistor instead
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diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts
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new file mode 100644
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index 00000000..36dbc31a
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts
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@@ -0,0 +1,17 @@
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ compatible = "allwinner,sun8i-h3";
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+
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+ fragment@0 {
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+ target = <&codec>;
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+ __overlay__ {
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+ allwinner,audio-routing =
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+ "Line Out", "LINEOUT",
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+ "MIC1", "Mic",
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+ "Mic", "MBIAS";
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+ status = "okay";
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+ };
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+ };
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+};
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diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts
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new file mode 100644
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index 00000000..9b62fd2b
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts
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@@ -0,0 +1,15 @@
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ compatible = "allwinner,sun8i-h3";
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+
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+ fragment@0 {
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+ target = <&ir>;
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+ __overlay__ {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&ir_pins_a>;
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+ status = "okay";
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+ };
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+ };
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+};
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diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd
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new file mode 100644
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index 00000000..744889c6
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd
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@@ -0,0 +1,110 @@
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+# overlays fixup script
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+# implements (or rather substitutes) overlay arguments functionality
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+# using u-boot scripting, environment variables and "fdt" command
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+
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+# setexpr test_var ${tmp_bank} - A
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+# works only for hex numbers (A-F)
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+
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+setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1";
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+setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
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+test "${tmp_bank}" = "A" && setenv tmp_bank 0;
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+test "${tmp_bank}" = "C" && setenv tmp_bank 2;
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+test "${tmp_bank}" = "D" && setenv tmp_bank 3;
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+test "${tmp_bank}" = "G" && setenv tmp_bank 6'
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+
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+if test -n "${param_spinor_spi_bus}"; then
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+ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@01c68000"
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+ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@01c69000"
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+ fdt set /soc/${tmp_spi_path} status "okay"
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+ fdt set /soc/${tmp_spi_path}/spiflash status "okay"
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+ if test -n "${param_spinor_max_freq}"; then
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+ fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
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+ fi
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+ if test "${param_spinor_spi_cs}" = "1"; then
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+ fdt set /soc/${tmp_spi_path}/spiflash reg "<1>"
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+ fi
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+ env delete tmp_spi_path
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+fi
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+
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+if test -n "${param_spidev_spi_bus}"; then
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+ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@01c68000"
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+ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@01c69000"
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+ fdt set /soc/${tmp_spi_path} status "okay"
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+ fdt set /soc/${tmp_spi_path}/spidev status "okay"
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+ if test -n "${param_spidev_max_freq}"; then
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+ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
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+ fi
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+ if test "${param_spidev_spi_cs}" = "1"; then
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+ fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
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+ fi
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+ env delete tmp_spi_path
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+fi
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+
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+if test -n "${param_pps_pin}"; then
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+ setenv tmp_bank "${param_pps_pin}"
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+ setenv tmp_pin "${param_pps_pin}"
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+ run decompose_pin
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+ fdt set /soc/pinctrl@01c20800/pps_pins pins "${param_pps_pin}"
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+ fdt get value tmp_phandle /soc/pinctrl@01c20800 phandle
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+ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
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+ env delete tmp_pin tmp_bank tmp_phandle
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+fi
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+
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+if test "${param_pps_falling_edge}" = "1"; then
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+ fdt set /pps@0 assert-falling-edge
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+fi
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+
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+for f in ${overlays}; do
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+ if test "${f}" = "pwm"; then
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+ setenv bootargs_new ""
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+ for arg in ${bootargs}; do
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+ if test "${arg}" = "console=ttyS0,115200"; then
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+ echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
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+ else
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+ setenv bootargs_new "${bootargs_new} ${arg}"
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+ fi
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+ done
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+ setenv bootargs "${bootargs_new}"
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+ fi
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+done
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+
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+if test -n "${param_w1_pin}"; then
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+ setenv tmp_bank "${param_w1_pin}"
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+ setenv tmp_pin "${param_w1_pin}"
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+ run decompose_pin
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+ fdt set /soc/pinctrl@01c20800/w1_pins pins "${param_w1_pin}"
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+ fdt get value tmp_phandle /soc/pinctrl@01c20800 phandle
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+ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
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+ env delete tmp_pin tmp_bank tmp_phandle
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+fi
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+
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+if test "${param_w1_pin_int_pullup}" = "1"; then
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+ fdt set /soc/pinctrl@01c20800/w1_pins bias-pull-up
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+fi
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+
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+if test "${param_uart1_rtscts}" = "1"; then
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+ fdt get value tmp_phandle1 /soc/pinctrl@01c20800/uart1 phandle
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+ fdt get value tmp_phandle2 /soc/pinctrl@01c20800/uart1_rts_cts phandle
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+ fdt set /soc/serial@01c28400 pinctrl-names "default" "default"
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+ fdt set /soc/serial@01c28400 pinctrl-0 "<${tmp_phandle1}>"
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+ fdt set /soc/serial@01c28400 pinctrl-1 "<${tmp_phandle2}>"
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+ env delete tmp_phandle1 tmp_phandle2
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+fi
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+
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+if test "${param_uart2_rtscts}" = "1"; then
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+ fdt get value tmp_phandle1 /soc/pinctrl@01c20800/uart2 phandle
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+ fdt get value tmp_phandle2 /soc/pinctrl@01c20800/uart2_rts_cts phandle
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+ fdt set /soc/serial@01c28800 pinctrl-names "default" "default"
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+ fdt set /soc/serial@01c28800 pinctrl-0 "<${tmp_phandle1}>"
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+ fdt set /soc/serial@01c28800 pinctrl-1 "<${tmp_phandle2}>"
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+ env delete tmp_phandle1 tmp_phandle2
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+fi
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+
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+if test "${param_uart3_rtscts}" = "1"; then
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+ fdt get value tmp_phandle1 /soc/pinctrl@01c20800/uart3 phandle
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+ fdt get value tmp_phandle2 /soc/pinctrl@01c20800/uart3_rts_cts phandle
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+ fdt set /soc/serial@01c28c00 pinctrl-names "default" "default"
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+ fdt set /soc/serial@01c28c00 pinctrl-0 "<${tmp_phandle1}>"
|
|
+ fdt set /soc/serial@01c28c00 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+fi
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts
|
|
new file mode 100644
|
|
index 00000000..b457ac71
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts
|
|
@@ -0,0 +1,20 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c0 = "/soc/i2c@01c2ac00";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c0>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts
|
|
new file mode 100644
|
|
index 00000000..fd0928a1
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts
|
|
@@ -0,0 +1,20 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c1 = "/soc/i2c@01c2b000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c1>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts
|
|
new file mode 100644
|
|
index 00000000..25b75b71
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts
|
|
@@ -0,0 +1,20 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c2 = "/soc/i2c@01c2b400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c2>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts
|
|
new file mode 100644
|
|
index 00000000..16a737b0
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts
|
|
@@ -0,0 +1,29 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ pps_pins: pps_pins {
|
|
+ pins = "PD14";
|
|
+ function = "gpio_in";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ pps@0 {
|
|
+ compatible = "pps-gpio";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pps_pins>;
|
|
+ gpios = <&pio 3 14 0>; /* PD14 */
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts
|
|
new file mode 100644
|
|
index 00000000..ed3b8e60
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts
|
|
@@ -0,0 +1,39 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/chosen";
|
|
+ __overlay__ {
|
|
+ /delete-property/ stdout-path;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart0>;
|
|
+ __overlay__ {
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ pwm0_pin: pwm0 {
|
|
+ pins = "PA5";
|
|
+ function = "pwm0";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&pwm>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pwm0_pin>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts
|
|
new file mode 100644
|
|
index 00000000..c7c01411
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts
|
|
@@ -0,0 +1,38 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&spdif>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spdif_tx_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ sound {
|
|
+ compatible = "simple-audio-card";
|
|
+ simple-audio-card,name = "On-board SPDIF";
|
|
+
|
|
+ simple-audio-card,cpu {
|
|
+ sound-dai = <&spdif>;
|
|
+ };
|
|
+
|
|
+ simple-audio-card,codec {
|
|
+ sound-dai = <&spdif_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spdif_out: spdif-out {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "linux,spdif-dit";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts
|
|
new file mode 100644
|
|
index 00000000..bd8e2561
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts
|
|
@@ -0,0 +1,41 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ spi0_cs1: spi0_cs1 {
|
|
+ pins = "PA21";
|
|
+ function = "gpio_out";
|
|
+ output-high;
|
|
+ };
|
|
+
|
|
+ spi1_cs1: spi1_cs1 {
|
|
+ pins = "PA10";
|
|
+ function = "gpio_out";
|
|
+ output-high;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default", "default";
|
|
+ pinctrl-1 = <&spi0_cs1>;
|
|
+ cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default", "default";
|
|
+ pinctrl-1 = <&spi1_cs1>;
|
|
+ cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts
|
|
new file mode 100644
|
|
index 00000000..ad22a71a
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts
|
|
@@ -0,0 +1,42 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc/spi@01c68000";
|
|
+ spi1 = "/soc/spi@01c69000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts
|
|
new file mode 100644
|
|
index 00000000..180979e0
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts
|
|
@@ -0,0 +1,42 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc/spi@01c68000";
|
|
+ spi1 = "/soc/spi@01c69000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev {
|
|
+ compatible = "spidev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev {
|
|
+ compatible = "spidev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts
|
|
new file mode 100644
|
|
index 00000000..8a4f7e49
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial1 = "/soc/serial@01c28400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart1>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart1_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts
|
|
new file mode 100644
|
|
index 00000000..499a1b49
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial2 = "/soc/serial@01c28800";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart2>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart2_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts
|
|
new file mode 100644
|
|
index 00000000..b5734c5b
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial3 = "/soc/serial@01c28c00";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart3>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart3_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts
|
|
new file mode 100644
|
|
index 00000000..ff1d82fd
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts
|
|
@@ -0,0 +1,20 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&ehci0>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&ohci0>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts
|
|
new file mode 100644
|
|
index 00000000..bf0c4f59
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts
|
|
@@ -0,0 +1,20 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&ehci2>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&ohci2>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts
|
|
new file mode 100644
|
|
index 00000000..f737075b
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts
|
|
@@ -0,0 +1,20 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&ehci3>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&ohci3>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts
|
|
new file mode 100644
|
|
index 00000000..f4ccb7fb
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts
|
|
@@ -0,0 +1,29 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ w1_pins: w1_pins {
|
|
+ pins = "PD14";
|
|
+ function = "gpio_in";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ onewire@0 {
|
|
+ compatible = "w1-gpio";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&w1_pins>;
|
|
+ gpios = <&pio 3 14 0>; /* PD14 */
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|