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91 lines
3.4 KiB
Diff
91 lines
3.4 KiB
Diff
From dc42dd038ca95acad010efcb6d11b96752392cfc Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Tue, 1 Aug 2017 21:12:52 +0800
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Subject: [PATCH] dt-bindings: update the binding for Allwinner H3 DE2 support
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Allwinner H3 features a "Display Engine 2.0".
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Add device tree bindings for the following parts:
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- H3 TCONs
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- H3 Mixers
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- H3 Display engine
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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.../bindings/display/sunxi/sun4i-drm.txt | 25 ++++++++++++++++++----
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1 file changed, 21 insertions(+), 4 deletions(-)
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diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
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index 2ee6ff0ef98e7..92512953943e1 100644
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--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
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+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
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@@ -87,18 +87,17 @@ Required properties:
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* allwinner,sun6i-a31-tcon
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* allwinner,sun6i-a31s-tcon
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* allwinner,sun8i-a33-tcon
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+ * allwinner,sun8i-h3-tcon
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* allwinner,sun8i-v3s-tcon
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- reg: base address and size of memory-mapped region
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the TCON. Three are needed:
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- 'ahb': the interface clocks
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- - 'tcon-ch0': The clock driving the TCON channel 0
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- resets: phandles to the reset controllers driving the encoder
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- "lcd": the reset line for the TCON channel 0
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- clock-names: the clock names mentioned above
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- reset-names: the reset names mentioned above
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- - clock-output-names: Name of the pixel clock created
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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@@ -112,7 +111,23 @@ Required properties:
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channel the endpoint is associated to. If that property is not
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present, the endpoint number will be used as the channel number.
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-On SoCs other than the A33 and V3s, there is one more clock required:
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+For the following compatibles:
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+ * allwinner,sun5i-a13-tcon
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+ * allwinner,sun6i-a31-tcon
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+ * allwinner,sun6i-a31s-tcon
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+ * allwinner,sun8i-a33-tcon
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+ * allwinner,sun8i-v3s-tcon
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+there is one more clock and one more property required:
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+ - clocks:
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+ - 'tcon-ch0': The clock driving the TCON channel 0
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+ - clock-output-names: Name of the pixel clock created
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+
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+For the following compatibles:
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+ * allwinner,sun5i-a13-tcon
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+ * allwinner,sun6i-a31-tcon
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+ * allwinner,sun6i-a31s-tcon
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+ * allwinner,sun8i-h3-tcon
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+there is one more clock required:
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- 'tcon-ch1': The clock driving the TCON channel 1
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DRC
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@@ -207,6 +222,8 @@ supported.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun8i-v3s-de2-mixer
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+ * allwinner,sun8i-h3-de2-mixer0
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+ * allwinner,sun8i-h3-de2-mixer1
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- reg: base address and size of the memory-mapped region.
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- clocks: phandles to the clocks feeding the mixer
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* bus: the mixer interface clock
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@@ -218,7 +235,6 @@ Required properties:
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoints, the second one the output
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-
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Display Engine Pipeline
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-----------------------
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@@ -233,6 +249,7 @@ Required properties:
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* allwinner,sun6i-a31-display-engine
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* allwinner,sun6i-a31s-display-engine
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* allwinner,sun8i-a33-display-engine
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+ * allwinner,sun8i-h3-display-engine
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* allwinner,sun8i-v3s-display-engine
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- allwinner,pipelines: list of phandle to the display engine
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