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67 lines
1.8 KiB
Diff
67 lines
1.8 KiB
Diff
From a3e8bf0e49687679382fd76aaad5be49bd65793c Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Mon, 25 Dec 2017 12:10:06 +0800
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Subject: [PATCH 23/35] arm64: allwinner: h6: add USB3 device nodes
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Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
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a custom PHY.
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Add device tree nodes for them.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 38 ++++++++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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index f3ca411..b3d8da4 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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@@ -233,6 +233,44 @@
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status = "disabled";
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};
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+ usb3: usb@5200000 {
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+ compatible = "allwinner,sun50i-h6-dwc3";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ clocks = <&ccu CLK_BUS_XHCI>;
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+ clock-names = "bus";
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+ resets = <&ccu RST_BUS_XHCI>;
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+ reset-names = "bus";
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+ status = "disabled";
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+
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+ dwc3: dwc3 {
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+ compatible = "snps,dwc3";
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+ reg = <0x5200000 0x10000>;
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+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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+ /*
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+ * According to Wink from Allwinner, the
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+ * USB3 port on H6 is not capable of OTG;
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+ * the datasheet doesn't mention OTG at all
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+ * either, so the dr_mode is default to
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+ * "host" here.
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+ */
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+ dr_mode = "host";
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+ phys = <&usb3phy>;
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+ phy-names = "usb3-phy";
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+ status = "disabled";
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+ };
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+ };
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+
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+ usb3phy: phy@5210000 {
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+ compatible = "allwinner,sun50i-h6-usb3-phy";
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+ reg = <0x5210000 0x10000>;
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+ clocks = <&ccu CLK_USB_PHY1>;
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+ resets = <&ccu RST_USB_PHY1>;
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+
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r_ccu: clock@7010000 {
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compatible = "allwinner,sun50i-h6-r-ccu";
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reg = <0x07010000 0x400>;
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--
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2.7.4
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