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95 lines
3.3 KiB
Diff
95 lines
3.3 KiB
Diff
From 92e5c7876cef2b53ed3d1701169fcd93b73e0e33 Mon Sep 17 00:00:00 2001
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From: Philipp Rossak <embed3d@gmail.com>
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Date: Sat, 20 Jan 2018 13:25:21 +0100
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Subject: [PATCH 009/146] dt-bindings: update the Allwinner GPADC device tree
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binding for H3 & A83T
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Allwinner H3 features a thermal sensor like the one in A33, but has its
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register re-arranged, the clock divider moved to CCU (originally the
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clock divider is in ADC) and added a pair of bus clock and reset.
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Allwinner A83T features a thermal sensor similar to the H3, the ths clock,
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the bus clock and the reset was removed from the CCU. The THS in A83T
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has a clock that is directly connected and runs with 24 MHz.
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Update the binding document to cover H3 and A83T.
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Signed-off-by: Philipp Rossak <embed3d@gmail.com>
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---
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.../devicetree/bindings/mfd/sun4i-gpadc.txt | 50 +++++++++++++++++--
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1 file changed, 47 insertions(+), 3 deletions(-)
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diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
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index 86dd8191b04c..f6b939617a6d 100644
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--- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
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+++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
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@@ -4,12 +4,35 @@ The Allwinner SoCs all have an ADC that can also act as a thermal sensor
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and sometimes as a touchscreen controller.
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Required properties:
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- - compatible: "allwinner,sun8i-a33-ths",
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+ - compatible: must contain one of the following compatibles:
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+ - "allwinner,sun8i-a33-ths"
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+ - "allwinner,sun8i-h3-ths"
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+ - "allwinner,sun8i-a83t-ths"
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- reg: mmio address range of the chip,
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- - #thermal-sensor-cells: shall be 0,
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+ - #thermal-sensor-cells: shall be 0 or 1,
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- #io-channel-cells: shall be 0,
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-Example:
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+Required properties for the following compatibles:
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+ - "allwinner,sun8i-h3-ths"
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+ - "allwinner,sun8i-a83t-ths"
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+ - interrupts: the sampling interrupt of the ADC,
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+
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+Required properties for the following compatibles:
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+ - "allwinner,sun8i-h3-ths"
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+ - clocks: the bus clock and the input clock of the ADC,
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+ - clock-names: should be "bus" and "mod",
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+ - resets: the bus reset of the ADC,
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+
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+Optional properties for the following compatibles:
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+ - "allwinner,sun8i-h3-ths"
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+ - nvmem-cells: A phandle to the calibration data provided by a nvmem device.
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+ If unspecified default values shall be used. The size should
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+ be 0x4 or 0x8, depending on the amount of CDATA registers.
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+ - nvmem-cell-names: Should be "calibration".
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+
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+Details see: bindings/nvmem/nvmem.txt
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+
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+Example for A33:
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ths: ths@1c25000 {
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compatible = "allwinner,sun8i-a33-ths";
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reg = <0x01c25000 0x100>;
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@@ -17,6 +40,27 @@ Example:
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#io-channel-cells = <0>;
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};
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+Example for H3:
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+ ths: thermal-sensor@1c25000 {
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+ compatible = "allwinner,sun8i-h3-ths";
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+ reg = <0x01c25000 0x400>;
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+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
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+ clock-names = "bus", "mod";
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+ resets = <&ccu RST_BUS_THS>;
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+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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+ #thermal-sensor-cells = <0>;
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+ #io-channel-cells = <0>;
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+ };
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+
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+Example for A83T:
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+ ths: thermal-sensor@1f04000 {
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+ compatible = "allwinner,sun8i-a83t-ths";
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+ reg = <0x01f04000 0x100>;
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+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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+ #thermal-sensor-cells = <1>;
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+ #io-channel-cells = <0>;
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+ };
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+
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sun4i, sun5i and sun6i SoCs are also supported via the older binding:
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sun4i resistive touchscreen controller
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--
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2.17.1
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