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221 lines
5.4 KiB
Diff
221 lines
5.4 KiB
Diff
From 38727062e2758832418fbf250f327e5e916f877e Mon Sep 17 00:00:00 2001
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From: Jagan Teki <jagan@amarulasolutions.com>
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Date: Tue, 4 Sep 2018 12:40:50 +0800
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Subject: [PATCH 098/146] arm64: dts: allwinner: a64: Add display pipeline
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Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first
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TCON is connected to LCD and the second is to HDMI.
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The HDMI controller/PHY pair is similar to the one on H3/H5.
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Add all required device tree nodes of the display pipeline, including
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the TCON0 LCD one and the TCON1 HDMI one.
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Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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[Icenowy: refactor commit message and add 1st pipeline]
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 166 ++++++++++++++++++
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1 file changed, 166 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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index 73f7e69755f8..132da408aa52 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -166,6 +166,13 @@
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};
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};
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+ de: display-engine {
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+ compatible = "allwinner,sun50i-a64-display-engine";
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+ allwinner,pipelines = <&mixer0>,
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+ <&mixer1>;
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+ status = "disabled";
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+ };
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+
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@@ -317,6 +324,52 @@
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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+
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+ mixer0: mixer@100000 {
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+ compatible = "allwinner,sun50i-a64-de2-mixer-0";
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+ reg = <0x100000 0x100000>;
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+ clocks = <&display_clocks CLK_BUS_MIXER0>,
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+ <&display_clocks CLK_MIXER0>;
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+ clock-names = "bus",
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+ "mod";
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+ resets = <&display_clocks RST_MIXER0>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mixer0_out: port@1 {
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+ reg = <1>;
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+
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+ mixer0_out_tcon0: endpoint {
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+ remote-endpoint = <&tcon0_in_mixer0>;
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+ };
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+ };
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+ };
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+ };
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+
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+ mixer1: mixer@200000 {
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+ compatible = "allwinner,sun50i-a64-de2-mixer-1";
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+ reg = <0x200000 0x100000>;
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+ clocks = <&display_clocks CLK_BUS_MIXER1>,
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+ <&display_clocks CLK_MIXER1>;
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+ clock-names = "bus",
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+ "mod";
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+ resets = <&display_clocks RST_MIXER1>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mixer1_out: port@1 {
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+ reg = <1>;
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+
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+ mixer1_out_tcon1: endpoint {
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+ remote-endpoint = <&tcon1_in_mixer1>;
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+ };
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+ };
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+ };
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+ };
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};
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syscon: syscon@1c00000 {
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@@ -351,6 +404,75 @@
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#dma-cells = <1>;
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};
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+ tcon0: lcd-controller@1c0c000 {
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+ compatible = "allwinner,sun50i-a64-tcon-lcd",
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+ "allwinner,sun8i-a83t-tcon-lcd";
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+ reg = <0x01c0c000 0x1000>;
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+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
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+ clock-names = "ahb", "tcon-ch0";
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+ clock-output-names = "tcon-pixel-clock";
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+ resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
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+ reset-names = "lcd", "lvds";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ tcon0_in: port@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+
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+ tcon0_in_mixer0: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&mixer0_out_tcon0>;
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+ };
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+ };
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+
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+ tcon0_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+ };
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+ };
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+ };
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+
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+ tcon1: lcd-controller@1c0d000 {
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+ compatible = "allwinner,sun50i-a64-tcon-tv",
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+ "allwinner,sun8i-a83t-tcon-tv";
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+ reg = <0x01c0d000 0x1000>;
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+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
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+ clock-names = "ahb", "tcon-ch1";
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+ resets = <&ccu RST_BUS_TCON1>;
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+ reset-names = "lcd";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ tcon1_in: port@0 {
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+ reg = <0>;
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+
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+ tcon1_in_mixer1: endpoint {
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+ remote-endpoint = <&mixer1_out_tcon1>;
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+ };
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+ };
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+
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+ tcon1_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+
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+ tcon1_out_hdmi: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&hdmi_in_tcon1>;
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+ };
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+ };
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+ };
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+ };
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+
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c0f000 0x1000>;
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@@ -860,6 +982,50 @@
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status = "disabled";
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};
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+ hdmi: hdmi@1ee0000 {
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+ compatible = "allwinner,sun50i-a64-dw-hdmi",
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+ "allwinner,sun8i-a83t-dw-hdmi";
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+ reg = <0x01ee0000 0x10000>;
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+ reg-io-width = <1>;
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+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
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+ <&ccu CLK_HDMI>;
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+ clock-names = "iahb", "isfr", "tmds";
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+ resets = <&ccu RST_BUS_HDMI1>;
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+ reset-names = "ctrl";
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+ phys = <&hdmi_phy>;
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+ phy-names = "hdmi-phy";
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ hdmi_in: port@0 {
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+ reg = <0>;
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+
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+ hdmi_in_tcon1: endpoint {
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+ remote-endpoint = <&tcon1_out_hdmi>;
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+ };
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+ };
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+
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+ hdmi_out: port@1 {
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+ reg = <1>;
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+ };
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+ };
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+ };
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+
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+ hdmi_phy: hdmi-phy@1ef0000 {
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+ compatible = "allwinner,sun8i-h3-hdmi-phy";
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+ reg = <0x01ef0000 0x10000>;
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+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
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+ <&ccu 7>;
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+ clock-names = "bus", "mod", "pll-0";
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+ resets = <&ccu RST_BUS_HDMI0>;
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+ reset-names = "phy";
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+ #phy-cells = <0>;
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+ };
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+
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sound_hdmi: sound_hdmi {
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compatible = "simple-audio-card";
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simple-audio-card,format = "i2s";
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--
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2.17.1
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