mirror of
https://github.com/Fishwaldo/build.git
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a57ce78b37
* Bump to 4.18, removing the obvious, fixing build problems, put some on waiting. * Pin 4.18 to DEV, rollback 4.14 to NEXT, adjust configs, remove one deprecated patch from NEXT and add board-h3-address-some-stability-issues.patch * Adjust few boards in development to new reality, removing it from NEXT for now * Adjust few board configs * Board config adjustement * Adjust few boards configs * Port NeoCore2 and Neo21.1 to 4.14.y * Adjust board config * Adjust board config
76 lines
2 KiB
Diff
76 lines
2 KiB
Diff
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
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index b36f9f42..de8cfb13 100644
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -43,6 +43,71 @@
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#include "sunxi-h3-h5.dtsi"
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/ {
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+ cpu_opp_table: opp_table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp@240000000 {
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+ opp-hz = /bits/ 64 <240000000>;
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+ opp-microvolt = <980000 980000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@480000000 {
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+ opp-hz = /bits/ 64 <480000000>;
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+ opp-microvolt = <980000 980000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@648000000 {
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+ opp-hz = /bits/ 64 <648000000>;
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+ opp-microvolt = <1000000 1000000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@816000000 {
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+ opp-hz = /bits/ 64 <816000000>;
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+ opp-microvolt = <1020000 1020000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@912000000 {
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+ opp-hz = /bits/ 64 <912000000>;
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+ opp-microvolt = <1040000 1040000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@960000000 {
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+ opp-hz = /bits/ 64 <960000000>;
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+ opp-microvolt = <1080000 1080000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <1140000 1140000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <1180000 1180000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1240000 1240000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1296000000 {
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+ opp-hz = /bits/ 64 <1296000000>;
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+ opp-microvolt = <1320000 1320000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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