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* sunxi: kernel: current/dev: enable sun6i-csi and disable LL debug on UART0 The former is useful on some boards, e.g. PineCube. The latter blocks boards that do not utilize UART0 from booting. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> * sunxi: add new family sun8i-v3s This family is intended for boards with V3/V3s/S3/S3L chips and low DRAM capacity. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> * sunxi: add PineCube board This board features Sochip S3 SoC (Allwinner V3 die + co-packaged 128MiB DRAM), and an OmniVision OV5640 camera is shipped with the board. Add support for it. It could be used as an IP camera then. Kernel support is only added to current/dev branch, with dev just using mainline-merged DT and current using backported DT from 5.10-rc. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> * sunxi: kernel: current/dev: add V3s OHCI/EHCI nodes These are needed for USB host on V3s boards to work. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
152 lines
3.8 KiB
Diff
152 lines
3.8 KiB
Diff
From bdbf0a1cb3c23e69ddff2a2c1c3202455b248afc Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Wed, 16 Aug 2017 12:37:30 +0800
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Subject: [PATCH 1/3] ARM: dts: sun8i: v3s: add EHCI/OHCI0 device nodes
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The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
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controllers.
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Add the device nodes for the controllers.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++
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1 file changed, 19 insertions(+)
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diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
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index 7b2d684aeb97..3e7e99745b73 100644
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--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
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+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
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@@ -297,6 +297,25 @@ usbphy: phy@1c19400 {
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#phy-cells = <1>;
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};
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+ ehci0: usb@1c1a000 {
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+ compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
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+ reg = <0x01c1a000 0x100>;
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+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
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+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
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+ status = "disabled";
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+ };
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+
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+ ohci0: usb@1c1a400 {
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+ compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
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+ reg = <0x01c1a400 0x100>;
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+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
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+ <&ccu CLK_USB_OHCI0>;
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+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
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+ status = "disabled";
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+ };
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+
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ccu: clock@1c20000 {
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compatible = "allwinner,sun8i-v3s-ccu";
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reg = <0x01c20000 0x400>;
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--
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2.28.0
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From 7c23b1d9d8140c97ffcfe5714467a6dc23462b32 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Wed, 16 Aug 2017 12:38:25 +0800
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Subject: [PATCH 2/3] ARM: dts: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero
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As the USB port on Lichee Pi Zero works in the OTG mode, enable the
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EHCI/OHCI controllers for it.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
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index 2e4587d26ce5..0cd969194acb 100644
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--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
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+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
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@@ -77,6 +77,10 @@ red_led {
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};
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};
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+&ehci0 {
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+ status = "okay";
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+};
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+
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&mmc0 {
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broken-cd;
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bus-width = <4>;
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@@ -84,6 +88,10 @@ &mmc0 {
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status = "okay";
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};
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+&ohci0 {
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+ status = "okay";
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+};
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+
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&uart0 {
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pinctrl-0 = <&uart0_pb_pins>;
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pinctrl-names = "default";
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--
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2.28.0
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From 845ece80db17cca5e205a14bb07bc428f0035c14 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Sun, 22 Nov 2020 08:25:35 +0800
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Subject: [PATCH 3/3] ARM: dts: sun8i: s3: switch PineCube to use OHCI/EHCI
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only
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The PineCube board features a USB Type-A connector connected to the
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SoC's USB pins.
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As this is not designed for being used as a USB device, disable OTG
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controller and route USB to OHCI/EHCI fixedly.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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arch/arm/boot/dts/sun8i-s3-pinecube.dts | 17 ++++++++++++-----
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1 file changed, 12 insertions(+), 5 deletions(-)
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diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
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index 4aa0ee897a0a..c4177c54ef29 100644
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--- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts
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+++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
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@@ -78,6 +78,12 @@ csi1_ep: endpoint {
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};
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};
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+&ehci0 {
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+ phys = <&usbphy 0>;
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+ phy-names = "usb";
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+ status = "okay";
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+};
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+
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&emac {
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phy-handle = <&int_mii_phy>;
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phy-mode = "mii";
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@@ -158,6 +164,12 @@ &mmc1 {
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status = "okay";
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};
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+&ohci0 {
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+ phys = <&usbphy 0>;
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+ phy-names = "usb";
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+ status = "okay";
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+};
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+
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&pio {
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vcc-pd-supply = <®_dcdc3>;
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vcc-pe-supply = <®_ldo3>;
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@@ -224,11 +236,6 @@ &uart2 {
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status = "okay";
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};
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-&usb_otg {
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- dr_mode = "host";
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- status = "okay";
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-};
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-
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&usbphy {
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usb0_vbus-supply = <®_vcc5v0>;
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status = "okay";
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--
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2.28.0
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