mirror of
https://github.com/Fishwaldo/build.git
synced 2025-03-29 10:11:23 +00:00
201 lines
6 KiB
Diff
201 lines
6 KiB
Diff
diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
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index 9918a57..64be5aa 100644
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--- a/drivers/spi/spi-sun6i.c
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+++ b/drivers/spi/spi-sun6i.c
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@@ -17,6 +17,7 @@
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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+#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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@@ -24,6 +25,7 @@
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#include <linux/spi/spi.h>
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#define SUN6I_FIFO_DEPTH 128
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+#define SUN8I_FIFO_DEPTH 64
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#define SUN6I_GBL_CTL_REG 0x04
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#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
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@@ -44,6 +46,8 @@
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#define SUN6I_TFR_CTL_XCH BIT(31)
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#define SUN6I_INT_CTL_REG 0x10
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+#define SUN6I_INT_CTL_RF_FUL BIT(2)
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+#define SUN6I_INT_CTL_TF_EMP BIT(5)
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#define SUN6I_INT_CTL_RF_OVF BIT(8)
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#define SUN6I_INT_CTL_TC BIT(12)
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@@ -66,11 +70,13 @@
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#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
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#define SUN6I_CLK_CTL_DRS BIT(12)
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+#define SUN6I_MAX_XFER_SIZE 0xffffff
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+
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#define SUN6I_BURST_CNT_REG 0x30
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-#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff)
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+#define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
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#define SUN6I_XMIT_CNT_REG 0x34
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-#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
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+#define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
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#define SUN6I_BURST_CTL_CNT_REG 0x38
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#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff)
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@@ -90,6 +96,7 @@ struct sun6i_spi {
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const u8 *tx_buf;
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u8 *rx_buf;
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int len;
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+ unsigned long fifo_depth;
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};
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static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
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@@ -102,6 +109,31 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
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writel(value, sspi->base_addr + reg);
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}
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+static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
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+{
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+ u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
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+
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+ reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;
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+
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+ return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
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+}
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+
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+static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
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+{
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+ u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
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+
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+ reg |= mask;
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+ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
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+}
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+
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+static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
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+{
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+ u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
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+
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+ reg &= ~mask;
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+ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
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+}
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+
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static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
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{
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u32 reg, cnt;
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@@ -124,10 +156,13 @@ static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
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static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
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{
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+ u32 cnt;
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u8 byte;
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- if (len > sspi->len)
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- len = sspi->len;
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+ /* See how much data we can fit */
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+ cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
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+
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+ len = min3(len, (int)cnt, sspi->len);
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while (len--) {
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byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
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@@ -155,7 +190,7 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
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static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
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{
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- return SUN6I_FIFO_DEPTH - 1;
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+ return SUN6I_MAX_XFER_SIZE - 1;
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}
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static int sun6i_spi_transfer_one(struct spi_master *master,
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@@ -169,8 +204,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
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int ret = 0;
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u32 reg;
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- /* We don't support transfer larger than the FIFO */
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- if (tfr->len > SUN6I_FIFO_DEPTH)
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+ if (tfr->len > SUN6I_MAX_XFER_SIZE)
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return -EINVAL;
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reinit_completion(&sspi->done);
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@@ -265,10 +299,16 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
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SUN6I_BURST_CTL_CNT_STC(tx_len));
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/* Fill the TX FIFO */
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- sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
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+ sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
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/* Enable the interrupts */
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- sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
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+ /* Only enable Tx FIFO interrupt if we really need it */
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+ if (tx_len > sspi->fifo_depth)
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+ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG,
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+ SUN6I_INT_CTL_TC | SUN6I_INT_CTL_RF_FUL | SUN6I_INT_CTL_TF_EMP);
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+ else
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+ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG,
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+ SUN6I_INT_CTL_TC | SUN6I_INT_CTL_RF_FUL);
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/* Start the transfer */
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reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
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@@ -288,8 +328,6 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
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goto out;
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}
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- sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
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-
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out:
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
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@@ -304,10 +342,33 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
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/* Transfer complete */
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if (status & SUN6I_INT_CTL_TC) {
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sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
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+ sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
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complete(&sspi->done);
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return IRQ_HANDLED;
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}
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+ /* Receive FIFO Full */
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+ if (status & SUN6I_INT_CTL_RF_FUL) {
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+ sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
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+ /* Only clear the interrupt _after_ draining the FIFO */
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+ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_FUL);
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+ return IRQ_HANDLED;
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+ }
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+
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+ /* Transmit FIFO Empty */
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+ if (status & SUN6I_INT_CTL_TF_EMP) {
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+ sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
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+
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+ if (!sspi->len)
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+ /* nothing left to transmit */
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+ sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_EMP);
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+
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+ /* Only clear the interrupt _after_ re-seeding the FIFO */
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+ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_EMP);
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+
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+ return IRQ_HANDLED;
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+ }
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+
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return IRQ_NONE;
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}
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@@ -398,6 +459,8 @@ static int sun6i_spi_probe(struct platform_device *pdev)
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}
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sspi->master = master;
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+ sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
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+
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master->max_speed_hz = 100 * 1000 * 1000;
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master->min_speed_hz = 3 * 1000;
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master->set_cs = sun6i_spi_set_cs;
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@@ -470,7 +533,8 @@ static int sun6i_spi_remove(struct platform_device *pdev)
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}
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static const struct of_device_id sun6i_spi_match[] = {
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- { .compatible = "allwinner,sun6i-a31-spi", },
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+ { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
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+ { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
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{}
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};
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MODULE_DEVICE_TABLE(of, sun6i_spi_match);
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